arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/soc/qcom,apr.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         memory {
  20                 device_type = "memory";
  21                 /* We expect the bootloader to fill in the reg */
  22                 reg = <0 0 0 0>;
  23         };
  24
  25         reserved-memory {
  26                 #address-cells = <2>;
  27                 #size-cells = <2>;
  28                 ranges;
  29
  30                 mba_region: mba@91500000 {
  31                         reg = <0x0 0x91500000 0x0 0x200000>;
  32                         no-map;
  33                 };
  34
  35                 slpi_region: slpi@90b00000 {
  36                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  37                         no-map;
  38                 };
  39
  40                 venus_region: venus@90400000 {
  41                         reg = <0x0 0x90400000 0x0 0x700000>;
  42                         no-map;
  43                 };
  44
  45                 adsp_region: adsp@8ea00000 {
  46                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  47                         no-map;
  48                 };
  49
  50                 mpss_region: mpss@88800000 {
  51                         reg = <0x0 0x88800000 0x0 0x6200000>;
  52                         no-map;
  53                 };
  54
  55                 smem_mem: smem-mem@86000000 {
  56                         reg = <0x0 0x86000000 0x0 0x200000>;
  57                         no-map;
  58                 };
  59
  60                 memory@85800000 {
  61                         reg = <0x0 0x85800000 0x0 0x800000>;
  62                         no-map;
  63                 };
  64
  65                 memory@86200000 {
  66                         reg = <0x0 0x86200000 0x0 0x2600000>;
  67                         no-map;
  68                 };
  69
  70                 rmtfs@86700000 {
  71                         compatible = "qcom,rmtfs-mem";
  72
  73                         size = <0x0 0x200000>;
  74                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  75                         no-map;
  76
  77                         qcom,client-id = <1>;
  78                         qcom,vmid = <15>;
  79                 };
  80
  81                 zap_shader_region: gpu@8f200000 {
  82                         compatible = "shared-dma-pool";
  83                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  84                         no-map;
  85                 };
  86         };
  87
  88         cpus {
  89                 #address-cells = <2>;
  90                 #size-cells = <0>;
  91
  92                 CPU0: cpu@0 {
  93                         device_type = "cpu";
  94                         compatible = "qcom,kryo";
  95                         reg = <0x0 0x0>;
  96                         enable-method = "psci";
  97                         cpu-idle-states = <&CPU_SLEEP_0>;
  98                         capacity-dmips-mhz = <1024>;
  99                         next-level-cache = <&L2_0>;
 100                         L2_0: l2-cache {
 101                               compatible = "cache";
 102                               cache-level = <2>;
 103                         };
 104                 };
 105
 106                 CPU1: cpu@1 {
 107                         device_type = "cpu";
 108                         compatible = "qcom,kryo";
 109                         reg = <0x0 0x1>;
 110                         enable-method = "psci";
 111                         cpu-idle-states = <&CPU_SLEEP_0>;
 112                         capacity-dmips-mhz = <1024>;
 113                         next-level-cache = <&L2_0>;
 114                 };
 115
 116                 CPU2: cpu@100 {
 117                         device_type = "cpu";
 118                         compatible = "qcom,kryo";
 119                         reg = <0x0 0x100>;
 120                         enable-method = "psci";
 121                         cpu-idle-states = <&CPU_SLEEP_0>;
 122                         capacity-dmips-mhz = <1024>;
 123                         next-level-cache = <&L2_1>;
 124                         L2_1: l2-cache {
 125                               compatible = "cache";
 126                               cache-level = <2>;
 127                         };
 128                 };
 129
 130                 CPU3: cpu@101 {
 131                         device_type = "cpu";
 132                         compatible = "qcom,kryo";
 133                         reg = <0x0 0x101>;
 134                         enable-method = "psci";
 135                         cpu-idle-states = <&CPU_SLEEP_0>;
 136                         capacity-dmips-mhz = <1024>;
 137                         next-level-cache = <&L2_1>;
 138                 };
 139
 140                 cpu-map {
 141                         cluster0 {
 142                                 core0 {
 143                                         cpu = <&CPU0>;
 144                                 };
 145
 146                                 core1 {
 147                                         cpu = <&CPU1>;
 148                                 };
 149                         };
 150
 151                         cluster1 {
 152                                 core0 {
 153                                         cpu = <&CPU2>;
 154                                 };
 155
 156                                 core1 {
 157                                         cpu = <&CPU3>;
 158                                 };
 159                         };
 160                 };
 161
 162                 idle-states {
 163                         entry-method = "psci";
 164
 165                         CPU_SLEEP_0: cpu-sleep-0 {
 166                                 compatible = "arm,idle-state";
 167                                 idle-state-name = "standalone-power-collapse";
 168                                 arm,psci-suspend-param = <0x00000004>;
 169                                 entry-latency-us = <130>;
 170                                 exit-latency-us = <80>;
 171                                 min-residency-us = <300>;
 172                         };
 173                 };
 174         };
 175
 176         thermal-zones {
 177                 cpu0-thermal {
 178                         polling-delay-passive = <250>;
 179                         polling-delay = <1000>;
 180
 181                         thermal-sensors = <&tsens0 3>;
 182
 183                         trips {
 184                                 cpu0_alert0: trip-point@0 {
 185                                         temperature = <75000>;
 186                                         hysteresis = <2000>;
 187                                         type = "passive";
 188                                 };
 189
 190                                 cpu0_crit: cpu_crit {
 191                                         temperature = <110000>;
 192                                         hysteresis = <2000>;
 193                                         type = "critical";
 194                                 };
 195                         };
 196                 };
 197
 198                 cpu1-thermal {
 199                         polling-delay-passive = <250>;
 200                         polling-delay = <1000>;
 201
 202                         thermal-sensors = <&tsens0 5>;
 203
 204                         trips {
 205                                 cpu1_alert0: trip-point@0 {
 206                                         temperature = <75000>;
 207                                         hysteresis = <2000>;
 208                                         type = "passive";
 209                                 };
 210
 211                                 cpu1_crit: cpu_crit {
 212                                         temperature = <110000>;
 213                                         hysteresis = <2000>;
 214                                         type = "critical";
 215                                 };
 216                         };
 217                 };
 218
 219                 cpu2-thermal {
 220                         polling-delay-passive = <250>;
 221                         polling-delay = <1000>;
 222
 223                         thermal-sensors = <&tsens0 8>;
 224
 225                         trips {
 226                                 cpu2_alert0: trip-point@0 {
 227                                         temperature = <75000>;
 228                                         hysteresis = <2000>;
 229                                         type = "passive";
 230                                 };
 231
 232                                 cpu2_crit: cpu_crit {
 233                                         temperature = <110000>;
 234                                         hysteresis = <2000>;
 235                                         type = "critical";
 236                                 };
 237                         };
 238                 };
 239
 240                 cpu3-thermal {
 241                         polling-delay-passive = <250>;
 242                         polling-delay = <1000>;
 243
 244                         thermal-sensors = <&tsens0 10>;
 245
 246                         trips {
 247                                 cpu3_alert0: trip-point@0 {
 248                                         temperature = <75000>;
 249                                         hysteresis = <2000>;
 250                                         type = "passive";
 251                                 };
 252
 253                                 cpu3_crit: cpu_crit {
 254                                         temperature = <110000>;
 255                                         hysteresis = <2000>;
 256                                         type = "critical";
 257                                 };
 258                         };
 259                 };
 260
 261                 gpu-thermal-top {
 262                         polling-delay-passive = <250>;
 263                         polling-delay = <1000>;
 264
 265                         thermal-sensors = <&tsens1 6>;
 266
 267                         trips {
 268                                 gpu1_alert0: trip-point@0 {
 269                                         temperature = <90000>;
 270                                         hysteresis = <2000>;
 271                                         type = "hot";
 272                                 };
 273                         };
 274                 };
 275
 276                 gpu-thermal-bottom {
 277                         polling-delay-passive = <250>;
 278                         polling-delay = <1000>;
 279
 280                         thermal-sensors = <&tsens1 7>;
 281
 282                         trips {
 283                                 gpu2_alert0: trip-point@0 {
 284                                         temperature = <90000>;
 285                                         hysteresis = <2000>;
 286                                         type = "hot";
 287                                 };
 288                         };
 289                 };
 290
 291                 m4m-thermal {
 292                         polling-delay-passive = <250>;
 293                         polling-delay = <1000>;
 294
 295                         thermal-sensors = <&tsens0 1>;
 296
 297                         trips {
 298                                 m4m_alert0: trip-point@0 {
 299                                         temperature = <90000>;
 300                                         hysteresis = <2000>;
 301                                         type = "hot";
 302                                 };
 303                         };
 304                 };
 305
 306                 l3-or-venus-thermal {
 307                         polling-delay-passive = <250>;
 308                         polling-delay = <1000>;
 309
 310                         thermal-sensors = <&tsens0 2>;
 311
 312                         trips {
 313                                 l3_or_venus_alert0: trip-point@0 {
 314                                         temperature = <90000>;
 315                                         hysteresis = <2000>;
 316                                         type = "hot";
 317                                 };
 318                         };
 319                 };
 320
 321                 cluster0-l2-thermal {
 322                         polling-delay-passive = <250>;
 323                         polling-delay = <1000>;
 324
 325                         thermal-sensors = <&tsens0 7>;
 326
 327                         trips {
 328                                 cluster0_l2_alert0: trip-point@0 {
 329                                         temperature = <90000>;
 330                                         hysteresis = <2000>;
 331                                         type = "hot";
 332                                 };
 333                         };
 334                 };
 335
 336                 cluster1-l2-thermal {
 337                         polling-delay-passive = <250>;
 338                         polling-delay = <1000>;
 339
 340                         thermal-sensors = <&tsens0 12>;
 341
 342                         trips {
 343                                 cluster1_l2_alert0: trip-point@0 {
 344                                         temperature = <90000>;
 345                                         hysteresis = <2000>;
 346                                         type = "hot";
 347                                 };
 348                         };
 349                 };
 350
 351                 camera-thermal {
 352                         polling-delay-passive = <250>;
 353                         polling-delay = <1000>;
 354
 355                         thermal-sensors = <&tsens1 1>;
 356
 357                         trips {
 358                                 camera_alert0: trip-point@0 {
 359                                         temperature = <90000>;
 360                                         hysteresis = <2000>;
 361                                         type = "hot";
 362                                 };
 363                         };
 364                 };
 365
 366                 q6-dsp-thermal {
 367                         polling-delay-passive = <250>;
 368                         polling-delay = <1000>;
 369
 370                         thermal-sensors = <&tsens1 2>;
 371
 372                         trips {
 373                                 q6_dsp_alert0: trip-point@0 {
 374                                         temperature = <90000>;
 375                                         hysteresis = <2000>;
 376                                         type = "hot";
 377                                 };
 378                         };
 379                 };
 380
 381                 mem-thermal {
 382                         polling-delay-passive = <250>;
 383                         polling-delay = <1000>;
 384
 385                         thermal-sensors = <&tsens1 3>;
 386
 387                         trips {
 388                                 mem_alert0: trip-point@0 {
 389                                         temperature = <90000>;
 390                                         hysteresis = <2000>;
 391                                         type = "hot";
 392                                 };
 393                         };
 394                 };
 395
 396                 modemtx-thermal {
 397                         polling-delay-passive = <250>;
 398                         polling-delay = <1000>;
 399
 400                         thermal-sensors = <&tsens1 4>;
 401
 402                         trips {
 403                                 modemtx_alert0: trip-point@0 {
 404                                         temperature = <90000>;
 405                                         hysteresis = <2000>;
 406                                         type = "hot";
 407                                 };
 408                         };
 409                 };
 410         };
 411
 412         timer {
 413                 compatible = "arm,armv8-timer";
 414                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 415                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 416                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 417                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 418         };
 419
 420         clocks {
 421                 xo_board: xo_board {
 422                         compatible = "fixed-clock";
 423                         #clock-cells = <0>;
 424                         clock-frequency = <19200000>;
 425                         clock-output-names = "xo_board";
 426                 };
 427
 428                 sleep_clk: sleep_clk {
 429                         compatible = "fixed-clock";
 430                         #clock-cells = <0>;
 431                         clock-frequency = <32764>;
 432                         clock-output-names = "sleep_clk";
 433                 };
 434         };
 435
 436         psci {
 437                 compatible = "arm,psci-1.0";
 438                 method = "smc";
 439         };
 440
 441         firmware {
 442                 scm {
 443                         compatible = "qcom,scm-msm8996";
 444
 445                         qcom,dload-mode = <&tcsr 0x13000>;
 446                 };
 447         };
 448
 449         tcsr_mutex: hwlock {
 450                 compatible = "qcom,tcsr-mutex";
 451                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 452                 #hwlock-cells = <1>;
 453         };
 454
 455         smem {
 456                 compatible = "qcom,smem";
 457                 memory-region = <&smem_mem>;
 458                 hwlocks = <&tcsr_mutex 3>;
 459         };
 460
 461         rpm-glink {
 462                 compatible = "qcom,glink-rpm";
 463
 464                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 465
 466                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 467
 468                 mboxes = <&apcs_glb 0>;
 469
 470                 rpm_requests {
 471                         compatible = "qcom,rpm-msm8996";
 472                         qcom,glink-channels = "rpm_requests";
 473
 474                         rpmcc: qcom,rpmcc {
 475                                 compatible = "qcom,rpmcc-msm8996";
 476                                 #clock-cells = <1>;
 477                         };
 478
 479                         rpmpd: power-controller {
 480                                 compatible = "qcom,msm8996-rpmpd";
 481                                 #power-domain-cells = <1>;
 482                                 operating-points-v2 = <&rpmpd_opp_table>;
 483
 484                                 rpmpd_opp_table: opp-table {
 485                                         compatible = "operating-points-v2";
 486
 487                                         rpmpd_opp1: opp1 {
 488                                                 opp-level = <1>;
 489                                         };
 490
 491                                         rpmpd_opp2: opp2 {
 492                                                 opp-level = <2>;
 493                                         };
 494
 495                                         rpmpd_opp3: opp3 {
 496                                                 opp-level = <3>;
 497                                         };
 498
 499                                         rpmpd_opp4: opp4 {
 500                                                 opp-level = <4>;
 501                                         };
 502
 503                                         rpmpd_opp5: opp5 {
 504                                                 opp-level = <5>;
 505                                         };
 506
 507                                         rpmpd_opp6: opp6 {
 508                                                 opp-level = <6>;
 509                                         };
 510                                 };
 511                         };
 512
 513                         pm8994-regulators {
 514                                 compatible = "qcom,rpm-pm8994-regulators";
 515
 516                                 pm8994_s1: s1 {};
 517                                 pm8994_s2: s2 {};
 518                                 pm8994_s3: s3 {};
 519                                 pm8994_s4: s4 {};
 520                                 pm8994_s5: s5 {};
 521                                 pm8994_s6: s6 {};
 522                                 pm8994_s7: s7 {};
 523                                 pm8994_s8: s8 {};
 524                                 pm8994_s9: s9 {};
 525                                 pm8994_s10: s10 {};
 526                                 pm8994_s11: s11 {};
 527                                 pm8994_s12: s12 {};
 528
 529                                 pm8994_l1: l1 {};
 530                                 pm8994_l2: l2 {};
 531                                 pm8994_l3: l3 {};
 532                                 pm8994_l4: l4 {};
 533                                 pm8994_l5: l5 {};
 534                                 pm8994_l6: l6 {};
 535                                 pm8994_l7: l7 {};
 536                                 pm8994_l8: l8 {};
 537                                 pm8994_l9: l9 {};
 538                                 pm8994_l10: l10 {};
 539                                 pm8994_l11: l11 {};
 540                                 pm8994_l12: l12 {};
 541                                 pm8994_l13: l13 {};
 542                                 pm8994_l14: l14 {};
 543                                 pm8994_l15: l15 {};
 544                                 pm8994_l16: l16 {};
 545                                 pm8994_l17: l17 {};
 546                                 pm8994_l18: l18 {};
 547                                 pm8994_l19: l19 {};
 548                                 pm8994_l20: l20 {};
 549                                 pm8994_l21: l21 {};
 550                                 pm8994_l22: l22 {};
 551                                 pm8994_l23: l23 {};
 552                                 pm8994_l24: l24 {};
 553                                 pm8994_l25: l25 {};
 554                                 pm8994_l26: l26 {};
 555                                 pm8994_l27: l27 {};
 556                                 pm8994_l28: l28 {};
 557                                 pm8994_l29: l29 {};
 558                                 pm8994_l30: l30 {};
 559                                 pm8994_l31: l31 {};
 560                                 pm8994_l32: l32 {};
 561                         };
 562
 563                 };
 564         };
 565
 566         soc: soc {
 567                 #address-cells = <1>;
 568                 #size-cells = <1>;
 569                 ranges = <0 0 0 0xffffffff>;
 570                 compatible = "simple-bus";
 571
 572                 rpm_msg_ram: memory@68000 {
 573                         compatible = "qcom,rpm-msg-ram";
 574                         reg = <0x68000 0x6000>;
 575                 };
 576
 577                 rng: rng@83000 {
 578                         compatible = "qcom,prng-ee";
 579                         reg = <0x00083000 0x1000>;
 580                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 581                         clock-names = "core";
 582                 };
 583
 584                 tcsr_mutex_regs: syscon@740000 {
 585                         compatible = "syscon";
 586                         reg = <0x740000 0x20000>;
 587                 };
 588
 589                 tsens0: thermal-sensor@4a9000 {
 590                         compatible = "qcom,msm8996-tsens";
 591                         reg = <0x4a9000 0x1000>, /* TM */
 592                               <0x4a8000 0x1000>; /* SROT */
 593                         #qcom,sensors = <13>;
 594                         #thermal-sensor-cells = <1>;
 595                 };
 596
 597                 tsens1: thermal-sensor@4ad000 {
 598                         compatible = "qcom,msm8996-tsens";
 599                         reg = <0x4ad000 0x1000>, /* TM */
 600                               <0x4ac000 0x1000>; /* SROT */
 601                         #qcom,sensors = <8>;
 602                         #thermal-sensor-cells = <1>;
 603                 };
 604
 605                 tcsr: syscon@7a0000 {
 606                         compatible = "qcom,tcsr-msm8996", "syscon";
 607                         reg = <0x7a0000 0x18000>;
 608                 };
 609
 610                 intc: interrupt-controller@9bc0000 {
 611                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
 612                         #interrupt-cells = <3>;
 613                         interrupt-controller;
 614                         #redistributor-regions = <1>;
 615                         redistributor-stride = <0x0 0x40000>;
 616                         reg = <0x09bc0000 0x10000>,
 617                               <0x09c00000 0x100000>;
 618                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 619                 };
 620
 621                 apcs_glb: mailbox@9820000 {
 622                         compatible = "qcom,msm8996-apcs-hmss-global";
 623                         reg = <0x9820000 0x1000>;
 624
 625                         #mbox-cells = <1>;
 626                 };
 627
 628                 gcc: clock-controller@300000 {
 629                         compatible = "qcom,gcc-msm8996";
 630                         #clock-cells = <1>;
 631                         #reset-cells = <1>;
 632                         #power-domain-cells = <1>;
 633                         reg = <0x300000 0x90000>;
 634                 };
 635
 636                 stm@3002000 {
 637                         compatible = "arm,coresight-stm", "arm,primecell";
 638                         reg = <0x3002000 0x1000>,
 639                               <0x8280000 0x180000>;
 640                         reg-names = "stm-base", "stm-stimulus-base";
 641
 642                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 643                         clock-names = "apb_pclk", "atclk";
 644
 645                         out-ports {
 646                                 port {
 647                                         stm_out: endpoint {
 648                                                 remote-endpoint =
 649                                                   <&funnel0_in>;
 650                                         };
 651                                 };
 652                         };
 653                 };
 654
 655                 tpiu@3020000 {
 656                         compatible = "arm,coresight-tpiu", "arm,primecell";
 657                         reg = <0x3020000 0x1000>;
 658
 659                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 660                         clock-names = "apb_pclk", "atclk";
 661
 662                         in-ports {
 663                                 port {
 664                                         tpiu_in: endpoint {
 665                                                 remote-endpoint =
 666                                                   <&replicator_out1>;
 667                                         };
 668                                 };
 669                         };
 670                 };
 671
 672                 funnel@3021000 {
 673                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 674                         reg = <0x3021000 0x1000>;
 675
 676                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 677                         clock-names = "apb_pclk", "atclk";
 678
 679                         in-ports {
 680                                 #address-cells = <1>;
 681                                 #size-cells = <0>;
 682
 683                                 port@7 {
 684                                         reg = <7>;
 685                                         funnel0_in: endpoint {
 686                                                 remote-endpoint =
 687                                                   <&stm_out>;
 688                                         };
 689                                 };
 690                         };
 691
 692                         out-ports {
 693                                 port {
 694                                         funnel0_out: endpoint {
 695                                                 remote-endpoint =
 696                                                   <&merge_funnel_in0>;
 697                                         };
 698                                 };
 699                         };
 700                 };
 701
 702                 funnel@3022000 {
 703                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 704                         reg = <0x3022000 0x1000>;
 705
 706                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 707                         clock-names = "apb_pclk", "atclk";
 708
 709                         in-ports {
 710                                 #address-cells = <1>;
 711                                 #size-cells = <0>;
 712
 713                                 port@6 {
 714                                         reg = <6>;
 715                                         funnel1_in: endpoint {
 716                                                 remote-endpoint =
 717                                                   <&apss_merge_funnel_out>;
 718                                         };
 719                                 };
 720                         };
 721
 722                         out-ports {
 723                                 port {
 724                                         funnel1_out: endpoint {
 725                                                 remote-endpoint =
 726                                                   <&merge_funnel_in1>;
 727                                         };
 728                                 };
 729                         };
 730                 };
 731
 732                 funnel@3023000 {
 733                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 734                         reg = <0x3023000 0x1000>;
 735
 736                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 737                         clock-names = "apb_pclk", "atclk";
 738
 739
 740                         out-ports {
 741                                 port {
 742                                         funnel2_out: endpoint {
 743                                                 remote-endpoint =
 744                                                   <&merge_funnel_in2>;
 745                                         };
 746                                 };
 747                         };
 748                 };
 749
 750                 funnel@3025000 {
 751                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 752                         reg = <0x3025000 0x1000>;
 753
 754                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 755                         clock-names = "apb_pclk", "atclk";
 756
 757                         in-ports {
 758                                 #address-cells = <1>;
 759                                 #size-cells = <0>;
 760
 761                                 port@0 {
 762                                         reg = <0>;
 763                                         merge_funnel_in0: endpoint {
 764                                                 remote-endpoint =
 765                                                   <&funnel0_out>;
 766                                         };
 767                                 };
 768
 769                                 port@1 {
 770                                         reg = <1>;
 771                                         merge_funnel_in1: endpoint {
 772                                                 remote-endpoint =
 773                                                   <&funnel1_out>;
 774                                         };
 775                                 };
 776
 777                                 port@2 {
 778                                         reg = <2>;
 779                                         merge_funnel_in2: endpoint {
 780                                                 remote-endpoint =
 781                                                   <&funnel2_out>;
 782                                         };
 783                                 };
 784                         };
 785
 786                         out-ports {
 787                                 port {
 788                                         merge_funnel_out: endpoint {
 789                                                 remote-endpoint =
 790                                                   <&etf_in>;
 791                                         };
 792                                 };
 793                         };
 794                 };
 795
 796                 replicator@3026000 {
 797                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 798                         reg = <0x3026000 0x1000>;
 799
 800                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 801                         clock-names = "apb_pclk", "atclk";
 802
 803                         in-ports {
 804                                 port {
 805                                         replicator_in: endpoint {
 806                                                 remote-endpoint =
 807                                                   <&etf_out>;
 808                                         };
 809                                 };
 810                         };
 811
 812                         out-ports {
 813                                 #address-cells = <1>;
 814                                 #size-cells = <0>;
 815
 816                                 port@0 {
 817                                         reg = <0>;
 818                                         replicator_out0: endpoint {
 819                                                 remote-endpoint =
 820                                                   <&etr_in>;
 821                                         };
 822                                 };
 823
 824                                 port@1 {
 825                                         reg = <1>;
 826                                         replicator_out1: endpoint {
 827                                                 remote-endpoint =
 828                                                   <&tpiu_in>;
 829                                         };
 830                                 };
 831                         };
 832                 };
 833
 834                 etf@3027000 {
 835                         compatible = "arm,coresight-tmc", "arm,primecell";
 836                         reg = <0x3027000 0x1000>;
 837
 838                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 839                         clock-names = "apb_pclk", "atclk";
 840
 841                         in-ports {
 842                                 port {
 843                                         etf_in: endpoint {
 844                                                 remote-endpoint =
 845                                                   <&merge_funnel_out>;
 846                                         };
 847                                 };
 848                         };
 849
 850                         out-ports {
 851                                 port {
 852                                         etf_out: endpoint {
 853                                                 remote-endpoint =
 854                                                   <&replicator_in>;
 855                                         };
 856                                 };
 857                         };
 858                 };
 859
 860                 etr@3028000 {
 861                         compatible = "arm,coresight-tmc", "arm,primecell";
 862                         reg = <0x3028000 0x1000>;
 863
 864                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 865                         clock-names = "apb_pclk", "atclk";
 866                         arm,scatter-gather;
 867
 868                         in-ports {
 869                                 port {
 870                                         etr_in: endpoint {
 871                                                 remote-endpoint =
 872                                                   <&replicator_out0>;
 873                                         };
 874                                 };
 875                         };
 876                 };
 877
 878                 debug@3810000 {
 879                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 880                         reg = <0x3810000 0x1000>;
 881
 882                         clocks = <&rpmcc RPM_QDSS_CLK>;
 883                         clock-names = "apb_pclk";
 884
 885                         cpu = <&CPU0>;
 886                 };
 887
 888                 etm@3840000 {
 889                         compatible = "arm,coresight-etm4x", "arm,primecell";
 890                         reg = <0x3840000 0x1000>;
 891
 892                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 893                         clock-names = "apb_pclk", "atclk";
 894
 895                         cpu = <&CPU0>;
 896
 897                         out-ports {
 898                                 port {
 899                                         etm0_out: endpoint {
 900                                                 remote-endpoint =
 901                                                   <&apss_funnel0_in0>;
 902                                         };
 903                                 };
 904                         };
 905                 };
 906
 907                 debug@3910000 {
 908                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 909                         reg = <0x3910000 0x1000>;
 910
 911                         clocks = <&rpmcc RPM_QDSS_CLK>;
 912                         clock-names = "apb_pclk";
 913
 914                         cpu = <&CPU1>;
 915                 };
 916
 917                 etm@3940000 {
 918                         compatible = "arm,coresight-etm4x", "arm,primecell";
 919                         reg = <0x3940000 0x1000>;
 920
 921                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 922                         clock-names = "apb_pclk", "atclk";
 923
 924                         cpu = <&CPU1>;
 925
 926                         out-ports {
 927                                 port {
 928                                         etm1_out: endpoint {
 929                                                 remote-endpoint =
 930                                                   <&apss_funnel0_in1>;
 931                                         };
 932                                 };
 933                         };
 934                 };
 935
 936                 funnel@39b0000 { /* APSS Funnel 0 */
 937                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 938                         reg = <0x39b0000 0x1000>;
 939
 940                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 941                         clock-names = "apb_pclk", "atclk";
 942
 943                         in-ports {
 944                                 #address-cells = <1>;
 945                                 #size-cells = <0>;
 946
 947                                 port@0 {
 948                                         reg = <0>;
 949                                         apss_funnel0_in0: endpoint {
 950                                                 remote-endpoint = <&etm0_out>;
 951                                         };
 952                                 };
 953
 954                                 port@1 {
 955                                         reg = <1>;
 956                                         apss_funnel0_in1: endpoint {
 957                                                 remote-endpoint = <&etm1_out>;
 958                                         };
 959                                 };
 960                         };
 961
 962                         out-ports {
 963                                 port {
 964                                         apss_funnel0_out: endpoint {
 965                                                 remote-endpoint =
 966                                                   <&apss_merge_funnel_in0>;
 967                                         };
 968                                 };
 969                         };
 970                 };
 971
 972                 debug@3a10000 {
 973                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 974                         reg = <0x3a10000 0x1000>;
 975
 976                         clocks = <&rpmcc RPM_QDSS_CLK>;
 977                         clock-names = "apb_pclk";
 978
 979                         cpu = <&CPU2>;
 980                 };
 981
 982                 etm@3a40000 {
 983                         compatible = "arm,coresight-etm4x", "arm,primecell";
 984                         reg = <0x3a40000 0x1000>;
 985
 986                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 987                         clock-names = "apb_pclk", "atclk";
 988
 989                         cpu = <&CPU2>;
 990
 991                         out-ports {
 992                                 port {
 993                                         etm2_out: endpoint {
 994                                                 remote-endpoint =
 995                                                   <&apss_funnel1_in0>;
 996                                         };
 997                                 };
 998                         };
 999                 };
1000
1001                 debug@3b10000 {
1002                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
1003                         reg = <0x3b10000 0x1000>;
1004
1005                         clocks = <&rpmcc RPM_QDSS_CLK>;
1006                         clock-names = "apb_pclk";
1007
1008                         cpu = <&CPU3>;
1009                 };
1010
1011                 etm@3b40000 {
1012                         compatible = "arm,coresight-etm4x", "arm,primecell";
1013                         reg = <0x3b40000 0x1000>;
1014
1015                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1016                         clock-names = "apb_pclk", "atclk";
1017
1018                         cpu = <&CPU3>;
1019
1020                         out-ports {
1021                                 port {
1022                                         etm3_out: endpoint {
1023                                                 remote-endpoint =
1024                                                   <&apss_funnel1_in1>;
1025                                         };
1026                                 };
1027                         };
1028                 };
1029
1030                 funnel@3bb0000 { /* APSS Funnel 1 */
1031                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1032                         reg = <0x3bb0000 0x1000>;
1033
1034                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1035                         clock-names = "apb_pclk", "atclk";
1036
1037                         in-ports {
1038                                 #address-cells = <1>;
1039                                 #size-cells = <0>;
1040
1041                                 port@0 {
1042                                         reg = <0>;
1043                                         apss_funnel1_in0: endpoint {
1044                                                 remote-endpoint = <&etm2_out>;
1045                                         };
1046                                 };
1047
1048                                 port@1 {
1049                                         reg = <1>;
1050                                         apss_funnel1_in1: endpoint {
1051                                                 remote-endpoint = <&etm3_out>;
1052                                         };
1053                                 };
1054                         };
1055
1056                         out-ports {
1057                                 port {
1058                                         apss_funnel1_out: endpoint {
1059                                                 remote-endpoint =
1060                                                   <&apss_merge_funnel_in1>;
1061                                         };
1062                                 };
1063                         };
1064                 };
1065
1066                 funnel@3bc0000 {
1067                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1068                         reg = <0x3bc0000 0x1000>;
1069
1070                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1071                         clock-names = "apb_pclk", "atclk";
1072
1073                         in-ports {
1074                                 #address-cells = <1>;
1075                                 #size-cells = <0>;
1076
1077                                 port@0 {
1078                                         reg = <0>;
1079                                         apss_merge_funnel_in0: endpoint {
1080                                                 remote-endpoint =
1081                                                   <&apss_funnel0_out>;
1082                                         };
1083                                 };
1084
1085                                 port@1 {
1086                                         reg = <1>;
1087                                         apss_merge_funnel_in1: endpoint {
1088                                                 remote-endpoint =
1089                                                   <&apss_funnel1_out>;
1090                                         };
1091                                 };
1092                         };
1093
1094                         out-ports {
1095                                 port {
1096                                         apss_merge_funnel_out: endpoint {
1097                                                 remote-endpoint =
1098                                                   <&funnel1_in>;
1099                                         };
1100                                 };
1101                         };
1102                 };
1103
1104                 kryocc: clock-controller@6400000 {
1105                         compatible = "qcom,apcc-msm8996";
1106                         reg = <0x6400000 0x90000>;
1107                         #clock-cells = <1>;
1108                 };
1109
1110                 blsp1_uart1: serial@7570000 {
1111                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1112                         reg = <0x07570000 0x1000>;
1113                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1114                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1115                                  <&gcc GCC_BLSP1_AHB_CLK>;
1116                         clock-names = "core", "iface";
1117                         status = "disabled";
1118                 };
1119
1120                 blsp1_spi0: spi@7575000 {
1121                         compatible = "qcom,spi-qup-v2.2.1";
1122                         reg = <0x07575000 0x600>;
1123                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1124                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1125                                  <&gcc GCC_BLSP1_AHB_CLK>;
1126                         clock-names = "core", "iface";
1127                         pinctrl-names = "default", "sleep";
1128                         pinctrl-0 = <&blsp1_spi0_default>;
1129                         pinctrl-1 = <&blsp1_spi0_sleep>;
1130                         #address-cells = <1>;
1131                         #size-cells = <0>;
1132                         status = "disabled";
1133                 };
1134
1135                 blsp2_i2c0: i2c@75b5000 {
1136                         compatible = "qcom,i2c-qup-v2.2.1";
1137                         reg = <0x075b5000 0x1000>;
1138                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1139                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1140                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1141                         clock-names = "iface", "core";
1142                         pinctrl-names = "default", "sleep";
1143                         pinctrl-0 = <&blsp2_i2c0_default>;
1144                         pinctrl-1 = <&blsp2_i2c0_sleep>;
1145                         #address-cells = <1>;
1146                         #size-cells = <0>;
1147                         status = "disabled";
1148                 };
1149
1150                 blsp2_uart1: serial@75b0000 {
1151                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1152                         reg = <0x75b0000 0x1000>;
1153                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1154                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1155                                  <&gcc GCC_BLSP2_AHB_CLK>;
1156                         clock-names = "core", "iface";
1157                         status = "disabled";
1158                 };
1159
1160                 blsp2_i2c1: i2c@75b6000 {
1161                         compatible = "qcom,i2c-qup-v2.2.1";
1162                         reg = <0x075b6000 0x1000>;
1163                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1164                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1165                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1166                         clock-names = "iface", "core";
1167                         pinctrl-names = "default", "sleep";
1168                         pinctrl-0 = <&blsp2_i2c1_default>;
1169                         pinctrl-1 = <&blsp2_i2c1_sleep>;
1170                         #address-cells = <1>;
1171                         #size-cells = <0>;
1172                         status = "disabled";
1173                 };
1174
1175                 blsp2_uart2: serial@75b1000 {
1176                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1177                         reg = <0x075b1000 0x1000>;
1178                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1179                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1180                                  <&gcc GCC_BLSP2_AHB_CLK>;
1181                         clock-names = "core", "iface";
1182                         status = "disabled";
1183                 };
1184
1185                 blsp1_i2c2: i2c@7577000 {
1186                         compatible = "qcom,i2c-qup-v2.2.1";
1187                         reg = <0x07577000 0x1000>;
1188                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1189                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1190                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1191                         clock-names = "iface", "core";
1192                         pinctrl-names = "default", "sleep";
1193                         pinctrl-0 = <&blsp1_i2c2_default>;
1194                         pinctrl-1 = <&blsp1_i2c2_sleep>;
1195                         #address-cells = <1>;
1196                         #size-cells = <0>;
1197                         status = "disabled";
1198                 };
1199
1200                 blsp2_spi5: spi@75ba000{
1201                         compatible = "qcom,spi-qup-v2.2.1";
1202                         reg = <0x075ba000 0x600>;
1203                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1204                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1205                                  <&gcc GCC_BLSP2_AHB_CLK>;
1206                         clock-names = "core", "iface";
1207                         pinctrl-names = "default", "sleep";
1208                         pinctrl-0 = <&blsp2_spi5_default>;
1209                         pinctrl-1 = <&blsp2_spi5_sleep>;
1210                         #address-cells = <1>;
1211                         #size-cells = <0>;
1212                         status = "disabled";
1213                 };
1214
1215                 sdhc2: sdhci@74a4900 {
1216                          status = "disabled";
1217                          compatible = "qcom,sdhci-msm-v4";
1218                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
1219                          reg-names = "hc_mem", "core_mem";
1220
1221                          interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1222                                       <0 221 IRQ_TYPE_LEVEL_HIGH>;
1223                          interrupt-names = "hc_irq", "pwr_irq";
1224
1225                          clock-names = "iface", "core", "xo";
1226                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1227                          <&gcc GCC_SDCC2_APPS_CLK>,
1228                          <&xo_board>;
1229                          bus-width = <4>;
1230                  };
1231
1232                 msmgpio: pinctrl@1010000 {
1233                         compatible = "qcom,msm8996-pinctrl";
1234                         reg = <0x01010000 0x300000>;
1235                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1236                         gpio-controller;
1237                         #gpio-cells = <2>;
1238                         interrupt-controller;
1239                         #interrupt-cells = <2>;
1240                 };
1241
1242                 timer@9840000 {
1243                         #address-cells = <1>;
1244                         #size-cells = <1>;
1245                         ranges;
1246                         compatible = "arm,armv7-timer-mem";
1247                         reg = <0x09840000 0x1000>;
1248                         clock-frequency = <19200000>;
1249
1250                         frame@9850000 {
1251                                 frame-number = <0>;
1252                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1253                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1254                                 reg = <0x09850000 0x1000>,
1255                                       <0x09860000 0x1000>;
1256                         };
1257
1258                         frame@9870000 {
1259                                 frame-number = <1>;
1260                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1261                                 reg = <0x09870000 0x1000>;
1262                                 status = "disabled";
1263                         };
1264
1265                         frame@9880000 {
1266                                 frame-number = <2>;
1267                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1268                                 reg = <0x09880000 0x1000>;
1269                                 status = "disabled";
1270                         };
1271
1272                         frame@9890000 {
1273                                 frame-number = <3>;
1274                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1275                                 reg = <0x09890000 0x1000>;
1276                                 status = "disabled";
1277                         };
1278
1279                         frame@98a0000 {
1280                                 frame-number = <4>;
1281                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1282                                 reg = <0x098a0000 0x1000>;
1283                                 status = "disabled";
1284                         };
1285
1286                         frame@98b0000 {
1287                                 frame-number = <5>;
1288                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1289                                 reg = <0x098b0000 0x1000>;
1290                                 status = "disabled";
1291                         };
1292
1293                         frame@98c0000 {
1294                                 frame-number = <6>;
1295                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1296                                 reg = <0x098c0000 0x1000>;
1297                                 status = "disabled";
1298                         };
1299                 };
1300
1301                 spmi_bus: qcom,spmi@400f000 {
1302                         compatible = "qcom,spmi-pmic-arb";
1303                         reg = <0x400f000 0x1000>,
1304                               <0x4400000 0x800000>,
1305                               <0x4c00000 0x800000>,
1306                               <0x5800000 0x200000>,
1307                               <0x400a000 0x002100>;
1308                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1309                         interrupt-names = "periph_irq";
1310                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1311                         qcom,ee = <0>;
1312                         qcom,channel = <0>;
1313                         #address-cells = <2>;
1314                         #size-cells = <0>;
1315                         interrupt-controller;
1316                         #interrupt-cells = <4>;
1317                 };
1318
1319                 ufsphy: phy@627000 {
1320                         compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
1321                         reg = <0x627000 0xda8>;
1322                         reg-names = "phy_mem";
1323                         #phy-cells = <0>;
1324
1325                         vdda-phy-supply = <&pm8994_l28>;
1326                         vdda-pll-supply = <&pm8994_l12>;
1327
1328                         vdda-phy-max-microamp = <18380>;
1329                         vdda-pll-max-microamp = <9440>;
1330
1331                         vddp-ref-clk-supply = <&pm8994_l25>;
1332                         vddp-ref-clk-max-microamp = <100>;
1333                         vddp-ref-clk-always-on;
1334
1335                         clock-names = "ref_clk_src", "ref_clk";
1336                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
1337                                  <&gcc GCC_UFS_CLKREF_CLK>;
1338                         resets = <&ufshc 0>;
1339                         status = "disabled";
1340                 };
1341
1342                 ufshc: ufshc@624000 {
1343                         compatible = "qcom,ufshc";
1344                         reg = <0x624000 0x2500>;
1345                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
1346
1347                         phys = <&ufsphy>;
1348                         phy-names = "ufsphy";
1349
1350                         vcc-supply = <&pm8994_l20>;
1351                         vccq-supply = <&pm8994_l25>;
1352                         vccq2-supply = <&pm8994_s4>;
1353
1354                         vcc-max-microamp = <600000>;
1355                         vccq-max-microamp = <450000>;
1356                         vccq2-max-microamp = <450000>;
1357
1358                         power-domains = <&gcc UFS_GDSC>;
1359
1360                         clock-names =
1361                                 "core_clk_src",
1362                                 "core_clk",
1363                                 "bus_clk",
1364                                 "bus_aggr_clk",
1365                                 "iface_clk",
1366                                 "core_clk_unipro_src",
1367                                 "core_clk_unipro",
1368                                 "core_clk_ice",
1369                                 "ref_clk",
1370                                 "tx_lane0_sync_clk",
1371                                 "rx_lane0_sync_clk";
1372                         clocks =
1373                                 <&gcc UFS_AXI_CLK_SRC>,
1374                                 <&gcc GCC_UFS_AXI_CLK>,
1375                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
1376                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
1377                                 <&gcc GCC_UFS_AHB_CLK>,
1378                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
1379                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
1380                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
1381                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
1382                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
1383                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
1384                         freq-table-hz =
1385                                 <100000000 200000000>,
1386                                 <0 0>,
1387                                 <0 0>,
1388                                 <0 0>,
1389                                 <0 0>,
1390                                 <150000000 300000000>,
1391                                 <0 0>,
1392                                 <0 0>,
1393                                 <0 0>,
1394                                 <0 0>,
1395                                 <0 0>;
1396
1397                         lanes-per-direction = <1>;
1398                         #reset-cells = <1>;
1399                         status = "disabled";
1400
1401                         ufs_variant {
1402                                 compatible = "qcom,ufs_variant";
1403                         };
1404                 };
1405
1406                 mmcc: clock-controller@8c0000 {
1407                         compatible = "qcom,mmcc-msm8996";
1408                         #clock-cells = <1>;
1409                         #reset-cells = <1>;
1410                         #power-domain-cells = <1>;
1411                         reg = <0x8c0000 0x40000>;
1412                         assigned-clocks = <&mmcc MMPLL9_PLL>,
1413                                           <&mmcc MMPLL1_PLL>,
1414                                           <&mmcc MMPLL3_PLL>,
1415                                           <&mmcc MMPLL4_PLL>,
1416                                           <&mmcc MMPLL5_PLL>;
1417                         assigned-clock-rates = <624000000>,
1418                                                <810000000>,
1419                                                <980000000>,
1420                                                <960000000>,
1421                                                <825000000>;
1422                 };
1423
1424                 qfprom@74000 {
1425                         compatible = "qcom,qfprom";
1426                         reg = <0x74000 0x8ff>;
1427                         #address-cells = <1>;
1428                         #size-cells = <1>;
1429
1430                         qusb2p_hstx_trim: hstx_trim@24e {
1431                                 reg = <0x24e 0x2>;
1432                                 bits = <5 4>;
1433                         };
1434
1435                         qusb2s_hstx_trim: hstx_trim@24f {
1436                                 reg = <0x24f 0x1>;
1437                                 bits = <1 4>;
1438                         };
1439
1440                         gpu_speed_bin: gpu_speed_bin@133 {
1441                                 reg = <0x133 0x1>;
1442                                 bits = <5 3>;
1443                         };
1444                 };
1445
1446                 phy@34000 {
1447                         compatible = "qcom,msm8996-qmp-pcie-phy";
1448                         reg = <0x34000 0x488>;
1449                         #clock-cells = <1>;
1450                         #address-cells = <1>;
1451                         #size-cells = <1>;
1452                         ranges;
1453
1454                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
1455                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
1456                                 <&gcc GCC_PCIE_CLKREF_CLK>;
1457                         clock-names = "aux", "cfg_ahb", "ref";
1458
1459                         vdda-phy-supply = <&pm8994_l28>;
1460                         vdda-pll-supply = <&pm8994_l12>;
1461
1462                         resets = <&gcc GCC_PCIE_PHY_BCR>,
1463                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
1464                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
1465                         reset-names = "phy", "common", "cfg";
1466                         status = "disabled";
1467
1468                         pciephy_0: lane@35000 {
1469                                 reg = <0x035000 0x130>,
1470                                         <0x035200 0x200>,
1471                                         <0x035400 0x1dc>;
1472                                 #phy-cells = <0>;
1473
1474                                 clock-output-names = "pcie_0_pipe_clk_src";
1475                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
1476                                 clock-names = "pipe0";
1477                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
1478                                 reset-names = "lane0";
1479                         };
1480
1481                         pciephy_1: lane@36000 {
1482                                 reg = <0x036000 0x130>,
1483                                         <0x036200 0x200>,
1484                                         <0x036400 0x1dc>;
1485                                 #phy-cells = <0>;
1486
1487                                 clock-output-names = "pcie_1_pipe_clk_src";
1488                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
1489                                 clock-names = "pipe1";
1490                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
1491                                 reset-names = "lane1";
1492                         };
1493
1494                         pciephy_2: lane@37000 {
1495                                 reg = <0x037000 0x130>,
1496                                         <0x037200 0x200>,
1497                                         <0x037400 0x1dc>;
1498                                 #phy-cells = <0>;
1499
1500                                 clock-output-names = "pcie_2_pipe_clk_src";
1501                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
1502                                 clock-names = "pipe2";
1503                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
1504                                 reset-names = "lane2";
1505                         };
1506                 };
1507
1508                 phy@7410000 {
1509                         compatible = "qcom,msm8996-qmp-usb3-phy";
1510                         reg = <0x7410000 0x1c4>;
1511                         #clock-cells = <1>;
1512                         #address-cells = <1>;
1513                         #size-cells = <1>;
1514                         ranges;
1515
1516                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1517                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1518                                 <&gcc GCC_USB3_CLKREF_CLK>;
1519                         clock-names = "aux", "cfg_ahb", "ref";
1520
1521                         vdda-phy-supply = <&pm8994_l28>;
1522                         vdda-pll-supply = <&pm8994_l12>;
1523
1524                         resets = <&gcc GCC_USB3_PHY_BCR>,
1525                                 <&gcc GCC_USB3PHY_PHY_BCR>;
1526                         reset-names = "phy", "common";
1527                         status = "disabled";
1528
1529                         ssusb_phy_0: lane@7410200 {
1530                                 reg = <0x7410200 0x200>,
1531                                         <0x7410400 0x130>,
1532                                         <0x7410600 0x1a8>;
1533                                 #phy-cells = <0>;
1534
1535                                 clock-output-names = "usb3_phy_pipe_clk_src";
1536                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1537                                 clock-names = "pipe0";
1538                         };
1539                 };
1540
1541                 hsusb_phy1: phy@7411000 {
1542                         compatible = "qcom,msm8996-qusb2-phy";
1543                         reg = <0x7411000 0x180>;
1544                         #phy-cells = <0>;
1545
1546                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1547                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1548                         clock-names = "cfg_ahb", "ref";
1549
1550                         vdda-pll-supply = <&pm8994_l12>;
1551                         vdda-phy-dpdm-supply = <&pm8994_l24>;
1552
1553                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1554                         nvmem-cells = <&qusb2p_hstx_trim>;
1555                         status = "disabled";
1556                 };
1557
1558                 hsusb_phy2: phy@7412000 {
1559                         compatible = "qcom,msm8996-qusb2-phy";
1560                         reg = <0x7412000 0x180>;
1561                         #phy-cells = <0>;
1562
1563                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1564                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1565                         clock-names = "cfg_ahb", "ref";
1566
1567                         vdda-pll-supply = <&pm8994_l12>;
1568                         vdda-phy-dpdm-supply = <&pm8994_l24>;
1569
1570                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1571                         nvmem-cells = <&qusb2s_hstx_trim>;
1572                         status = "disabled";
1573                 };
1574
1575                 usb2: usb@76f8800 {
1576                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1577                         reg = <0x76f8800 0x400>;
1578                         #address-cells = <1>;
1579                         #size-cells = <1>;
1580                         ranges;
1581
1582                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1583                                 <&gcc GCC_USB20_MASTER_CLK>,
1584                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1585                                 <&gcc GCC_USB20_SLEEP_CLK>,
1586                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1587
1588                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1589                                           <&gcc GCC_USB20_MASTER_CLK>;
1590                         assigned-clock-rates = <19200000>, <60000000>;
1591
1592                         power-domains = <&gcc USB30_GDSC>;
1593                         status = "disabled";
1594
1595                         dwc3@7600000 {
1596                                 compatible = "snps,dwc3";
1597                                 reg = <0x7600000 0xcc00>;
1598                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1599                                 phys = <&hsusb_phy2>;
1600                                 phy-names = "usb2-phy";
1601                         };
1602                 };
1603
1604                 usb3: usb@6af8800 {
1605                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1606                         reg = <0x6af8800 0x400>;
1607                         #address-cells = <1>;
1608                         #size-cells = <1>;
1609                         ranges;
1610
1611                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1612                                 <&gcc GCC_USB30_MASTER_CLK>,
1613                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1614                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1615                                 <&gcc GCC_USB30_SLEEP_CLK>,
1616                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1617
1618                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1619                                           <&gcc GCC_USB30_MASTER_CLK>;
1620                         assigned-clock-rates = <19200000>, <120000000>;
1621
1622                         power-domains = <&gcc USB30_GDSC>;
1623                         status = "disabled";
1624
1625                         dwc3@6a00000 {
1626                                 compatible = "snps,dwc3";
1627                                 reg = <0x6a00000 0xcc00>;
1628                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1629                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1630                                 phy-names = "usb2-phy", "usb3-phy";
1631                         };
1632                 };
1633
1634                 vfe_smmu: iommu@da0000 {
1635                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1636                         reg = <0xda0000 0x10000>;
1637
1638                         #global-interrupts = <1>;
1639                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1640                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1641                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1642                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1643                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1644                                  <&mmcc SMMU_VFE_AXI_CLK>;
1645                         clock-names = "iface",
1646                                       "bus";
1647                         #iommu-cells = <1>;
1648                 };
1649
1650                 camss: camss@a00000 {
1651                         compatible = "qcom,msm8996-camss";
1652                         reg = <0xa34000 0x1000>,
1653                                 <0xa00030 0x4>,
1654                                 <0xa35000 0x1000>,
1655                                 <0xa00038 0x4>,
1656                                 <0xa36000 0x1000>,
1657                                 <0xa00040 0x4>,
1658                                 <0xa30000 0x100>,
1659                                 <0xa30400 0x100>,
1660                                 <0xa30800 0x100>,
1661                                 <0xa30c00 0x100>,
1662                                 <0xa31000 0x500>,
1663                                 <0xa00020 0x10>,
1664                                 <0xa10000 0x1000>,
1665                                 <0xa14000 0x1000>;
1666                         reg-names = "csiphy0",
1667                                 "csiphy0_clk_mux",
1668                                 "csiphy1",
1669                                 "csiphy1_clk_mux",
1670                                 "csiphy2",
1671                                 "csiphy2_clk_mux",
1672                                 "csid0",
1673                                 "csid1",
1674                                 "csid2",
1675                                 "csid3",
1676                                 "ispif",
1677                                 "csi_clk_mux",
1678                                 "vfe0",
1679                                 "vfe1";
1680                         interrupts = <GIC_SPI 78 0>,
1681                                 <GIC_SPI 79 0>,
1682                                 <GIC_SPI 80 0>,
1683                                 <GIC_SPI 296 0>,
1684                                 <GIC_SPI 297 0>,
1685                                 <GIC_SPI 298 0>,
1686                                 <GIC_SPI 299 0>,
1687                                 <GIC_SPI 309 0>,
1688                                 <GIC_SPI 314 0>,
1689                                 <GIC_SPI 315 0>;
1690                         interrupt-names = "csiphy0",
1691                                 "csiphy1",
1692                                 "csiphy2",
1693                                 "csid0",
1694                                 "csid1",
1695                                 "csid2",
1696                                 "csid3",
1697                                 "ispif",
1698                                 "vfe0",
1699                                 "vfe1";
1700                         power-domains = <&mmcc VFE0_GDSC>;
1701                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1702                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1703                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1704                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1705                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1706                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1707                                 <&mmcc CAMSS_CSI0_CLK>,
1708                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1709                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1710                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1711                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1712                                 <&mmcc CAMSS_CSI1_CLK>,
1713                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1714                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1715                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1716                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1717                                 <&mmcc CAMSS_CSI2_CLK>,
1718                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1719                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1720                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1721                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1722                                 <&mmcc CAMSS_CSI3_CLK>,
1723                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1724                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1725                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1726                                 <&mmcc CAMSS_AHB_CLK>,
1727                                 <&mmcc CAMSS_VFE0_CLK>,
1728                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1729                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1730                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1731                                 <&mmcc CAMSS_VFE1_CLK>,
1732                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1733                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1734                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1735                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1736                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1737                         clock-names = "top_ahb",
1738                                 "ispif_ahb",
1739                                 "csiphy0_timer",
1740                                 "csiphy1_timer",
1741                                 "csiphy2_timer",
1742                                 "csi0_ahb",
1743                                 "csi0",
1744                                 "csi0_phy",
1745                                 "csi0_pix",
1746                                 "csi0_rdi",
1747                                 "csi1_ahb",
1748                                 "csi1",
1749                                 "csi1_phy",
1750                                 "csi1_pix",
1751                                 "csi1_rdi",
1752                                 "csi2_ahb",
1753                                 "csi2",
1754                                 "csi2_phy",
1755                                 "csi2_pix",
1756                                 "csi2_rdi",
1757                                 "csi3_ahb",
1758                                 "csi3",
1759                                 "csi3_phy",
1760                                 "csi3_pix",
1761                                 "csi3_rdi",
1762                                 "ahb",
1763                                 "vfe0",
1764                                 "csi_vfe0",
1765                                 "vfe0_ahb",
1766                                 "vfe0_stream",
1767                                 "vfe1",
1768                                 "csi_vfe1",
1769                                 "vfe1_ahb",
1770                                 "vfe1_stream",
1771                                 "vfe_ahb",
1772                                 "vfe_axi";
1773                         vdda-supply = <&pm8994_l2>;
1774                         iommus = <&vfe_smmu 0>,
1775                                  <&vfe_smmu 1>,
1776                                  <&vfe_smmu 2>,
1777                                  <&vfe_smmu 3>;
1778                         status = "disabled";
1779                         ports {
1780                                 #address-cells = <1>;
1781                                 #size-cells = <0>;
1782                         };
1783                 };
1784
1785                 adreno_smmu: iommu@b40000 {
1786                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1787                         reg = <0xb40000 0x10000>;
1788
1789                         #global-interrupts = <1>;
1790                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1791                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1792                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1793                         #iommu-cells = <1>;
1794
1795                         clocks = <&mmcc GPU_AHB_CLK>,
1796                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1797                         clock-names = "iface", "bus";
1798
1799                         power-domains = <&mmcc GPU_GDSC>;
1800                 };
1801
1802                 mdp_smmu: iommu@d00000 {
1803                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1804                         reg = <0xd00000 0x10000>;
1805
1806                         #global-interrupts = <1>;
1807                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1808                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1809                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1810                         #iommu-cells = <1>;
1811                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1812                                  <&mmcc SMMU_MDP_AXI_CLK>;
1813                         clock-names = "iface", "bus";
1814
1815                         power-domains = <&mmcc MDSS_GDSC>;
1816                 };
1817
1818                 lpass_q6_smmu: iommu@1600000 {
1819                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1820                         reg = <0x1600000 0x20000>;
1821                         #iommu-cells = <1>;
1822                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1823
1824                         #global-interrupts = <1>;
1825                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1826                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1827                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1828                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1829                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1830                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1831                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1832                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1833                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1834                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1835                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1836                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1837                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1838
1839                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1840                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1841                         clock-names = "iface", "bus";
1842                 };
1843
1844                 agnoc@0 {
1845                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1846                         compatible = "simple-pm-bus";
1847                         #address-cells = <1>;
1848                         #size-cells = <1>;
1849                         ranges;
1850
1851                         pcie0: pcie@600000 {
1852                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1853                                 status = "disabled";
1854                                 power-domains = <&gcc PCIE0_GDSC>;
1855                                 bus-range = <0x00 0xff>;
1856                                 num-lanes = <1>;
1857
1858                                 reg = <0x00600000 0x2000>,
1859                                       <0x0c000000 0xf1d>,
1860                                       <0x0c000f20 0xa8>,
1861                                       <0x0c100000 0x100000>;
1862                                 reg-names = "parf", "dbi", "elbi","config";
1863
1864                                 phys = <&pciephy_0>;
1865                                 phy-names = "pciephy";
1866
1867                                 #address-cells = <3>;
1868                                 #size-cells = <2>;
1869                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1870                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1871
1872                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1873                                 interrupt-names = "msi";
1874                                 #interrupt-cells = <1>;
1875                                 interrupt-map-mask = <0 0 0 0x7>;
1876                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1877                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1878                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1879                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1880
1881                                 pinctrl-names = "default", "sleep";
1882                                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1883                                 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
1884
1885
1886                                 vdda-supply = <&pm8994_l28>;
1887
1888                                 linux,pci-domain = <0>;
1889
1890                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1891                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1892                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1893                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1894                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1895
1896                                 clock-names =  "pipe",
1897                                                 "aux",
1898                                                 "cfg",
1899                                                 "bus_master",
1900                                                 "bus_slave";
1901
1902                         };
1903
1904                         pcie1: pcie@608000 {
1905                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1906                                 power-domains = <&gcc PCIE1_GDSC>;
1907                                 bus-range = <0x00 0xff>;
1908                                 num-lanes = <1>;
1909
1910                                 status  = "disabled";
1911
1912                                 reg = <0x00608000 0x2000>,
1913                                       <0x0d000000 0xf1d>,
1914                                       <0x0d000f20 0xa8>,
1915                                       <0x0d100000 0x100000>;
1916
1917                                 reg-names = "parf", "dbi", "elbi","config";
1918
1919                                 phys = <&pciephy_1>;
1920                                 phy-names = "pciephy";
1921
1922                                 #address-cells = <3>;
1923                                 #size-cells = <2>;
1924                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1925                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1926
1927                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1928                                 interrupt-names = "msi";
1929                                 #interrupt-cells = <1>;
1930                                 interrupt-map-mask = <0 0 0 0x7>;
1931                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1932                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1933                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1934                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1935
1936                                 pinctrl-names = "default", "sleep";
1937                                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1938                                 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1939
1940
1941                                 vdda-supply = <&pm8994_l28>;
1942                                 linux,pci-domain = <1>;
1943
1944                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1945                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1946                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1947                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1948                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1949
1950                                 clock-names =  "pipe",
1951                                                 "aux",
1952                                                 "cfg",
1953                                                 "bus_master",
1954                                                 "bus_slave";
1955                         };
1956
1957                         pcie2: pcie@610000 {
1958                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1959                                 power-domains = <&gcc PCIE2_GDSC>;
1960                                 bus-range = <0x00 0xff>;
1961                                 num-lanes = <1>;
1962                                 status = "disabled";
1963                                 reg = <0x00610000 0x2000>,
1964                                       <0x0e000000 0xf1d>,
1965                                       <0x0e000f20 0xa8>,
1966                                       <0x0e100000 0x100000>;
1967
1968                                 reg-names = "parf", "dbi", "elbi","config";
1969
1970                                 phys = <&pciephy_2>;
1971                                 phy-names = "pciephy";
1972
1973                                 #address-cells = <3>;
1974                                 #size-cells = <2>;
1975                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1976                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1977
1978                                 device_type = "pci";
1979
1980                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1981                                 interrupt-names = "msi";
1982                                 #interrupt-cells = <1>;
1983                                 interrupt-map-mask = <0 0 0 0x7>;
1984                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1985                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1986                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1987                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1988
1989                                 pinctrl-names = "default", "sleep";
1990                                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1991                                 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1992
1993                                 vdda-supply = <&pm8994_l28>;
1994
1995                                 linux,pci-domain = <2>;
1996                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1997                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1998                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1999                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
2000                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
2001
2002                                 clock-names =  "pipe",
2003                                                 "aux",
2004                                                 "cfg",
2005                                                 "bus_master",
2006                                                 "bus_slave";
2007                         };
2008                 };
2009
2010                 slimbam:dma@9184000
2011                 {
2012                         compatible = "qcom,bam-v1.7.0";
2013                         qcom,controlled-remotely;
2014                         reg = <0x9184000 0x32000>;
2015                         num-channels  = <31>;
2016                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2017                         #dma-cells = <1>;
2018                         qcom,ee = <1>;
2019                         qcom,num-ees = <2>;
2020                 };
2021
2022                 slim_msm: slim@91c0000 {
2023                         compatible = "qcom,slim-ngd-v1.5.0";
2024                         reg = <0x91c0000 0x2C000>;
2025                         reg-names = "ctrl";
2026                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2027                         dmas =  <&slimbam 3>, <&slimbam 4>,
2028                                 <&slimbam 5>, <&slimbam 6>;
2029                         dma-names = "rx", "tx", "tx2", "rx2";
2030                         #address-cells = <1>;
2031                         #size-cells = <0>;
2032                         ngd@1 {
2033                                 reg = <1>;
2034                                 #address-cells = <1>;
2035                                 #size-cells = <1>;
2036
2037                                 tasha_ifd: tas-ifd {
2038                                         compatible = "slim217,1a0";
2039                                         reg  = <0 0>;
2040                                 };
2041
2042                                 wcd9335: codec@1{
2043                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2044                                         pinctrl-names = "default";
2045
2046                                         compatible = "slim217,1a0";
2047                                         reg  = <1 0>;
2048
2049                                         interrupt-parent = <&msmgpio>;
2050                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2051                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
2052                                         interrupt-names  = "intr1", "intr2";
2053                                         interrupt-controller;
2054                                         #interrupt-cells = <1>;
2055                                         reset-gpios = <&msmgpio 64 0>;
2056
2057                                         slim-ifc-dev  = <&tasha_ifd>;
2058
2059                                         vdd-buck-supply = <&pm8994_s4>;
2060                                         vdd-buck-sido-supply = <&pm8994_s4>;
2061                                         vdd-tx-supply = <&pm8994_s4>;
2062                                         vdd-rx-supply = <&pm8994_s4>;
2063                                         vdd-io-supply = <&pm8994_s4>;
2064
2065                                         #sound-dai-cells = <1>;
2066                                 };
2067                         };
2068                 };
2069
2070                 gpu@b00000 {
2071                         compatible = "qcom,adreno-530.2", "qcom,adreno";
2072                         #stream-id-cells = <16>;
2073
2074                         reg = <0xb00000 0x3f000>;
2075                         reg-names = "kgsl_3d0_reg_memory";
2076
2077                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
2078
2079                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
2080                                 <&mmcc GPU_AHB_CLK>,
2081                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
2082                                 <&gcc GCC_BIMC_GFX_CLK>,
2083                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
2084
2085                         clock-names = "core",
2086                                 "iface",
2087                                 "rbbmtimer",
2088                                 "mem",
2089                                 "mem_iface";
2090
2091                         power-domains = <&mmcc GPU_GDSC>;
2092                         iommus = <&adreno_smmu 0>;
2093
2094                         nvmem-cells = <&gpu_speed_bin>;
2095                         nvmem-cell-names = "speed_bin";
2096
2097                         qcom,gpu-quirk-two-pass-use-wfi;
2098                         qcom,gpu-quirk-fault-detect-mask;
2099
2100                         operating-points-v2 = <&gpu_opp_table>;
2101
2102                         gpu_opp_table: opp-table {
2103                                 compatible  ="operating-points-v2";
2104
2105                                 /*
2106                                  * 624Mhz and 560Mhz are only available on speed
2107                                  * bin (1 << 0). All the rest are available on
2108                                  * all bins of the hardware
2109                                  */
2110                                 opp-624000000 {
2111                                         opp-hz = /bits/ 64 <624000000>;
2112                                         opp-supported-hw = <0x01>;
2113                                 };
2114                                 opp-560000000 {
2115                                         opp-hz = /bits/ 64 <560000000>;
2116                                         opp-supported-hw = <0x01>;
2117                                 };
2118                                 opp-510000000 {
2119                                         opp-hz = /bits/ 64 <510000000>;
2120                                         opp-supported-hw = <0xFF>;
2121                                 };
2122                                 opp-401800000 {
2123                                         opp-hz = /bits/ 64 <401800000>;
2124                                         opp-supported-hw = <0xFF>;
2125                                 };
2126                                 opp-315000000 {
2127                                         opp-hz = /bits/ 64 <315000000>;
2128                                         opp-supported-hw = <0xFF>;
2129                                 };
2130                                 opp-214000000 {
2131                                         opp-hz = /bits/ 64 <214000000>;
2132                                         opp-supported-hw = <0xFF>;
2133                                 };
2134                                 opp-133000000 {
2135                                         opp-hz = /bits/ 64 <133000000>;
2136                                         opp-supported-hw = <0xFF>;
2137                                 };
2138                         };
2139
2140                         zap-shader {
2141                                 memory-region = <&zap_shader_region>;
2142                         };
2143                 };
2144
2145                 mdss: mdss@900000 {
2146                         compatible = "qcom,mdss";
2147
2148                         reg = <0x900000 0x1000>,
2149                               <0x9b0000 0x1040>,
2150                               <0x9b8000 0x1040>;
2151                         reg-names = "mdss_phys",
2152                                     "vbif_phys",
2153                                     "vbif_nrt_phys";
2154
2155                         power-domains = <&mmcc MDSS_GDSC>;
2156                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2157
2158                         interrupt-controller;
2159                         #interrupt-cells = <1>;
2160
2161                         clocks = <&mmcc MDSS_AHB_CLK>;
2162                         clock-names = "iface";
2163
2164                         #address-cells = <1>;
2165                         #size-cells = <1>;
2166                         ranges;
2167
2168                         mdp: mdp@901000 {
2169                                 compatible = "qcom,mdp5";
2170                                 reg = <0x901000 0x90000>;
2171                                 reg-names = "mdp_phys";
2172
2173                                 interrupt-parent = <&mdss>;
2174                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
2175
2176                                 clocks = <&mmcc MDSS_AHB_CLK>,
2177                                          <&mmcc MDSS_AXI_CLK>,
2178                                          <&mmcc MDSS_MDP_CLK>,
2179                                          <&mmcc SMMU_MDP_AXI_CLK>,
2180                                          <&mmcc MDSS_VSYNC_CLK>;
2181                                 clock-names = "iface",
2182                                               "bus",
2183                                               "core",
2184                                               "iommu",
2185                                               "vsync";
2186
2187                                 iommus = <&mdp_smmu 0>;
2188
2189                                 ports {
2190                                         #address-cells = <1>;
2191                                         #size-cells = <0>;
2192
2193                                         port@0 {
2194                                                 reg = <0>;
2195                                                 mdp5_intf3_out: endpoint {
2196                                                         remote-endpoint = <&hdmi_in>;
2197                                                 };
2198                                         };
2199                                 };
2200                         };
2201
2202                         hdmi: hdmi-tx@9a0000 {
2203                                 compatible = "qcom,hdmi-tx-8996";
2204                                 reg =   <0x009a0000 0x50c>,
2205                                         <0x00070000 0x6158>,
2206                                         <0x009e0000 0xfff>;
2207                                 reg-names = "core_physical",
2208                                             "qfprom_physical",
2209                                             "hdcp_physical";
2210
2211                                 interrupt-parent = <&mdss>;
2212                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
2213
2214                                 clocks = <&mmcc MDSS_MDP_CLK>,
2215                                          <&mmcc MDSS_AHB_CLK>,
2216                                          <&mmcc MDSS_HDMI_CLK>,
2217                                          <&mmcc MDSS_HDMI_AHB_CLK>,
2218                                          <&mmcc MDSS_EXTPCLK_CLK>;
2219                                 clock-names =
2220                                         "mdp_core",
2221                                         "iface",
2222                                         "core",
2223                                         "alt_iface",
2224                                         "extp";
2225
2226                                 phys = <&hdmi_phy>;
2227                                 phy-names = "hdmi_phy";
2228                                 #sound-dai-cells = <1>;
2229
2230                                 ports {
2231                                         #address-cells = <1>;
2232                                         #size-cells = <0>;
2233
2234                                         port@0 {
2235                                                 reg = <0>;
2236                                                 hdmi_in: endpoint {
2237                                                         remote-endpoint = <&mdp5_intf3_out>;
2238                                                 };
2239                                         };
2240                                 };
2241                         };
2242
2243                         hdmi_phy: hdmi-phy@9a0600 {
2244                                 #phy-cells = <0>;
2245                                 compatible = "qcom,hdmi-phy-8996";
2246                                 reg = <0x9a0600 0x1c4>,
2247                                       <0x9a0a00 0x124>,
2248                                       <0x9a0c00 0x124>,
2249                                       <0x9a0e00 0x124>,
2250                                       <0x9a1000 0x124>,
2251                                       <0x9a1200 0x0c8>;
2252                                 reg-names = "hdmi_pll",
2253                                             "hdmi_tx_l0",
2254                                             "hdmi_tx_l1",
2255                                             "hdmi_tx_l2",
2256                                             "hdmi_tx_l3",
2257                                             "hdmi_phy";
2258
2259                                 clocks = <&mmcc MDSS_AHB_CLK>,
2260                                          <&gcc GCC_HDMI_CLKREF_CLK>;
2261                                 clock-names = "iface",
2262                                               "ref";
2263                         };
2264                 };
2265
2266                 venus_smmu: arm,smmu-venus@d40000 {
2267                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2268                         reg = <0xd40000 0x20000>;
2269                         #global-interrupts = <1>;
2270                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
2271                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
2272                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
2273                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
2274                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
2275                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
2276                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
2277                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
2278                         power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2279                         clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
2280                                  <&mmcc SMMU_VIDEO_AXI_CLK>;
2281                         clock-names = "iface", "bus";
2282                         #iommu-cells = <1>;
2283                         status = "okay";
2284                 };
2285
2286                 video-codec@c00000 {
2287                         compatible = "qcom,msm8996-venus";
2288                         reg = <0x00c00000 0xff000>;
2289                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2290                         power-domains = <&mmcc VENUS_GDSC>;
2291                         clocks = <&mmcc VIDEO_CORE_CLK>,
2292                                  <&mmcc VIDEO_AHB_CLK>,
2293                                  <&mmcc VIDEO_AXI_CLK>,
2294                                  <&mmcc VIDEO_MAXI_CLK>;
2295                         clock-names = "core", "iface", "bus", "mbus";
2296                         iommus = <&venus_smmu 0x00>,
2297                                  <&venus_smmu 0x01>,
2298                                  <&venus_smmu 0x0a>,
2299                                  <&venus_smmu 0x07>,
2300                                  <&venus_smmu 0x0e>,
2301                                  <&venus_smmu 0x0f>,
2302                                  <&venus_smmu 0x08>,
2303                                  <&venus_smmu 0x09>,
2304                                  <&venus_smmu 0x0b>,
2305                                  <&venus_smmu 0x0c>,
2306                                  <&venus_smmu 0x0d>,
2307                                  <&venus_smmu 0x10>,
2308                                  <&venus_smmu 0x11>,
2309                                  <&venus_smmu 0x21>,
2310                                  <&venus_smmu 0x28>,
2311                                  <&venus_smmu 0x29>,
2312                                  <&venus_smmu 0x2b>,
2313                                  <&venus_smmu 0x2c>,
2314                                  <&venus_smmu 0x2d>,
2315                                  <&venus_smmu 0x31>;
2316                         memory-region = <&venus_region>;
2317                         status = "okay";
2318
2319                         video-decoder {
2320                                 compatible = "venus-decoder";
2321                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2322                                 clock-names = "core";
2323                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2324                         };
2325
2326                         video-encoder {
2327                                 compatible = "venus-encoder";
2328                                 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2329                                 clock-names = "core";
2330                                 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2331                         };
2332                 };
2333         };
2334
2335         sound: sound {
2336         };
2337
2338         adsp-pil {
2339                 compatible = "qcom,msm8996-adsp-pil";
2340
2341                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2342                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2343                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2344                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2345                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2346                 interrupt-names = "wdog", "fatal", "ready",
2347                                   "handover", "stop-ack";
2348
2349                 clocks = <&xo_board>;
2350                 clock-names = "xo";
2351
2352                 memory-region = <&adsp_region>;
2353
2354                 qcom,smem-states = <&adsp_smp2p_out 0>;
2355                 qcom,smem-state-names = "stop";
2356
2357                 smd-edge {
2358                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2359
2360                         label = "lpass";
2361                         mboxes = <&apcs_glb 8>;
2362                         qcom,smd-edge = <1>;
2363                         qcom,remote-pid = <2>;
2364                         #address-cells = <1>;
2365                         #size-cells = <0>;
2366                         apr {
2367                                 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2368                                 compatible = "qcom,apr-v2";
2369                                 qcom,smd-channels = "apr_audio_svc";
2370                                 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2371                                 #address-cells = <1>;
2372                                 #size-cells = <0>;
2373
2374                                 q6core {
2375                                         reg = <APR_SVC_ADSP_CORE>;
2376                                         compatible = "qcom,q6core";
2377                                 };
2378
2379                                 q6afe: q6afe {
2380                                         compatible = "qcom,q6afe";
2381                                         reg = <APR_SVC_AFE>;
2382                                         q6afedai: dais {
2383                                                 compatible = "qcom,q6afe-dais";
2384                                                 #address-cells = <1>;
2385                                                 #size-cells = <0>;
2386                                                 #sound-dai-cells = <1>;
2387                                                 hdmi@1 {
2388                                                         reg = <1>;
2389                                                 };
2390                                         };
2391                                 };
2392
2393                                 q6asm: q6asm {
2394                                         compatible = "qcom,q6asm";
2395                                         reg = <APR_SVC_ASM>;
2396                                         q6asmdai: dais {
2397                                                 compatible = "qcom,q6asm-dais";
2398                                                 #sound-dai-cells = <1>;
2399                                                 iommus = <&lpass_q6_smmu 1>;
2400                                         };
2401                                 };
2402
2403                                 q6adm: q6adm {
2404                                         compatible = "qcom,q6adm";
2405                                         reg = <APR_SVC_ADM>;
2406                                         q6routing: routing {
2407                                                 compatible = "qcom,q6adm-routing";
2408                                                 #sound-dai-cells = <0>;
2409                                         };
2410                                 };
2411                         };
2412
2413                 };
2414         };
2415
2416         adsp-smp2p {
2417                 compatible = "qcom,smp2p";
2418                 qcom,smem = <443>, <429>;
2419
2420                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
2421
2422                 mboxes = <&apcs_glb 10>;
2423
2424                 qcom,local-pid = <0>;
2425                 qcom,remote-pid = <2>;
2426
2427                 adsp_smp2p_out: master-kernel {
2428                         qcom,entry-name = "master-kernel";
2429                         #qcom,smem-state-cells = <1>;
2430                 };
2431
2432                 adsp_smp2p_in: slave-kernel {
2433                         qcom,entry-name = "slave-kernel";
2434
2435                         interrupt-controller;
2436                         #interrupt-cells = <2>;
2437                 };
2438         };
2439
2440         modem-smp2p {
2441                 compatible = "qcom,smp2p";
2442                 qcom,smem = <435>, <428>;
2443
2444                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
2445
2446                 mboxes = <&apcs_glb 14>;
2447
2448                 qcom,local-pid = <0>;
2449                 qcom,remote-pid = <1>;
2450
2451                 modem_smp2p_out: master-kernel {
2452                         qcom,entry-name = "master-kernel";
2453                         #qcom,smem-state-cells = <1>;
2454                 };
2455
2456                 modem_smp2p_in: slave-kernel {
2457                         qcom,entry-name = "slave-kernel";
2458
2459                         interrupt-controller;
2460                         #interrupt-cells = <2>;
2461                 };
2462         };
2463
2464         smp2p-slpi {
2465                 compatible = "qcom,smp2p";
2466                 qcom,smem = <481>, <430>;
2467
2468                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
2469
2470                 mboxes = <&apcs_glb 26>;
2471
2472                 qcom,local-pid = <0>;
2473                 qcom,remote-pid = <3>;
2474
2475                 slpi_smp2p_in: slave-kernel {
2476                         qcom,entry-name = "slave-kernel";
2477                         interrupt-controller;
2478                         #interrupt-cells = <2>;
2479                 };
2480
2481                 slpi_smp2p_out: master-kernel {
2482                         qcom,entry-name = "master-kernel";
2483                         #qcom,smem-state-cells = <1>;
2484                 };
2485         };
2486
2487 };
2488 #include "msm8996-pins.dtsi"