arch/arm64/boot/dts/qcom/msm8994.dtsi

   1 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
  15
  16 / {
  17         model = "Qualcomm Technologies, Inc. MSM 8994";
  18         compatible = "qcom,msm8994";
  19         // msm-id and pmic-id are required by bootloader for
  20         // proper selection of dt blob
  21         qcom,msm-id = <207 0x20000>;
  22         qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
  23         interrupt-parent = <&intc>;
  24
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27
  28         chosen { };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 cpu-map {
  34                         cluster0 {
  35                                 core0 {
  36                                         cpu = <&CPU0>;
  37                                 };
  38                         };
  39                 };
  40
  41                 CPU0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0x0>;
  45                         next-level-cache = <&L2_0>;
  46                         L2_0: l2-cache {
  47                               compatible = "cache";
  48                               cache-level = <2>;
  49                         };
  50                 };
  51         };
  52
  53         timer {
  54                 compatible = "arm,armv8-timer";
  55                 interrupts = <1 2 0xff08>,
  56                              <1 3 0xff08>,
  57                              <1 4 0xff08>,
  58                              <1 1 0xff08>;
  59         };
  60
  61         soc: soc {
  62
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges = <0 0 0 0xffffffff>;
  66                 compatible = "simple-bus";
  67
  68                 intc: interrupt-controller@f9000000 {
  69                         compatible = "qcom,msm-qgic2";
  70                         interrupt-controller;
  71                         #interrupt-cells = <3>;
  72                         reg = <0xf9000000 0x1000>,
  73                                   <0xf9002000 0x1000>;
  74                 };
  75
  76                 timer@f9020000 {
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79                         ranges;
  80                         compatible = "arm,armv7-timer-mem";
  81                         reg = <0xf9020000 0x1000>;
  82
  83                         frame@f9021000 {
  84                                 frame-number = <0>;
  85                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  86                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  87                                 reg = <0xf9021000 0x1000>,
  88                                       <0xf9022000 0x1000>;
  89                         };
  90
  91                         frame@f9023000 {
  92                                 frame-number = <1>;
  93                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  94                                 reg = <0xf9023000 0x1000>;
  95                                 status = "disabled";
  96                         };
  97
  98                         frame@f9024000 {
  99                                 frame-number = <2>;
 100                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 101                                 reg = <0xf9024000 0x1000>;
 102                                 status = "disabled";
 103                         };
 104
 105                         frame@f9025000 {
 106                                 frame-number = <3>;
 107                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 108                                 reg = <0xf9025000 0x1000>;
 109                                 status = "disabled";
 110                         };
 111
 112                         frame@f9026000 {
 113                                 frame-number = <4>;
 114                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 115                                 reg = <0xf9026000 0x1000>;
 116                                 status = "disabled";
 117                         };
 118
 119                         frame@f9027000 {
 120                                 frame-number = <5>;
 121                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 122                                 reg = <0xf9027000 0x1000>;
 123                                 status = "disabled";
 124                         };
 125
 126                         frame@f9028000 {
 127                                 frame-number = <6>;
 128                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 129                                 reg = <0xf9028000 0x1000>;
 130                                 status = "disabled";
 131                         };
 132                 };
 133
 134                 restart@fc4ab000 {
 135                         compatible = "qcom,pshold";
 136                         reg = <0xfc4ab000 0x4>;
 137                 };
 138
 139                 msmgpio: pinctrl@fd510000 {
 140                         compatible = "qcom,msm8994-pinctrl";
 141                         reg = <0xfd510000 0x4000>;
 142                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 143                         gpio-controller;
 144                         #gpio-cells = <2>;
 145                         interrupt-controller;
 146                         #interrupt-cells = <2>;
 147                 };
 148
 149                 blsp1_uart2: serial@f991e000 {
 150                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 151                         reg = <0xf991e000 0x1000>;
 152                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 153                         status = "disabled";
 154                         clock-names = "core", "iface";
 155                         clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
 156                                  <&clock_gcc GCC_BLSP1_AHB_CLK>;
 157                 };
 158
 159                 tcsr_mutex_regs: syscon@fd484000 {
 160                         compatible = "syscon";
 161                         reg = <0xfd484000 0x2000>;
 162                 };
 163
 164                 clock_gcc: clock-controller@fc400000 {
 165                         compatible = "qcom,gcc-msm8994";
 166                         #clock-cells = <1>;
 167                         #reset-cells = <1>;
 168                         #power-domain-cells = <1>;
 169                         reg = <0xfc400000 0x2000>;
 170                 };
 171         };
 172
 173         memory {
 174                 device_type = "memory";
 175                 // We expect the bootloader to fill in the reg
 176                 reg = <0 0 0 0>;
 177         };
 178
 179         xo_board: xo_board {
 180                 compatible = "fixed-clock";
 181                 #clock-cells = <0>;
 182                 clock-frequency = <19200000>;
 183         };
 184
 185         sleep_clk: sleep_clk {
 186                 compatible = "fixed-clock";
 187                 #clock-cells = <0>;
 188                 clock-frequency = <32768>;
 189         };
 190
 191         reserved-memory {
 192                 #address-cells = <2>;
 193                 #size-cells = <2>;
 194                 ranges;
 195
 196                 smem_mem: smem_region@6a00000 {
 197                         reg = <0x0 0x6a00000 0x0 0x200000>;
 198                         no-map;
 199                 };
 200         };
 201
 202         tcsr_mutex: hwlock {
 203                 compatible = "qcom,tcsr-mutex";
 204                 syscon = <&tcsr_mutex_regs 0 0x80>;
 205                 #hwlock-cells = <1>;
 206         };
 207
 208         qcom,smem@6a00000 {
 209                 compatible = "qcom,smem";
 210                 memory-region = <&smem_mem>;
 211                 hwlocks = <&tcsr_mutex 3>;
 212         };
 213 };
 214
 215
 216 #include "msm8994-pins.dtsi"