2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
17 #include <dt-bindings/clock/qcom,rpmcc.h>
18 #include <dt-bindings/thermal/thermal.h>
21 interrupt-parent = <&intc>;
27 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
28 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
34 device_type = "memory";
35 /* We expect the bootloader to fill in the reg */
45 reg = <0x0 0x86000000 0x0 0x300000>;
49 smem_mem: smem_region@86300000 {
50 reg = <0x0 0x86300000 0x0 0x100000>;
55 reg = <0x0 0x86400000 0x0 0x100000>;
60 reg = <0x0 0x86500000 0x0 0x180000>;
65 reg = <0x0 0x86680000 0x0 0x80000>;
70 compatible = "qcom,rmtfs-mem";
71 reg = <0x0 0x86700000 0x0 0xe0000>;
78 reg = <0x0 0x867e0000 0x0 0x20000>;
82 mpss_mem: mpss@86800000 {
83 reg = <0x0 0x86800000 0x0 0x2b00000>;
87 wcnss_mem: wcnss@89300000 {
88 reg = <0x0 0x89300000 0x0 0x600000>;
92 venus_mem: venus@89900000 {
93 reg = <0x0 0x89900000 0x0 0x600000>;
97 mba_mem: mba@8ea00000 {
99 reg = <0 0x8ea00000 0 0x100000>;
104 #address-cells = <1>;
109 compatible = "arm,cortex-a53", "arm,armv8";
111 next-level-cache = <&L2_0>;
112 enable-method = "psci";
113 cpu-idle-states = <&CPU_SPC>;
115 operating-points-v2 = <&cpu_opp_table>;
116 #cooling-cells = <2>;
121 compatible = "arm,cortex-a53", "arm,armv8";
123 next-level-cache = <&L2_0>;
124 enable-method = "psci";
125 cpu-idle-states = <&CPU_SPC>;
127 operating-points-v2 = <&cpu_opp_table>;
128 #cooling-cells = <2>;
133 compatible = "arm,cortex-a53", "arm,armv8";
135 next-level-cache = <&L2_0>;
136 enable-method = "psci";
137 cpu-idle-states = <&CPU_SPC>;
139 operating-points-v2 = <&cpu_opp_table>;
140 #cooling-cells = <2>;
145 compatible = "arm,cortex-a53", "arm,armv8";
147 next-level-cache = <&L2_0>;
148 enable-method = "psci";
149 cpu-idle-states = <&CPU_SPC>;
151 operating-points-v2 = <&cpu_opp_table>;
152 #cooling-cells = <2>;
156 compatible = "cache";
162 compatible = "arm,idle-state";
163 arm,psci-suspend-param = <0x40000002>;
164 entry-latency-us = <130>;
165 exit-latency-us = <150>;
166 min-residency-us = <2000>;
173 compatible = "arm,psci-1.0";
178 compatible = "arm,cortex-a53-pmu";
179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
184 polling-delay-passive = <250>;
185 polling-delay = <1000>;
187 thermal-sensors = <&tsens 4>;
191 temperature = <75000>;
196 temperature = <110000>;
204 trip = <&cpu_alert0>;
205 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211 polling-delay-passive = <250>;
212 polling-delay = <1000>;
214 thermal-sensors = <&tsens 3>;
218 temperature = <75000>;
223 temperature = <110000>;
231 trip = <&cpu_alert1>;
232 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
239 cpu_opp_table: cpu_opp_table {
240 compatible = "operating-points-v2";
244 opp-hz = /bits/ 64 <200000000>;
247 opp-hz = /bits/ 64 <400000000>;
250 opp-hz = /bits/ 64 <800000000>;
253 opp-hz = /bits/ 64 <998400000>;
257 gpu_opp_table: opp_table {
258 compatible = "operating-points-v2";
261 opp-hz = /bits/ 64 <400000000>;
264 opp-hz = /bits/ 64 <19200000>;
269 compatible = "arm,armv8-timer";
270 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
271 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
272 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
273 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
278 compatible = "fixed-clock";
280 clock-frequency = <19200000>;
283 sleep_clk: sleep_clk {
284 compatible = "fixed-clock";
286 clock-frequency = <32768>;
291 compatible = "qcom,smem";
293 memory-region = <&smem_mem>;
294 qcom,rpm-msg-ram = <&rpm_msg_ram>;
296 hwlocks = <&tcsr_mutex 3>;
301 compatible = "qcom,scm";
302 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
303 clock-names = "core", "bus", "iface";
306 qcom,dload-mode = <&tcsr 0x6100>;
311 #address-cells = <1>;
313 ranges = <0 0 0 0xffffffff>;
314 compatible = "simple-bus";
317 compatible = "qcom,pshold";
318 reg = <0x4ab000 0x4>;
321 msmgpio: pinctrl@1000000 {
322 compatible = "qcom,msm8916-pinctrl";
323 reg = <0x1000000 0x300000>;
324 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
327 interrupt-controller;
328 #interrupt-cells = <2>;
331 gcc: clock-controller@1800000 {
332 compatible = "qcom,gcc-msm8916";
335 #power-domain-cells = <1>;
336 reg = <0x1800000 0x80000>;
339 tcsr_mutex_regs: syscon@1905000 {
340 compatible = "syscon";
341 reg = <0x1905000 0x20000>;
344 tcsr: syscon@1937000 {
345 compatible = "qcom,tcsr-msm8916", "syscon";
346 reg = <0x1937000 0x30000>;
350 compatible = "qcom,tcsr-mutex";
351 syscon = <&tcsr_mutex_regs 0 0x1000>;
355 rpm_msg_ram: memory@60000 {
356 compatible = "qcom,rpm-msg-ram";
357 reg = <0x60000 0x8000>;
360 blsp1_uart1: serial@78af000 {
361 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
362 reg = <0x78af000 0x200>;
363 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
365 clock-names = "core", "iface";
366 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
367 dma-names = "rx", "tx";
371 a53pll: clock@b016000 {
372 compatible = "qcom,msm8916-a53pll";
373 reg = <0xb016000 0x40>;
377 apcs: mailbox@b011000 {
378 compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
379 reg = <0xb011000 0x1000>;
385 blsp1_uart2: serial@78b0000 {
386 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
387 reg = <0x78b0000 0x200>;
388 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", "iface";
391 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
392 dma-names = "rx", "tx";
396 blsp_dma: dma@7884000 {
397 compatible = "qcom,bam-v1.7.0";
398 reg = <0x07884000 0x23000>;
399 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
401 clock-names = "bam_clk";
407 blsp_spi1: spi@78b5000 {
408 compatible = "qcom,spi-qup-v2.2.1";
409 reg = <0x078b5000 0x500>;
410 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
412 <&gcc GCC_BLSP1_AHB_CLK>;
413 clock-names = "core", "iface";
414 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
415 dma-names = "rx", "tx";
416 pinctrl-names = "default", "sleep";
417 pinctrl-0 = <&spi1_default>;
418 pinctrl-1 = <&spi1_sleep>;
419 #address-cells = <1>;
424 blsp_spi2: spi@78b6000 {
425 compatible = "qcom,spi-qup-v2.2.1";
426 reg = <0x078b6000 0x500>;
427 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
429 <&gcc GCC_BLSP1_AHB_CLK>;
430 clock-names = "core", "iface";
431 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
432 dma-names = "rx", "tx";
433 pinctrl-names = "default", "sleep";
434 pinctrl-0 = <&spi2_default>;
435 pinctrl-1 = <&spi2_sleep>;
436 #address-cells = <1>;
441 blsp_spi3: spi@78b7000 {
442 compatible = "qcom,spi-qup-v2.2.1";
443 reg = <0x078b7000 0x500>;
444 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
446 <&gcc GCC_BLSP1_AHB_CLK>;
447 clock-names = "core", "iface";
448 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
449 dma-names = "rx", "tx";
450 pinctrl-names = "default", "sleep";
451 pinctrl-0 = <&spi3_default>;
452 pinctrl-1 = <&spi3_sleep>;
453 #address-cells = <1>;
458 blsp_spi4: spi@78b8000 {
459 compatible = "qcom,spi-qup-v2.2.1";
460 reg = <0x078b8000 0x500>;
461 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
463 <&gcc GCC_BLSP1_AHB_CLK>;
464 clock-names = "core", "iface";
465 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
466 dma-names = "rx", "tx";
467 pinctrl-names = "default", "sleep";
468 pinctrl-0 = <&spi4_default>;
469 pinctrl-1 = <&spi4_sleep>;
470 #address-cells = <1>;
475 blsp_spi5: spi@78b9000 {
476 compatible = "qcom,spi-qup-v2.2.1";
477 reg = <0x078b9000 0x500>;
478 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
480 <&gcc GCC_BLSP1_AHB_CLK>;
481 clock-names = "core", "iface";
482 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
483 dma-names = "rx", "tx";
484 pinctrl-names = "default", "sleep";
485 pinctrl-0 = <&spi5_default>;
486 pinctrl-1 = <&spi5_sleep>;
487 #address-cells = <1>;
492 blsp_spi6: spi@78ba000 {
493 compatible = "qcom,spi-qup-v2.2.1";
494 reg = <0x078ba000 0x500>;
495 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
497 <&gcc GCC_BLSP1_AHB_CLK>;
498 clock-names = "core", "iface";
499 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
500 dma-names = "rx", "tx";
501 pinctrl-names = "default", "sleep";
502 pinctrl-0 = <&spi6_default>;
503 pinctrl-1 = <&spi6_sleep>;
504 #address-cells = <1>;
509 blsp_i2c2: i2c@78b6000 {
510 compatible = "qcom,i2c-qup-v2.2.1";
511 reg = <0x078b6000 0x500>;
512 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
514 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
515 clock-names = "iface", "core";
516 pinctrl-names = "default", "sleep";
517 pinctrl-0 = <&i2c2_default>;
518 pinctrl-1 = <&i2c2_sleep>;
519 #address-cells = <1>;
524 blsp_i2c4: i2c@78b8000 {
525 compatible = "qcom,i2c-qup-v2.2.1";
526 reg = <0x078b8000 0x500>;
527 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
529 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
530 clock-names = "iface", "core";
531 pinctrl-names = "default", "sleep";
532 pinctrl-0 = <&i2c4_default>;
533 pinctrl-1 = <&i2c4_sleep>;
534 #address-cells = <1>;
539 blsp_i2c6: i2c@78ba000 {
540 compatible = "qcom,i2c-qup-v2.2.1";
541 reg = <0x078ba000 0x500>;
542 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
543 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
544 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
545 clock-names = "iface", "core";
546 pinctrl-names = "default", "sleep";
547 pinctrl-0 = <&i2c6_default>;
548 pinctrl-1 = <&i2c6_sleep>;
549 #address-cells = <1>;
554 lpass: lpass@7708000 {
556 compatible = "qcom,lpass-cpu-apq8016";
557 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
558 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
559 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
560 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
561 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
562 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
563 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
565 clock-names = "ahbix-clk",
572 #sound-dai-cells = <1>;
574 interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
575 interrupt-names = "lpass-irq-lpaif";
576 reg = <0x07708000 0x10000>;
577 reg-names = "lpass-lpaif";
581 compatible = "qcom,msm8916-wcd-digital-codec";
582 reg = <0x0771c000 0x400>;
583 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
584 <&gcc GCC_CODEC_DIGCODEC_CLK>;
585 clock-names = "ahbix-clk", "mclk";
586 #sound-dai-cells = <1>;
589 sdhc_1: sdhci@7824000 {
590 compatible = "qcom,sdhci-msm-v4";
591 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
592 reg-names = "hc_mem", "core_mem";
594 interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
595 interrupt-names = "hc_irq", "pwr_irq";
596 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
597 <&gcc GCC_SDCC1_AHB_CLK>,
599 clock-names = "core", "iface", "xo";
606 sdhc_2: sdhci@7864000 {
607 compatible = "qcom,sdhci-msm-v4";
608 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
609 reg-names = "hc_mem", "core_mem";
611 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
612 interrupt-names = "hc_irq", "pwr_irq";
613 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
614 <&gcc GCC_SDCC2_AHB_CLK>,
616 clock-names = "core", "iface", "xo";
622 compatible = "qcom,ci-hdrc";
623 reg = <0x78d9000 0x200>,
625 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
628 <&gcc GCC_USB_HS_SYSTEM_CLK>;
629 clock-names = "iface", "core";
630 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
631 assigned-clock-rates = <80000000>;
632 resets = <&gcc GCC_USB_HS_BCR>;
633 reset-names = "core";
636 ahb-burst-config = <0>;
637 phy-names = "usb-phy";
638 phys = <&usb_hs_phy>;
644 compatible = "qcom,usb-hs-phy-msm8916",
647 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
648 clock-names = "ref", "sleep";
649 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
650 reset-names = "phy", "por";
651 qcom,init-seq = /bits/ 8 <0x0 0x44
652 0x1 0x6b 0x2 0x24 0x3 0x13>;
657 intc: interrupt-controller@b000000 {
658 compatible = "qcom,msm-qgic2";
659 interrupt-controller;
660 #interrupt-cells = <3>;
661 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
665 #address-cells = <1>;
668 compatible = "arm,armv7-timer-mem";
669 reg = <0xb020000 0x1000>;
670 clock-frequency = <19200000>;
674 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
676 reg = <0xb021000 0x1000>,
682 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
683 reg = <0xb023000 0x1000>;
689 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
690 reg = <0xb024000 0x1000>;
696 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
697 reg = <0xb025000 0x1000>;
703 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
704 reg = <0xb026000 0x1000>;
710 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
711 reg = <0xb027000 0x1000>;
717 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
718 reg = <0xb028000 0x1000>;
723 spmi_bus: spmi@200f000 {
724 compatible = "qcom,spmi-pmic-arb";
725 reg = <0x200f000 0x001000>,
726 <0x2400000 0x400000>,
727 <0x2c00000 0x400000>,
728 <0x3800000 0x200000>,
729 <0x200a000 0x002100>;
730 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
731 interrupt-names = "periph_irq";
732 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
735 #address-cells = <2>;
737 interrupt-controller;
738 #interrupt-cells = <4>;
742 compatible = "qcom,prng";
743 reg = <0x00022000 0x200>;
744 clocks = <&gcc GCC_PRNG_AHB_CLK>;
745 clock-names = "core";
748 qfprom: qfprom@5c000 {
749 compatible = "qcom,qfprom";
750 reg = <0x5c000 0x1000>;
751 #address-cells = <1>;
753 tsens_caldata: caldata@d0 {
756 tsens_calsel: calsel@ec {
761 tsens: thermal-sensor@4a8000 {
762 compatible = "qcom,msm8916-tsens";
763 reg = <0x4a8000 0x2000>;
764 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
765 nvmem-cell-names = "calib", "calib_sel";
766 #thermal-sensor-cells = <1>;
769 apps_iommu: iommu@1ef0000 {
770 #address-cells = <1>;
773 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
774 ranges = <0 0x1e20000 0x40000>;
775 reg = <0x1ef0000 0x3000>;
776 clocks = <&gcc GCC_SMMU_CFG_CLK>,
777 <&gcc GCC_APSS_TCU_CLK>;
778 clock-names = "iface", "bus";
779 qcom,iommu-secure-id = <17>;
783 compatible = "qcom,msm-iommu-v1-ns";
784 reg = <0x4000 0x1000>;
785 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
790 compatible = "qcom,msm-iommu-v1-sec";
791 reg = <0x5000 0x1000>;
792 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
796 gpu_iommu: iommu@1f08000 {
797 #address-cells = <1>;
800 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
801 ranges = <0 0x1f08000 0x10000>;
802 clocks = <&gcc GCC_SMMU_CFG_CLK>,
803 <&gcc GCC_GFX_TCU_CLK>;
804 clock-names = "iface", "bus";
805 qcom,iommu-secure-id = <18>;
809 compatible = "qcom,msm-iommu-v1-ns";
810 reg = <0x1000 0x1000>;
811 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
816 compatible = "qcom,msm-iommu-v1-ns";
817 reg = <0x2000 0x1000>;
818 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
823 compatible = "qcom,adreno-306.0", "qcom,adreno";
824 reg = <0x01c00000 0x20000>;
825 reg-names = "kgsl_3d0_reg_memory";
826 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
827 interrupt-names = "kgsl_3d0_irq";
836 <&gcc GCC_OXILI_GFX3D_CLK>,
837 <&gcc GCC_OXILI_AHB_CLK>,
838 <&gcc GCC_OXILI_GMEM_CLK>,
839 <&gcc GCC_BIMC_GFX_CLK>,
840 <&gcc GCC_BIMC_GPU_CLK>,
841 <&gcc GFX3D_CLK_SRC>;
842 power-domains = <&gcc OXILI_GDSC>;
843 operating-points-v2 = <&gpu_opp_table>;
844 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
848 compatible = "qcom,mdss";
849 reg = <0x1a00000 0x1000>,
851 reg-names = "mdss_phys", "vbif_phys";
853 power-domains = <&gcc MDSS_GDSC>;
855 clocks = <&gcc GCC_MDSS_AHB_CLK>,
856 <&gcc GCC_MDSS_AXI_CLK>,
857 <&gcc GCC_MDSS_VSYNC_CLK>;
858 clock-names = "iface",
862 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
864 interrupt-controller;
865 #interrupt-cells = <1>;
867 #address-cells = <1>;
872 compatible = "qcom,mdp5";
873 reg = <0x1a01000 0x89000>;
874 reg-names = "mdp_phys";
876 interrupt-parent = <&mdss>;
879 clocks = <&gcc GCC_MDSS_AHB_CLK>,
880 <&gcc GCC_MDSS_AXI_CLK>,
881 <&gcc GCC_MDSS_MDP_CLK>,
882 <&gcc GCC_MDSS_VSYNC_CLK>;
883 clock-names = "iface",
888 iommus = <&apps_iommu 4>;
891 #address-cells = <1>;
896 mdp5_intf1_out: endpoint {
897 remote-endpoint = <&dsi0_in>;
904 compatible = "qcom,mdss-dsi-ctrl";
905 reg = <0x1a98000 0x25c>;
906 reg-names = "dsi_ctrl";
908 interrupt-parent = <&mdss>;
911 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
912 <&gcc PCLK0_CLK_SRC>;
913 assigned-clock-parents = <&dsi_phy0 0>,
916 clocks = <&gcc GCC_MDSS_MDP_CLK>,
917 <&gcc GCC_MDSS_AHB_CLK>,
918 <&gcc GCC_MDSS_AXI_CLK>,
919 <&gcc GCC_MDSS_BYTE0_CLK>,
920 <&gcc GCC_MDSS_PCLK0_CLK>,
921 <&gcc GCC_MDSS_ESC0_CLK>;
922 clock-names = "mdp_core",
929 phy-names = "dsi-phy";
932 #address-cells = <1>;
938 remote-endpoint = <&mdp5_intf1_out>;
950 dsi_phy0: dsi-phy@1a98300 {
951 compatible = "qcom,dsi-phy-28nm-lp";
952 reg = <0x1a98300 0xd4>,
955 reg-names = "dsi_pll",
962 clocks = <&gcc GCC_MDSS_AHB_CLK>;
963 clock-names = "iface";
969 compatible = "qcom,q6v5-pil";
970 reg = <0x04080000 0x100>,
973 reg-names = "qdsp6", "rmb";
975 interrupts-extended = <&intc 0 24 1>,
976 <&hexagon_smp2p_in 0 0>,
977 <&hexagon_smp2p_in 1 0>,
978 <&hexagon_smp2p_in 2 0>,
979 <&hexagon_smp2p_in 3 0>;
980 interrupt-names = "wdog", "fatal", "ready",
981 "handover", "stop-ack";
983 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
984 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
985 <&gcc GCC_BOOT_ROM_AHB_CLK>,
987 clock-names = "iface", "bus", "mem", "xo";
989 qcom,smem-states = <&hexagon_smp2p_out 0>;
990 qcom,smem-state-names = "stop";
993 reset-names = "mss_restart";
995 cx-supply = <&pm8916_s1>;
996 mx-supply = <&pm8916_l3>;
997 pll-supply = <&pm8916_l7>;
999 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1001 status = "disabled";
1004 memory-region = <&mba_mem>;
1008 memory-region = <&mpss_mem>;
1012 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1014 qcom,smd-edge = <0>;
1015 qcom,ipc = <&apcs 8 12>;
1016 qcom,remote-pid = <1>;
1022 pronto: wcnss@a21b000 {
1023 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1024 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1025 reg-names = "ccu", "dxe", "pmu";
1027 memory-region = <&wcnss_mem>;
1029 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1030 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1031 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1032 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1033 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1034 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1036 vddmx-supply = <&pm8916_l3>;
1037 vddpx-supply = <&pm8916_l7>;
1039 qcom,state = <&wcnss_smp2p_out 0>;
1040 qcom,state-names = "stop";
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&wcnss_pin_a>;
1045 status = "disabled";
1048 compatible = "qcom,wcn3620";
1050 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1053 vddxo-supply = <&pm8916_l7>;
1054 vddrfa-supply = <&pm8916_s3>;
1055 vddpa-supply = <&pm8916_l9>;
1056 vdddig-supply = <&pm8916_l5>;
1060 interrupts = <0 142 1>;
1062 qcom,ipc = <&apcs 8 17>;
1063 qcom,smd-edge = <6>;
1064 qcom,remote-pid = <4>;
1069 compatible = "qcom,wcnss";
1070 qcom,smd-channels = "WCNSS_CTRL";
1072 qcom,mmio = <&pronto>;
1075 compatible = "qcom,wcnss-bt";
1079 compatible = "qcom,wcnss-wlan";
1081 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1082 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1083 interrupt-names = "tx", "rx";
1085 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1086 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1093 compatible = "arm,coresight-tpiu", "arm,primecell";
1094 reg = <0x820000 0x1000>;
1096 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1097 clock-names = "apb_pclk", "atclk";
1102 remote-endpoint = <&replicator_out1>;
1109 compatible = "arm,coresight-funnel", "arm,primecell";
1110 reg = <0x821000 0x1000>;
1112 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1113 clock-names = "apb_pclk", "atclk";
1116 #address-cells = <1>;
1120 * Not described input ports:
1121 * 0 - connected to Resource and Power Manger CPU ETM
1123 * 2 - connected to Modem CPU ETM
1126 * 6 - connected trought funnel to Wireless CPU ETM
1127 * 7 - connected to STM component
1132 funnel0_in4: endpoint {
1133 remote-endpoint = <&funnel1_out>;
1140 funnel0_out: endpoint {
1141 remote-endpoint = <&etf_in>;
1148 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1149 reg = <0x824000 0x1000>;
1151 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1152 clock-names = "apb_pclk", "atclk";
1155 #address-cells = <1>;
1160 replicator_out0: endpoint {
1161 remote-endpoint = <&etr_in>;
1166 replicator_out1: endpoint {
1167 remote-endpoint = <&tpiu_in>;
1174 replicator_in: endpoint {
1175 remote-endpoint = <&etf_out>;
1182 compatible = "arm,coresight-tmc", "arm,primecell";
1183 reg = <0x825000 0x1000>;
1185 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1186 clock-names = "apb_pclk", "atclk";
1191 remote-endpoint = <&funnel0_out>;
1199 remote-endpoint = <&replicator_in>;
1206 compatible = "arm,coresight-tmc", "arm,primecell";
1207 reg = <0x826000 0x1000>;
1209 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1210 clock-names = "apb_pclk", "atclk";
1215 remote-endpoint = <&replicator_out0>;
1221 funnel@841000 { /* APSS funnel only 4 inputs are used */
1222 compatible = "arm,coresight-funnel", "arm,primecell";
1223 reg = <0x841000 0x1000>;
1225 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1226 clock-names = "apb_pclk", "atclk";
1229 #address-cells = <1>;
1234 funnel1_in0: endpoint {
1235 remote-endpoint = <&etm0_out>;
1240 funnel1_in1: endpoint {
1241 remote-endpoint = <&etm1_out>;
1246 funnel1_in2: endpoint {
1247 remote-endpoint = <&etm2_out>;
1252 funnel1_in3: endpoint {
1253 remote-endpoint = <&etm3_out>;
1260 funnel1_out: endpoint {
1261 remote-endpoint = <&funnel0_in4>;
1268 compatible = "arm,coresight-cpu-debug","arm,primecell";
1269 reg = <0x850000 0x1000>;
1270 clocks = <&rpmcc RPM_QDSS_CLK>;
1271 clock-names = "apb_pclk";
1276 compatible = "arm,coresight-cpu-debug","arm,primecell";
1277 reg = <0x852000 0x1000>;
1278 clocks = <&rpmcc RPM_QDSS_CLK>;
1279 clock-names = "apb_pclk";
1284 compatible = "arm,coresight-cpu-debug","arm,primecell";
1285 reg = <0x854000 0x1000>;
1286 clocks = <&rpmcc RPM_QDSS_CLK>;
1287 clock-names = "apb_pclk";
1292 compatible = "arm,coresight-cpu-debug","arm,primecell";
1293 reg = <0x856000 0x1000>;
1294 clocks = <&rpmcc RPM_QDSS_CLK>;
1295 clock-names = "apb_pclk";
1300 compatible = "arm,coresight-etm4x", "arm,primecell";
1301 reg = <0x85c000 0x1000>;
1303 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1304 clock-names = "apb_pclk", "atclk";
1310 etm0_out: endpoint {
1311 remote-endpoint = <&funnel1_in0>;
1318 compatible = "arm,coresight-etm4x", "arm,primecell";
1319 reg = <0x85d000 0x1000>;
1321 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1322 clock-names = "apb_pclk", "atclk";
1328 etm1_out: endpoint {
1329 remote-endpoint = <&funnel1_in1>;
1336 compatible = "arm,coresight-etm4x", "arm,primecell";
1337 reg = <0x85e000 0x1000>;
1339 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1340 clock-names = "apb_pclk", "atclk";
1346 etm2_out: endpoint {
1347 remote-endpoint = <&funnel1_in2>;
1354 compatible = "arm,coresight-etm4x", "arm,primecell";
1355 reg = <0x85f000 0x1000>;
1357 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1358 clock-names = "apb_pclk", "atclk";
1364 etm3_out: endpoint {
1365 remote-endpoint = <&funnel1_in3>;
1371 venus: video-codec@1d00000 {
1372 compatible = "qcom,msm8916-venus";
1373 reg = <0x01d00000 0xff000>;
1374 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1375 power-domains = <&gcc VENUS_GDSC>;
1376 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1377 <&gcc GCC_VENUS0_AHB_CLK>,
1378 <&gcc GCC_VENUS0_AXI_CLK>;
1379 clock-names = "core", "iface", "bus";
1380 iommus = <&apps_iommu 5>;
1381 memory-region = <&venus_mem>;
1385 compatible = "venus-decoder";
1389 compatible = "venus-encoder";
1395 compatible = "qcom,smd";
1398 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1399 qcom,ipc = <&apcs 8 0>;
1400 qcom,smd-edge = <15>;
1403 compatible = "qcom,rpm-msm8916";
1404 qcom,smd-channels = "rpm_requests";
1407 compatible = "qcom,rpmcc-msm8916";
1411 smd_rpm_regulators: pm8916-regulators {
1412 compatible = "qcom,rpm-pm8916-regulators";
1442 compatible = "qcom,smp2p";
1443 qcom,smem = <435>, <428>;
1445 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1447 qcom,ipc = <&apcs 8 14>;
1449 qcom,local-pid = <0>;
1450 qcom,remote-pid = <1>;
1452 hexagon_smp2p_out: master-kernel {
1453 qcom,entry-name = "master-kernel";
1455 #qcom,smem-state-cells = <1>;
1458 hexagon_smp2p_in: slave-kernel {
1459 qcom,entry-name = "slave-kernel";
1461 interrupt-controller;
1462 #interrupt-cells = <2>;
1467 compatible = "qcom,smp2p";
1468 qcom,smem = <451>, <431>;
1470 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1472 qcom,ipc = <&apcs 8 18>;
1474 qcom,local-pid = <0>;
1475 qcom,remote-pid = <4>;
1477 wcnss_smp2p_out: master-kernel {
1478 qcom,entry-name = "master-kernel";
1480 #qcom,smem-state-cells = <1>;
1483 wcnss_smp2p_in: slave-kernel {
1484 qcom,entry-name = "slave-kernel";
1486 interrupt-controller;
1487 #interrupt-cells = <2>;
1492 compatible = "qcom,smsm";
1494 #address-cells = <1>;
1497 qcom,ipc-1 = <&apcs 8 13>;
1498 qcom,ipc-3 = <&apcs 8 19>;
1503 #qcom,smem-state-cells = <1>;
1506 hexagon_smsm: hexagon@1 {
1508 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1510 interrupt-controller;
1511 #interrupt-cells = <2>;
1514 wcnss_smsm: wcnss@6 {
1516 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1518 interrupt-controller;
1519 #interrupt-cells = <2>;
1524 #include "msm8916-pins.dtsi"