arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17 #include <dt-bindings/clock/qcom,rpmcc.h>
  18 #include <dt-bindings/thermal/thermal.h>
  19
  20 / {
  21         interrupt-parent = <&intc>;
  22
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         aliases {
  27                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  28                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  29         };
  30
  31         chosen { };
  32
  33         memory {
  34                 device_type = "memory";
  35                 /* We expect the bootloader to fill in the reg */
  36                 reg = <0 0 0 0>;
  37         };
  38
  39         reserved-memory {
  40                 #address-cells = <2>;
  41                 #size-cells = <2>;
  42                 ranges;
  43
  44                 tz-apps@86000000 {
  45                         reg = <0x0 0x86000000 0x0 0x300000>;
  46                         no-map;
  47                 };
  48
  49                 smem_mem: smem_region@86300000 {
  50                         reg = <0x0 0x86300000 0x0 0x100000>;
  51                         no-map;
  52                 };
  53
  54                 hypervisor@86400000 {
  55                         reg = <0x0 0x86400000 0x0 0x100000>;
  56                         no-map;
  57                 };
  58
  59                 tz@86500000 {
  60                         reg = <0x0 0x86500000 0x0 0x180000>;
  61                         no-map;
  62                 };
  63
  64                 reserved@8668000 {
  65                         reg = <0x0 0x86680000 0x0 0x80000>;
  66                         no-map;
  67                 };
  68
  69                 rmtfs@86700000 {
  70                         compatible = "qcom,rmtfs-mem";
  71                         reg = <0x0 0x86700000 0x0 0xe0000>;
  72                         no-map;
  73
  74                         qcom,client-id = <1>;
  75                 };
  76
  77                 rfsa@867e00000 {
  78                         reg = <0x0 0x867e0000 0x0 0x20000>;
  79                         no-map;
  80                 };
  81
  82                 mpss_mem: mpss@86800000 {
  83                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  84                         no-map;
  85                 };
  86
  87                 wcnss_mem: wcnss@89300000 {
  88                         reg = <0x0 0x89300000 0x0 0x600000>;
  89                         no-map;
  90                 };
  91
  92                 venus_mem: venus@89900000 {
  93                         reg = <0x0 0x89900000 0x0 0x600000>;
  94                         no-map;
  95                 };
  96
  97                 mba_mem: mba@8ea00000 {
  98                         no-map;
  99                         reg = <0 0x8ea00000 0 0x100000>;
 100                 };
 101         };
 102
 103         cpus {
 104                 #address-cells = <1>;
 105                 #size-cells = <0>;
 106
 107                 CPU0: cpu@0 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a53", "arm,armv8";
 110                         reg = <0x0>;
 111                         next-level-cache = <&L2_0>;
 112                         enable-method = "psci";
 113                         cpu-idle-states = <&CPU_SPC>;
 114                         clocks = <&apcs 0>;
 115                         operating-points-v2 = <&cpu_opp_table>;
 116                         #cooling-cells = <2>;
 117                 };
 118
 119                 CPU1: cpu@1 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a53", "arm,armv8";
 122                         reg = <0x1>;
 123                         next-level-cache = <&L2_0>;
 124                         enable-method = "psci";
 125                         cpu-idle-states = <&CPU_SPC>;
 126                         clocks = <&apcs 0>;
 127                         operating-points-v2 = <&cpu_opp_table>;
 128                         #cooling-cells = <2>;
 129                 };
 130
 131                 CPU2: cpu@2 {
 132                         device_type = "cpu";
 133                         compatible = "arm,cortex-a53", "arm,armv8";
 134                         reg = <0x2>;
 135                         next-level-cache = <&L2_0>;
 136                         enable-method = "psci";
 137                         cpu-idle-states = <&CPU_SPC>;
 138                         clocks = <&apcs 0>;
 139                         operating-points-v2 = <&cpu_opp_table>;
 140                         #cooling-cells = <2>;
 141                 };
 142
 143                 CPU3: cpu@3 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a53", "arm,armv8";
 146                         reg = <0x3>;
 147                         next-level-cache = <&L2_0>;
 148                         enable-method = "psci";
 149                         cpu-idle-states = <&CPU_SPC>;
 150                         clocks = <&apcs 0>;
 151                         operating-points-v2 = <&cpu_opp_table>;
 152                         #cooling-cells = <2>;
 153                 };
 154
 155                 L2_0: l2-cache {
 156                       compatible = "cache";
 157                       cache-level = <2>;
 158                 };
 159
 160                 idle-states {
 161                         CPU_SPC: spc {
 162                                 compatible = "arm,idle-state";
 163                                 arm,psci-suspend-param = <0x40000002>;
 164                                 entry-latency-us = <130>;
 165                                 exit-latency-us = <150>;
 166                                 min-residency-us = <2000>;
 167                                 local-timer-stop;
 168                         };
 169                 };
 170         };
 171
 172         psci {
 173                 compatible = "arm,psci-1.0";
 174                 method = "smc";
 175         };
 176
 177         pmu {
 178                 compatible = "arm,cortex-a53-pmu";
 179                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
 180         };
 181
 182         thermal-zones {
 183                 cpu-thermal0 {
 184                         polling-delay-passive = <250>;
 185                         polling-delay = <1000>;
 186
 187                         thermal-sensors = <&tsens 4>;
 188
 189                         trips {
 190                                 cpu_alert0: trip0 {
 191                                         temperature = <75000>;
 192                                         hysteresis = <2000>;
 193                                         type = "passive";
 194                                 };
 195                                 cpu_crit0: trip1 {
 196                                         temperature = <110000>;
 197                                         hysteresis = <2000>;
 198                                         type = "critical";
 199                                 };
 200                         };
 201
 202                         cooling-maps {
 203                                 map0 {
 204                                         trip = <&cpu_alert0>;
 205                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 206                                 };
 207                         };
 208                 };
 209
 210                 cpu-thermal1 {
 211                         polling-delay-passive = <250>;
 212                         polling-delay = <1000>;
 213
 214                         thermal-sensors = <&tsens 3>;
 215
 216                         trips {
 217                                 cpu_alert1: trip0 {
 218                                         temperature = <75000>;
 219                                         hysteresis = <2000>;
 220                                         type = "passive";
 221                                 };
 222                                 cpu_crit1: trip1 {
 223                                         temperature = <110000>;
 224                                         hysteresis = <2000>;
 225                                         type = "critical";
 226                                 };
 227                         };
 228
 229                         cooling-maps {
 230                                 map0 {
 231                                         trip = <&cpu_alert1>;
 232                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 233                                 };
 234                         };
 235                 };
 236
 237         };
 238
 239         cpu_opp_table: cpu_opp_table {
 240                 compatible = "operating-points-v2";
 241                 opp-shared;
 242
 243                 opp-200000000 {
 244                         opp-hz = /bits/ 64 <200000000>;
 245                 };
 246                 opp-400000000 {
 247                         opp-hz = /bits/ 64 <400000000>;
 248                 };
 249                 opp-800000000 {
 250                         opp-hz = /bits/ 64 <800000000>;
 251                 };
 252                 opp-998400000 {
 253                         opp-hz = /bits/ 64 <998400000>;
 254                 };
 255         };
 256
 257         gpu_opp_table: opp_table {
 258                 compatible = "operating-points-v2";
 259
 260                 opp-400000000 {
 261                         opp-hz = /bits/ 64 <400000000>;
 262                 };
 263                 opp-19200000 {
 264                         opp-hz = /bits/ 64 <19200000>;
 265                 };
 266         };
 267
 268         timer {
 269                 compatible = "arm,armv8-timer";
 270                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 271                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 272                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 273                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 274         };
 275
 276         clocks {
 277                 xo_board: xo_board {
 278                         compatible = "fixed-clock";
 279                         #clock-cells = <0>;
 280                         clock-frequency = <19200000>;
 281                 };
 282
 283                 sleep_clk: sleep_clk {
 284                         compatible = "fixed-clock";
 285                         #clock-cells = <0>;
 286                         clock-frequency = <32768>;
 287                 };
 288         };
 289
 290         smem {
 291                 compatible = "qcom,smem";
 292
 293                 memory-region = <&smem_mem>;
 294                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 295
 296                 hwlocks = <&tcsr_mutex 3>;
 297         };
 298
 299         firmware {
 300                 scm: scm {
 301                         compatible = "qcom,scm";
 302                         clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 303                         clock-names = "core", "bus", "iface";
 304                         #reset-cells = <1>;
 305
 306                         qcom,dload-mode = <&tcsr 0x6100>;
 307                 };
 308         };
 309
 310         soc: soc {
 311                 #address-cells = <1>;
 312                 #size-cells = <1>;
 313                 ranges = <0 0 0 0xffffffff>;
 314                 compatible = "simple-bus";
 315
 316                 restart@4ab000 {
 317                         compatible = "qcom,pshold";
 318                         reg = <0x4ab000 0x4>;
 319                 };
 320
 321                 msmgpio: pinctrl@1000000 {
 322                         compatible = "qcom,msm8916-pinctrl";
 323                         reg = <0x1000000 0x300000>;
 324                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 325                         gpio-controller;
 326                         #gpio-cells = <2>;
 327                         interrupt-controller;
 328                         #interrupt-cells = <2>;
 329                 };
 330
 331                 gcc: clock-controller@1800000 {
 332                         compatible = "qcom,gcc-msm8916";
 333                         #clock-cells = <1>;
 334                         #reset-cells = <1>;
 335                         #power-domain-cells = <1>;
 336                         reg = <0x1800000 0x80000>;
 337                 };
 338
 339                 tcsr_mutex_regs: syscon@1905000 {
 340                         compatible = "syscon";
 341                         reg = <0x1905000 0x20000>;
 342                 };
 343
 344                 tcsr: syscon@1937000 {
 345                         compatible = "qcom,tcsr-msm8916", "syscon";
 346                         reg = <0x1937000 0x30000>;
 347                 };
 348
 349                 tcsr_mutex: hwlock {
 350                         compatible = "qcom,tcsr-mutex";
 351                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 352                         #hwlock-cells = <1>;
 353                 };
 354
 355                 rpm_msg_ram: memory@60000 {
 356                         compatible = "qcom,rpm-msg-ram";
 357                         reg = <0x60000 0x8000>;
 358                 };
 359
 360                 blsp1_uart1: serial@78af000 {
 361                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 362                         reg = <0x78af000 0x200>;
 363                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 364                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 365                         clock-names = "core", "iface";
 366                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 367                         dma-names = "rx", "tx";
 368                         status = "disabled";
 369                 };
 370
 371                 a53pll: clock@b016000 {
 372                         compatible = "qcom,msm8916-a53pll";
 373                         reg = <0xb016000 0x40>;
 374                         #clock-cells = <0>;
 375                 };
 376
 377                 apcs: mailbox@b011000 {
 378                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
 379                         reg = <0xb011000 0x1000>;
 380                         #mbox-cells = <1>;
 381                         clocks = <&a53pll>;
 382                         #clock-cells = <0>;
 383                 };
 384
 385                 blsp1_uart2: serial@78b0000 {
 386                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 387                         reg = <0x78b0000 0x200>;
 388                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 390                         clock-names = "core", "iface";
 391                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 392                         dma-names = "rx", "tx";
 393                         status = "disabled";
 394                 };
 395
 396                 blsp_dma: dma@7884000 {
 397                         compatible = "qcom,bam-v1.7.0";
 398                         reg = <0x07884000 0x23000>;
 399                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 401                         clock-names = "bam_clk";
 402                         #dma-cells = <1>;
 403                         qcom,ee = <0>;
 404                         status = "disabled";
 405                 };
 406
 407                 blsp_spi1: spi@78b5000 {
 408                         compatible = "qcom,spi-qup-v2.2.1";
 409                         reg = <0x078b5000 0x500>;
 410                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 411                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 412                                  <&gcc GCC_BLSP1_AHB_CLK>;
 413                         clock-names = "core", "iface";
 414                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 415                         dma-names = "rx", "tx";
 416                         pinctrl-names = "default", "sleep";
 417                         pinctrl-0 = <&spi1_default>;
 418                         pinctrl-1 = <&spi1_sleep>;
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         status = "disabled";
 422                 };
 423
 424                 blsp_spi2: spi@78b6000 {
 425                         compatible = "qcom,spi-qup-v2.2.1";
 426                         reg = <0x078b6000 0x500>;
 427                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 428                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 429                                  <&gcc GCC_BLSP1_AHB_CLK>;
 430                         clock-names = "core", "iface";
 431                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 432                         dma-names = "rx", "tx";
 433                         pinctrl-names = "default", "sleep";
 434                         pinctrl-0 = <&spi2_default>;
 435                         pinctrl-1 = <&spi2_sleep>;
 436                         #address-cells = <1>;
 437                         #size-cells = <0>;
 438                         status = "disabled";
 439                 };
 440
 441                 blsp_spi3: spi@78b7000 {
 442                         compatible = "qcom,spi-qup-v2.2.1";
 443                         reg = <0x078b7000 0x500>;
 444                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 445                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 446                                  <&gcc GCC_BLSP1_AHB_CLK>;
 447                         clock-names = "core", "iface";
 448                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 449                         dma-names = "rx", "tx";
 450                         pinctrl-names = "default", "sleep";
 451                         pinctrl-0 = <&spi3_default>;
 452                         pinctrl-1 = <&spi3_sleep>;
 453                         #address-cells = <1>;
 454                         #size-cells = <0>;
 455                         status = "disabled";
 456                 };
 457
 458                 blsp_spi4: spi@78b8000 {
 459                         compatible = "qcom,spi-qup-v2.2.1";
 460                         reg = <0x078b8000 0x500>;
 461                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 462                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 463                                  <&gcc GCC_BLSP1_AHB_CLK>;
 464                         clock-names = "core", "iface";
 465                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 466                         dma-names = "rx", "tx";
 467                         pinctrl-names = "default", "sleep";
 468                         pinctrl-0 = <&spi4_default>;
 469                         pinctrl-1 = <&spi4_sleep>;
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472                         status = "disabled";
 473                 };
 474
 475                 blsp_spi5: spi@78b9000 {
 476                         compatible = "qcom,spi-qup-v2.2.1";
 477                         reg = <0x078b9000 0x500>;
 478                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 480                                  <&gcc GCC_BLSP1_AHB_CLK>;
 481                         clock-names = "core", "iface";
 482                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 483                         dma-names = "rx", "tx";
 484                         pinctrl-names = "default", "sleep";
 485                         pinctrl-0 = <&spi5_default>;
 486                         pinctrl-1 = <&spi5_sleep>;
 487                         #address-cells = <1>;
 488                         #size-cells = <0>;
 489                         status = "disabled";
 490                 };
 491
 492                 blsp_spi6: spi@78ba000 {
 493                         compatible = "qcom,spi-qup-v2.2.1";
 494                         reg = <0x078ba000 0x500>;
 495                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 496                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 497                                  <&gcc GCC_BLSP1_AHB_CLK>;
 498                         clock-names = "core", "iface";
 499                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 500                         dma-names = "rx", "tx";
 501                         pinctrl-names = "default", "sleep";
 502                         pinctrl-0 = <&spi6_default>;
 503                         pinctrl-1 = <&spi6_sleep>;
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506                         status = "disabled";
 507                 };
 508
 509                 blsp_i2c2: i2c@78b6000 {
 510                         compatible = "qcom,i2c-qup-v2.2.1";
 511                         reg = <0x078b6000 0x500>;
 512                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 513                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 514                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 515                         clock-names = "iface", "core";
 516                         pinctrl-names = "default", "sleep";
 517                         pinctrl-0 = <&i2c2_default>;
 518                         pinctrl-1 = <&i2c2_sleep>;
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                         status = "disabled";
 522                 };
 523
 524                 blsp_i2c4: i2c@78b8000 {
 525                         compatible = "qcom,i2c-qup-v2.2.1";
 526                         reg = <0x078b8000 0x500>;
 527                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 529                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 530                         clock-names = "iface", "core";
 531                         pinctrl-names = "default", "sleep";
 532                         pinctrl-0 = <&i2c4_default>;
 533                         pinctrl-1 = <&i2c4_sleep>;
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         status = "disabled";
 537                 };
 538
 539                 blsp_i2c6: i2c@78ba000 {
 540                         compatible = "qcom,i2c-qup-v2.2.1";
 541                         reg = <0x078ba000 0x500>;
 542                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 544                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 545                         clock-names = "iface", "core";
 546                         pinctrl-names = "default", "sleep";
 547                         pinctrl-0 = <&i2c6_default>;
 548                         pinctrl-1 = <&i2c6_sleep>;
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                         status = "disabled";
 552                 };
 553
 554                 lpass: lpass@7708000 {
 555                         status = "disabled";
 556                         compatible = "qcom,lpass-cpu-apq8016";
 557                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 558                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 559                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 560                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 561                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 562                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 563                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 564
 565                         clock-names = "ahbix-clk",
 566                                         "pcnoc-mport-clk",
 567                                         "pcnoc-sway-clk",
 568                                         "mi2s-bit-clk0",
 569                                         "mi2s-bit-clk1",
 570                                         "mi2s-bit-clk2",
 571                                         "mi2s-bit-clk3";
 572                         #sound-dai-cells = <1>;
 573
 574                         interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
 575                         interrupt-names = "lpass-irq-lpaif";
 576                         reg = <0x07708000 0x10000>;
 577                         reg-names = "lpass-lpaif";
 578                 };
 579
 580                 lpass_codec: codec{
 581                         compatible = "qcom,msm8916-wcd-digital-codec";
 582                         reg = <0x0771c000 0x400>;
 583                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 584                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
 585                         clock-names = "ahbix-clk", "mclk";
 586                         #sound-dai-cells = <1>;
 587                 };
 588
 589                 sdhc_1: sdhci@7824000 {
 590                         compatible = "qcom,sdhci-msm-v4";
 591                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 592                         reg-names = "hc_mem", "core_mem";
 593
 594                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
 595                         interrupt-names = "hc_irq", "pwr_irq";
 596                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 597                                  <&gcc GCC_SDCC1_AHB_CLK>,
 598                                  <&xo_board>;
 599                         clock-names = "core", "iface", "xo";
 600                         mmc-ddr-1_8v;
 601                         bus-width = <8>;
 602                         non-removable;
 603                         status = "disabled";
 604                 };
 605
 606                 sdhc_2: sdhci@7864000 {
 607                         compatible = "qcom,sdhci-msm-v4";
 608                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 609                         reg-names = "hc_mem", "core_mem";
 610
 611                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
 612                         interrupt-names = "hc_irq", "pwr_irq";
 613                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 614                                  <&gcc GCC_SDCC2_AHB_CLK>,
 615                                  <&xo_board>;
 616                         clock-names = "core", "iface", "xo";
 617                         bus-width = <4>;
 618                         status = "disabled";
 619                 };
 620
 621                 otg: usb@78d9000 {
 622                         compatible = "qcom,ci-hdrc";
 623                         reg = <0x78d9000 0x200>,
 624                               <0x78d9200 0x200>;
 625                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 626                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 628                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 629                         clock-names = "iface", "core";
 630                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 631                         assigned-clock-rates = <80000000>;
 632                         resets = <&gcc GCC_USB_HS_BCR>;
 633                         reset-names = "core";
 634                         phy_type = "ulpi";
 635                         dr_mode = "otg";
 636                         ahb-burst-config = <0>;
 637                         phy-names = "usb-phy";
 638                         phys = <&usb_hs_phy>;
 639                         status = "disabled";
 640                         #reset-cells = <1>;
 641
 642                         ulpi {
 643                                 usb_hs_phy: phy {
 644                                         compatible = "qcom,usb-hs-phy-msm8916",
 645                                                      "qcom,usb-hs-phy";
 646                                         #phy-cells = <0>;
 647                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 648                                         clock-names = "ref", "sleep";
 649                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 650                                         reset-names = "phy", "por";
 651                                         qcom,init-seq = /bits/ 8 <0x0 0x44
 652                                                 0x1 0x6b 0x2 0x24 0x3 0x13>;
 653                                 };
 654                         };
 655                 };
 656
 657                 intc: interrupt-controller@b000000 {
 658                         compatible = "qcom,msm-qgic2";
 659                         interrupt-controller;
 660                         #interrupt-cells = <3>;
 661                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 662                 };
 663
 664                 timer@b020000 {
 665                         #address-cells = <1>;
 666                         #size-cells = <1>;
 667                         ranges;
 668                         compatible = "arm,armv7-timer-mem";
 669                         reg = <0xb020000 0x1000>;
 670                         clock-frequency = <19200000>;
 671
 672                         frame@b021000 {
 673                                 frame-number = <0>;
 674                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 675                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 676                                 reg = <0xb021000 0x1000>,
 677                                       <0xb022000 0x1000>;
 678                         };
 679
 680                         frame@b023000 {
 681                                 frame-number = <1>;
 682                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 683                                 reg = <0xb023000 0x1000>;
 684                                 status = "disabled";
 685                         };
 686
 687                         frame@b024000 {
 688                                 frame-number = <2>;
 689                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 690                                 reg = <0xb024000 0x1000>;
 691                                 status = "disabled";
 692                         };
 693
 694                         frame@b025000 {
 695                                 frame-number = <3>;
 696                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 697                                 reg = <0xb025000 0x1000>;
 698                                 status = "disabled";
 699                         };
 700
 701                         frame@b026000 {
 702                                 frame-number = <4>;
 703                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 704                                 reg = <0xb026000 0x1000>;
 705                                 status = "disabled";
 706                         };
 707
 708                         frame@b027000 {
 709                                 frame-number = <5>;
 710                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 711                                 reg = <0xb027000 0x1000>;
 712                                 status = "disabled";
 713                         };
 714
 715                         frame@b028000 {
 716                                 frame-number = <6>;
 717                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 718                                 reg = <0xb028000 0x1000>;
 719                                 status = "disabled";
 720                         };
 721                 };
 722
 723                 spmi_bus: spmi@200f000 {
 724                         compatible = "qcom,spmi-pmic-arb";
 725                         reg = <0x200f000 0x001000>,
 726                               <0x2400000 0x400000>,
 727                               <0x2c00000 0x400000>,
 728                               <0x3800000 0x200000>,
 729                               <0x200a000 0x002100>;
 730                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 731                         interrupt-names = "periph_irq";
 732                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 733                         qcom,ee = <0>;
 734                         qcom,channel = <0>;
 735                         #address-cells = <2>;
 736                         #size-cells = <0>;
 737                         interrupt-controller;
 738                         #interrupt-cells = <4>;
 739                 };
 740
 741                 rng@22000 {
 742                         compatible = "qcom,prng";
 743                         reg = <0x00022000 0x200>;
 744                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 745                         clock-names = "core";
 746                 };
 747
 748                 qfprom: qfprom@5c000 {
 749                         compatible = "qcom,qfprom";
 750                         reg = <0x5c000 0x1000>;
 751                         #address-cells = <1>;
 752                         #size-cells = <1>;
 753                         tsens_caldata: caldata@d0 {
 754                                 reg = <0xd0 0x8>;
 755                         };
 756                         tsens_calsel: calsel@ec {
 757                                 reg = <0xec 0x4>;
 758                         };
 759                 };
 760
 761                 tsens: thermal-sensor@4a8000 {
 762                         compatible = "qcom,msm8916-tsens";
 763                         reg = <0x4a8000 0x2000>;
 764                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 765                         nvmem-cell-names = "calib", "calib_sel";
 766                         #thermal-sensor-cells = <1>;
 767                 };
 768
 769                 apps_iommu: iommu@1ef0000 {
 770                         #address-cells = <1>;
 771                         #size-cells = <1>;
 772                         #iommu-cells = <1>;
 773                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 774                         ranges = <0 0x1e20000 0x40000>;
 775                         reg = <0x1ef0000 0x3000>;
 776                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 777                                  <&gcc GCC_APSS_TCU_CLK>;
 778                         clock-names = "iface", "bus";
 779                         qcom,iommu-secure-id = <17>;
 780
 781                         // mdp_0:
 782                         iommu-ctx@4000 {
 783                                 compatible = "qcom,msm-iommu-v1-ns";
 784                                 reg = <0x4000 0x1000>;
 785                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 786                         };
 787
 788                         // venus_ns:
 789                         iommu-ctx@5000 {
 790                                 compatible = "qcom,msm-iommu-v1-sec";
 791                                 reg = <0x5000 0x1000>;
 792                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 793                         };
 794                 };
 795
 796                 gpu_iommu: iommu@1f08000 {
 797                         #address-cells = <1>;
 798                         #size-cells = <1>;
 799                         #iommu-cells = <1>;
 800                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 801                         ranges = <0 0x1f08000 0x10000>;
 802                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 803                                  <&gcc GCC_GFX_TCU_CLK>;
 804                         clock-names = "iface", "bus";
 805                         qcom,iommu-secure-id = <18>;
 806
 807                         // gfx3d_user:
 808                         iommu-ctx@1000 {
 809                                 compatible = "qcom,msm-iommu-v1-ns";
 810                                 reg = <0x1000 0x1000>;
 811                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 812                         };
 813
 814                         // gfx3d_priv:
 815                         iommu-ctx@2000 {
 816                                 compatible = "qcom,msm-iommu-v1-ns";
 817                                 reg = <0x2000 0x1000>;
 818                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 819                         };
 820                 };
 821
 822                 gpu@1c00000 {
 823                         compatible = "qcom,adreno-306.0", "qcom,adreno";
 824                         reg = <0x01c00000 0x20000>;
 825                         reg-names = "kgsl_3d0_reg_memory";
 826                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 827                         interrupt-names = "kgsl_3d0_irq";
 828                         clock-names =
 829                             "core",
 830                             "iface",
 831                             "mem",
 832                             "mem_iface",
 833                             "alt_mem_iface",
 834                             "gfx3d";
 835                         clocks =
 836                             <&gcc GCC_OXILI_GFX3D_CLK>,
 837                             <&gcc GCC_OXILI_AHB_CLK>,
 838                             <&gcc GCC_OXILI_GMEM_CLK>,
 839                             <&gcc GCC_BIMC_GFX_CLK>,
 840                             <&gcc GCC_BIMC_GPU_CLK>,
 841                             <&gcc GFX3D_CLK_SRC>;
 842                         power-domains = <&gcc OXILI_GDSC>;
 843                         operating-points-v2 = <&gpu_opp_table>;
 844                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
 845                 };
 846
 847                 mdss: mdss@1a00000 {
 848                         compatible = "qcom,mdss";
 849                         reg = <0x1a00000 0x1000>,
 850                               <0x1ac8000 0x3000>;
 851                         reg-names = "mdss_phys", "vbif_phys";
 852
 853                         power-domains = <&gcc MDSS_GDSC>;
 854
 855                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 856                                  <&gcc GCC_MDSS_AXI_CLK>,
 857                                  <&gcc GCC_MDSS_VSYNC_CLK>;
 858                         clock-names = "iface",
 859                                       "bus",
 860                                       "vsync";
 861
 862                         interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 863
 864                         interrupt-controller;
 865                         #interrupt-cells = <1>;
 866
 867                         #address-cells = <1>;
 868                         #size-cells = <1>;
 869                         ranges;
 870
 871                         mdp: mdp@1a01000 {
 872                                 compatible = "qcom,mdp5";
 873                                 reg = <0x1a01000 0x89000>;
 874                                 reg-names = "mdp_phys";
 875
 876                                 interrupt-parent = <&mdss>;
 877                                 interrupts = <0 0>;
 878
 879                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 880                                          <&gcc GCC_MDSS_AXI_CLK>,
 881                                          <&gcc GCC_MDSS_MDP_CLK>,
 882                                          <&gcc GCC_MDSS_VSYNC_CLK>;
 883                                 clock-names = "iface",
 884                                               "bus",
 885                                               "core",
 886                                               "vsync";
 887
 888                                 iommus = <&apps_iommu 4>;
 889
 890                                 ports {
 891                                         #address-cells = <1>;
 892                                         #size-cells = <0>;
 893
 894                                         port@0 {
 895                                                 reg = <0>;
 896                                                 mdp5_intf1_out: endpoint {
 897                                                         remote-endpoint = <&dsi0_in>;
 898                                                 };
 899                                         };
 900                                 };
 901                         };
 902
 903                         dsi0: dsi@1a98000 {
 904                                 compatible = "qcom,mdss-dsi-ctrl";
 905                                 reg = <0x1a98000 0x25c>;
 906                                 reg-names = "dsi_ctrl";
 907
 908                                 interrupt-parent = <&mdss>;
 909                                 interrupts = <4 0>;
 910
 911                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
 912                                                   <&gcc PCLK0_CLK_SRC>;
 913                                 assigned-clock-parents = <&dsi_phy0 0>,
 914                                                          <&dsi_phy0 1>;
 915
 916                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 917                                          <&gcc GCC_MDSS_AHB_CLK>,
 918                                          <&gcc GCC_MDSS_AXI_CLK>,
 919                                          <&gcc GCC_MDSS_BYTE0_CLK>,
 920                                          <&gcc GCC_MDSS_PCLK0_CLK>,
 921                                          <&gcc GCC_MDSS_ESC0_CLK>;
 922                                 clock-names = "mdp_core",
 923                                               "iface",
 924                                               "bus",
 925                                               "byte",
 926                                               "pixel",
 927                                               "core";
 928                                 phys = <&dsi_phy0>;
 929                                 phy-names = "dsi-phy";
 930
 931                                 ports {
 932                                         #address-cells = <1>;
 933                                         #size-cells = <0>;
 934
 935                                         port@0 {
 936                                                 reg = <0>;
 937                                                 dsi0_in: endpoint {
 938                                                         remote-endpoint = <&mdp5_intf1_out>;
 939                                                 };
 940                                         };
 941
 942                                         port@1 {
 943                                                 reg = <1>;
 944                                                 dsi0_out: endpoint {
 945                                                 };
 946                                         };
 947                                 };
 948                         };
 949
 950                         dsi_phy0: dsi-phy@1a98300 {
 951                                 compatible = "qcom,dsi-phy-28nm-lp";
 952                                 reg = <0x1a98300 0xd4>,
 953                                       <0x1a98500 0x280>,
 954                                       <0x1a98780 0x30>;
 955                                 reg-names = "dsi_pll",
 956                                             "dsi_phy",
 957                                             "dsi_phy_regulator";
 958
 959                                 #clock-cells = <1>;
 960                                 #phy-cells = <0>;
 961
 962                                 clocks = <&gcc GCC_MDSS_AHB_CLK>;
 963                                 clock-names = "iface";
 964                         };
 965                 };
 966
 967
 968                 hexagon@4080000 {
 969                         compatible = "qcom,q6v5-pil";
 970                         reg = <0x04080000 0x100>,
 971                               <0x04020000 0x040>;
 972
 973                         reg-names = "qdsp6", "rmb";
 974
 975                         interrupts-extended = <&intc 0 24 1>,
 976                                               <&hexagon_smp2p_in 0 0>,
 977                                               <&hexagon_smp2p_in 1 0>,
 978                                               <&hexagon_smp2p_in 2 0>,
 979                                               <&hexagon_smp2p_in 3 0>;
 980                         interrupt-names = "wdog", "fatal", "ready",
 981                                           "handover", "stop-ack";
 982
 983                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 984                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
 985                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
 986                                  <&xo_board>;
 987                         clock-names = "iface", "bus", "mem", "xo";
 988
 989                         qcom,smem-states = <&hexagon_smp2p_out 0>;
 990                         qcom,smem-state-names = "stop";
 991
 992                         resets = <&scm 0>;
 993                         reset-names = "mss_restart";
 994
 995                         cx-supply = <&pm8916_s1>;
 996                         mx-supply = <&pm8916_l3>;
 997                         pll-supply = <&pm8916_l7>;
 998
 999                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1000
1001                         status = "disabled";
1002
1003                         mba {
1004                                 memory-region = <&mba_mem>;
1005                         };
1006
1007                         mpss {
1008                                 memory-region = <&mpss_mem>;
1009                         };
1010
1011                         smd-edge {
1012                                 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1013
1014                                 qcom,smd-edge = <0>;
1015                                 qcom,ipc = <&apcs 8 12>;
1016                                 qcom,remote-pid = <1>;
1017
1018                                 label = "hexagon";
1019                         };
1020                 };
1021
1022                 pronto: wcnss@a21b000 {
1023                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1024                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1025                         reg-names = "ccu", "dxe", "pmu";
1026
1027                         memory-region = <&wcnss_mem>;
1028
1029                         interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1030                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1031                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1032                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1033                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1034                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1035
1036                         vddmx-supply = <&pm8916_l3>;
1037                         vddpx-supply = <&pm8916_l7>;
1038
1039                         qcom,state = <&wcnss_smp2p_out 0>;
1040                         qcom,state-names = "stop";
1041
1042                         pinctrl-names = "default";
1043                         pinctrl-0 = <&wcnss_pin_a>;
1044
1045                         status = "disabled";
1046
1047                         iris {
1048                                 compatible = "qcom,wcn3620";
1049
1050                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1051                                 clock-names = "xo";
1052
1053                                 vddxo-supply = <&pm8916_l7>;
1054                                 vddrfa-supply = <&pm8916_s3>;
1055                                 vddpa-supply = <&pm8916_l9>;
1056                                 vdddig-supply = <&pm8916_l5>;
1057                         };
1058
1059                         smd-edge {
1060                                 interrupts = <0 142 1>;
1061
1062                                 qcom,ipc = <&apcs 8 17>;
1063                                 qcom,smd-edge = <6>;
1064                                 qcom,remote-pid = <4>;
1065
1066                                 label = "pronto";
1067
1068                                 wcnss {
1069                                         compatible = "qcom,wcnss";
1070                                         qcom,smd-channels = "WCNSS_CTRL";
1071
1072                                         qcom,mmio = <&pronto>;
1073
1074                                         bt {
1075                                                 compatible = "qcom,wcnss-bt";
1076                                         };
1077
1078                                         wifi {
1079                                                 compatible = "qcom,wcnss-wlan";
1080
1081                                                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1082                                                              <0 146 IRQ_TYPE_LEVEL_HIGH>;
1083                                                 interrupt-names = "tx", "rx";
1084
1085                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1086                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1087                                         };
1088                                 };
1089                         };
1090                 };
1091
1092                 tpiu@820000 {
1093                         compatible = "arm,coresight-tpiu", "arm,primecell";
1094                         reg = <0x820000 0x1000>;
1095
1096                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1097                         clock-names = "apb_pclk", "atclk";
1098
1099                         in-ports {
1100                                 port {
1101                                         tpiu_in: endpoint {
1102                                                 remote-endpoint = <&replicator_out1>;
1103                                         };
1104                                 };
1105                         };
1106                 };
1107
1108                 funnel@821000 {
1109                         compatible = "arm,coresight-funnel", "arm,primecell";
1110                         reg = <0x821000 0x1000>;
1111
1112                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1113                         clock-names = "apb_pclk", "atclk";
1114
1115                         in-ports {
1116                                 #address-cells = <1>;
1117                                 #size-cells = <0>;
1118
1119                                 /*
1120                                  * Not described input ports:
1121                                  * 0 - connected to Resource and Power Manger CPU ETM
1122                                  * 1 - not-connected
1123                                  * 2 - connected to Modem CPU ETM
1124                                  * 3 - not-connected
1125                                  * 5 - not-connected
1126                                  * 6 - connected trought funnel to Wireless CPU ETM
1127                                  * 7 - connected to STM component
1128                                  */
1129
1130                                 port@4 {
1131                                         reg = <4>;
1132                                         funnel0_in4: endpoint {
1133                                                 remote-endpoint = <&funnel1_out>;
1134                                         };
1135                                 };
1136                         };
1137
1138                         out-ports {
1139                                 port {
1140                                         funnel0_out: endpoint {
1141                                                 remote-endpoint = <&etf_in>;
1142                                         };
1143                                 };
1144                         };
1145                 };
1146
1147                 replicator@824000 {
1148                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1149                         reg = <0x824000 0x1000>;
1150
1151                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1152                         clock-names = "apb_pclk", "atclk";
1153
1154                         out-ports {
1155                                 #address-cells = <1>;
1156                                 #size-cells = <0>;
1157
1158                                 port@0 {
1159                                         reg = <0>;
1160                                         replicator_out0: endpoint {
1161                                                 remote-endpoint = <&etr_in>;
1162                                         };
1163                                 };
1164                                 port@1 {
1165                                         reg = <1>;
1166                                         replicator_out1: endpoint {
1167                                                 remote-endpoint = <&tpiu_in>;
1168                                         };
1169                                 };
1170                         };
1171
1172                         in-ports {
1173                                 port {
1174                                         replicator_in: endpoint {
1175                                                 remote-endpoint = <&etf_out>;
1176                                         };
1177                                 };
1178                         };
1179                 };
1180
1181                 etf@825000 {
1182                         compatible = "arm,coresight-tmc", "arm,primecell";
1183                         reg = <0x825000 0x1000>;
1184
1185                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1186                         clock-names = "apb_pclk", "atclk";
1187
1188                         in-ports {
1189                                 port {
1190                                         etf_in: endpoint {
1191                                                 remote-endpoint = <&funnel0_out>;
1192                                         };
1193                                 };
1194                         };
1195
1196                         out-ports {
1197                                 port {
1198                                         etf_out: endpoint {
1199                                                 remote-endpoint = <&replicator_in>;
1200                                         };
1201                                 };
1202                         };
1203                 };
1204
1205                 etr@826000 {
1206                         compatible = "arm,coresight-tmc", "arm,primecell";
1207                         reg = <0x826000 0x1000>;
1208
1209                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1210                         clock-names = "apb_pclk", "atclk";
1211
1212                         in-ports {
1213                                 port {
1214                                         etr_in: endpoint {
1215                                                 remote-endpoint = <&replicator_out0>;
1216                                         };
1217                                 };
1218                         };
1219                 };
1220
1221                 funnel@841000 { /* APSS funnel only 4 inputs are used */
1222                         compatible = "arm,coresight-funnel", "arm,primecell";
1223                         reg = <0x841000 0x1000>;
1224
1225                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1226                         clock-names = "apb_pclk", "atclk";
1227
1228                         in-ports {
1229                                 #address-cells = <1>;
1230                                 #size-cells = <0>;
1231
1232                                 port@0 {
1233                                         reg = <0>;
1234                                         funnel1_in0: endpoint {
1235                                                 remote-endpoint = <&etm0_out>;
1236                                         };
1237                                 };
1238                                 port@1 {
1239                                         reg = <1>;
1240                                         funnel1_in1: endpoint {
1241                                                 remote-endpoint = <&etm1_out>;
1242                                         };
1243                                 };
1244                                 port@2 {
1245                                         reg = <2>;
1246                                         funnel1_in2: endpoint {
1247                                                 remote-endpoint = <&etm2_out>;
1248                                         };
1249                                 };
1250                                 port@3 {
1251                                         reg = <3>;
1252                                         funnel1_in3: endpoint {
1253                                                 remote-endpoint = <&etm3_out>;
1254                                         };
1255                                 };
1256                         };
1257
1258                         out-ports {
1259                                 port {
1260                                         funnel1_out: endpoint {
1261                                                 remote-endpoint = <&funnel0_in4>;
1262                                         };
1263                                 };
1264                         };
1265                 };
1266
1267                 debug@850000 {
1268                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1269                         reg = <0x850000 0x1000>;
1270                         clocks = <&rpmcc RPM_QDSS_CLK>;
1271                         clock-names = "apb_pclk";
1272                         cpu = <&CPU0>;
1273                 };
1274
1275                 debug@852000 {
1276                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1277                         reg = <0x852000 0x1000>;
1278                         clocks = <&rpmcc RPM_QDSS_CLK>;
1279                         clock-names = "apb_pclk";
1280                         cpu = <&CPU1>;
1281                 };
1282
1283                 debug@854000 {
1284                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1285                         reg = <0x854000 0x1000>;
1286                         clocks = <&rpmcc RPM_QDSS_CLK>;
1287                         clock-names = "apb_pclk";
1288                         cpu = <&CPU2>;
1289                 };
1290
1291                 debug@856000 {
1292                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1293                         reg = <0x856000 0x1000>;
1294                         clocks = <&rpmcc RPM_QDSS_CLK>;
1295                         clock-names = "apb_pclk";
1296                         cpu = <&CPU3>;
1297                 };
1298
1299                 etm@85c000 {
1300                         compatible = "arm,coresight-etm4x", "arm,primecell";
1301                         reg = <0x85c000 0x1000>;
1302
1303                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1304                         clock-names = "apb_pclk", "atclk";
1305
1306                         cpu = <&CPU0>;
1307
1308                         out-ports {
1309                                 port {
1310                                         etm0_out: endpoint {
1311                                                 remote-endpoint = <&funnel1_in0>;
1312                                         };
1313                                 };
1314                         };
1315                 };
1316
1317                 etm@85d000 {
1318                         compatible = "arm,coresight-etm4x", "arm,primecell";
1319                         reg = <0x85d000 0x1000>;
1320
1321                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1322                         clock-names = "apb_pclk", "atclk";
1323
1324                         cpu = <&CPU1>;
1325
1326                         out-ports {
1327                                 port {
1328                                         etm1_out: endpoint {
1329                                                 remote-endpoint = <&funnel1_in1>;
1330                                         };
1331                                 };
1332                         };
1333                 };
1334
1335                 etm@85e000 {
1336                         compatible = "arm,coresight-etm4x", "arm,primecell";
1337                         reg = <0x85e000 0x1000>;
1338
1339                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1340                         clock-names = "apb_pclk", "atclk";
1341
1342                         cpu = <&CPU2>;
1343
1344                         out-ports {
1345                                 port {
1346                                         etm2_out: endpoint {
1347                                                 remote-endpoint = <&funnel1_in2>;
1348                                         };
1349                                 };
1350                         };
1351                 };
1352
1353                 etm@85f000 {
1354                         compatible = "arm,coresight-etm4x", "arm,primecell";
1355                         reg = <0x85f000 0x1000>;
1356
1357                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1358                         clock-names = "apb_pclk", "atclk";
1359
1360                         cpu = <&CPU3>;
1361
1362                         out-ports {
1363                                 port {
1364                                         etm3_out: endpoint {
1365                                                 remote-endpoint = <&funnel1_in3>;
1366                                         };
1367                                 };
1368                         };
1369                 };
1370
1371                 venus: video-codec@1d00000 {
1372                         compatible = "qcom,msm8916-venus";
1373                         reg = <0x01d00000 0xff000>;
1374                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1375                         power-domains = <&gcc VENUS_GDSC>;
1376                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1377                                  <&gcc GCC_VENUS0_AHB_CLK>,
1378                                  <&gcc GCC_VENUS0_AXI_CLK>;
1379                         clock-names = "core", "iface", "bus";
1380                         iommus = <&apps_iommu 5>;
1381                         memory-region = <&venus_mem>;
1382                         status = "okay";
1383
1384                         video-decoder {
1385                                 compatible = "venus-decoder";
1386                         };
1387
1388                         video-encoder {
1389                                 compatible = "venus-encoder";
1390                         };
1391                 };
1392         };
1393
1394         smd {
1395                 compatible = "qcom,smd";
1396
1397                 rpm {
1398                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1399                         qcom,ipc = <&apcs 8 0>;
1400                         qcom,smd-edge = <15>;
1401
1402                         rpm_requests {
1403                                 compatible = "qcom,rpm-msm8916";
1404                                 qcom,smd-channels = "rpm_requests";
1405
1406                                 rpmcc: qcom,rpmcc {
1407                                         compatible = "qcom,rpmcc-msm8916";
1408                                         #clock-cells = <1>;
1409                                 };
1410
1411                                 smd_rpm_regulators: pm8916-regulators {
1412                                         compatible = "qcom,rpm-pm8916-regulators";
1413
1414                                         pm8916_s1: s1 {};
1415                                         pm8916_s3: s3 {};
1416                                         pm8916_s4: s4 {};
1417
1418                                         pm8916_l1: l1 {};
1419                                         pm8916_l2: l2 {};
1420                                         pm8916_l3: l3 {};
1421                                         pm8916_l4: l4 {};
1422                                         pm8916_l5: l5 {};
1423                                         pm8916_l6: l6 {};
1424                                         pm8916_l7: l7 {};
1425                                         pm8916_l8: l8 {};
1426                                         pm8916_l9: l9 {};
1427                                         pm8916_l10: l10 {};
1428                                         pm8916_l11: l11 {};
1429                                         pm8916_l12: l12 {};
1430                                         pm8916_l13: l13 {};
1431                                         pm8916_l14: l14 {};
1432                                         pm8916_l15: l15 {};
1433                                         pm8916_l16: l16 {};
1434                                         pm8916_l17: l17 {};
1435                                         pm8916_l18: l18 {};
1436                                 };
1437                         };
1438                 };
1439         };
1440
1441         hexagon-smp2p {
1442                 compatible = "qcom,smp2p";
1443                 qcom,smem = <435>, <428>;
1444
1445                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1446
1447                 qcom,ipc = <&apcs 8 14>;
1448
1449                 qcom,local-pid = <0>;
1450                 qcom,remote-pid = <1>;
1451
1452                 hexagon_smp2p_out: master-kernel {
1453                         qcom,entry-name = "master-kernel";
1454
1455                         #qcom,smem-state-cells = <1>;
1456                 };
1457
1458                 hexagon_smp2p_in: slave-kernel {
1459                         qcom,entry-name = "slave-kernel";
1460
1461                         interrupt-controller;
1462                         #interrupt-cells = <2>;
1463                 };
1464         };
1465
1466         wcnss-smp2p {
1467                 compatible = "qcom,smp2p";
1468                 qcom,smem = <451>, <431>;
1469
1470                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1471
1472                 qcom,ipc = <&apcs 8 18>;
1473
1474                 qcom,local-pid = <0>;
1475                 qcom,remote-pid = <4>;
1476
1477                 wcnss_smp2p_out: master-kernel {
1478                         qcom,entry-name = "master-kernel";
1479
1480                         #qcom,smem-state-cells = <1>;
1481                 };
1482
1483                 wcnss_smp2p_in: slave-kernel {
1484                         qcom,entry-name = "slave-kernel";
1485
1486                         interrupt-controller;
1487                         #interrupt-cells = <2>;
1488                 };
1489         };
1490
1491         smsm {
1492                 compatible = "qcom,smsm";
1493
1494                 #address-cells = <1>;
1495                 #size-cells = <0>;
1496
1497                 qcom,ipc-1 = <&apcs 8 13>;
1498                 qcom,ipc-3 = <&apcs 8 19>;
1499
1500                 apps_smsm: apps@0 {
1501                         reg = <0>;
1502
1503                         #qcom,smem-state-cells = <1>;
1504                 };
1505
1506                 hexagon_smsm: hexagon@1 {
1507                         reg = <1>;
1508                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1509
1510                         interrupt-controller;
1511                         #interrupt-cells = <2>;
1512                 };
1513
1514                 wcnss_smsm: wcnss@6 {
1515                         reg = <6>;
1516                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1517
1518                         interrupt-controller;
1519                         #interrupt-cells = <2>;
1520                 };
1521         };
1522 };
1523
1524 #include "msm8916-pins.dtsi"