arch/arm64/boot/dts/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/reset/tegra194-reset.h>
   7 #include <dt-bindings/power/tegra194-powergate.h>
   8 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
   9
  10 / {
  11         compatible = "nvidia,tegra194";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         /* control backbone */
  17         cbb {
  18                 compatible = "simple-bus";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x0 0x0 0x0 0x40000000>;
  22
  23                 gpio: gpio@2200000 {
  24                         compatible = "nvidia,tegra194-gpio";
  25                         reg-names = "security", "gpio";
  26                         reg = <0x2200000 0x10000>,
  27                               <0x2210000 0x10000>;
  28                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  29                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  30                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  31                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  32                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  33                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
  34                         #interrupt-cells = <2>;
  35                         interrupt-controller;
  36                         #gpio-cells = <2>;
  37                         gpio-controller;
  38                 };
  39
  40                 ethernet@2490000 {
  41                         compatible = "nvidia,tegra186-eqos",
  42                                      "snps,dwc-qos-ethernet-4.10";
  43                         reg = <0x02490000 0x10000>;
  44                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  45                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
  46                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
  47                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
  48                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
  49                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
  50                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  51                         resets = <&bpmp TEGRA194_RESET_EQOS>;
  52                         reset-names = "eqos";
  53                         status = "disabled";
  54
  55                         snps,write-requests = <1>;
  56                         snps,read-requests = <3>;
  57                         snps,burst-map = <0x7>;
  58                         snps,txpbl = <16>;
  59                         snps,rxpbl = <8>;
  60                 };
  61
  62                 uarta: serial@3100000 {
  63                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
  64                         reg = <0x03100000 0x40>;
  65                         reg-shift = <2>;
  66                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  67                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
  68                         clock-names = "serial";
  69                         resets = <&bpmp TEGRA194_RESET_UARTA>;
  70                         reset-names = "serial";
  71                         status = "disabled";
  72                 };
  73
  74                 uartb: serial@3110000 {
  75                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
  76                         reg = <0x03110000 0x40>;
  77                         reg-shift = <2>;
  78                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  79                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
  80                         clock-names = "serial";
  81                         resets = <&bpmp TEGRA194_RESET_UARTB>;
  82                         reset-names = "serial";
  83                         status = "disabled";
  84                 };
  85
  86                 uartd: serial@3130000 {
  87                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
  88                         reg = <0x03130000 0x40>;
  89                         reg-shift = <2>;
  90                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  91                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
  92                         clock-names = "serial";
  93                         resets = <&bpmp TEGRA194_RESET_UARTD>;
  94                         reset-names = "serial";
  95                         status = "disabled";
  96                 };
  97
  98                 uarte: serial@3140000 {
  99                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 100                         reg = <0x03140000 0x40>;
 101                         reg-shift = <2>;
 102                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 103                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 104                         clock-names = "serial";
 105                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 106                         reset-names = "serial";
 107                         status = "disabled";
 108                 };
 109
 110                 uartf: serial@3150000 {
 111                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 112                         reg = <0x03150000 0x40>;
 113                         reg-shift = <2>;
 114                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 115                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 116                         clock-names = "serial";
 117                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 118                         reset-names = "serial";
 119                         status = "disabled";
 120                 };
 121
 122                 gen1_i2c: i2c@3160000 {
 123                         compatible = "nvidia,tegra194-i2c";
 124                         reg = <0x03160000 0x10000>;
 125                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 129                         clock-names = "div-clk";
 130                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 131                         reset-names = "i2c";
 132                         status = "disabled";
 133                 };
 134
 135                 uarth: serial@3170000 {
 136                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 137                         reg = <0x03170000 0x40>;
 138                         reg-shift = <2>;
 139                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 140                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 141                         clock-names = "serial";
 142                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 143                         reset-names = "serial";
 144                         status = "disabled";
 145                 };
 146
 147                 cam_i2c: i2c@3180000 {
 148                         compatible = "nvidia,tegra194-i2c";
 149                         reg = <0x03180000 0x10000>;
 150                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 154                         clock-names = "div-clk";
 155                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 156                         reset-names = "i2c";
 157                         status = "disabled";
 158                 };
 159
 160                 /* shares pads with dpaux1 */
 161                 dp_aux_ch1_i2c: i2c@3190000 {
 162                         compatible = "nvidia,tegra194-i2c";
 163                         reg = <0x03190000 0x10000>;
 164                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 168                         clock-names = "div-clk";
 169                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 170                         reset-names = "i2c";
 171                         status = "disabled";
 172                 };
 173
 174                 /* shares pads with dpaux0 */
 175                 dp_aux_ch0_i2c: i2c@31b0000 {
 176                         compatible = "nvidia,tegra194-i2c";
 177                         reg = <0x031b0000 0x10000>;
 178                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 182                         clock-names = "div-clk";
 183                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 184                         reset-names = "i2c";
 185                         status = "disabled";
 186                 };
 187
 188                 gen7_i2c: i2c@31c0000 {
 189                         compatible = "nvidia,tegra194-i2c";
 190                         reg = <0x031c0000 0x10000>;
 191                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 195                         clock-names = "div-clk";
 196                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 197                         reset-names = "i2c";
 198                         status = "disabled";
 199                 };
 200
 201                 gen9_i2c: i2c@31e0000 {
 202                         compatible = "nvidia,tegra194-i2c";
 203                         reg = <0x031e0000 0x10000>;
 204                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 208                         clock-names = "div-clk";
 209                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 210                         reset-names = "i2c";
 211                         status = "disabled";
 212                 };
 213
 214                 pwm1: pwm@3280000 {
 215                         compatible = "nvidia,tegra194-pwm",
 216                                      "nvidia,tegra186-pwm";
 217                         reg = <0x3280000 0x10000>;
 218                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 219                         clock-names = "pwm";
 220                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 221                         reset-names = "pwm";
 222                         status = "disabled";
 223                         #pwm-cells = <2>;
 224                 };
 225
 226                 pwm2: pwm@3290000 {
 227                         compatible = "nvidia,tegra194-pwm",
 228                                      "nvidia,tegra186-pwm";
 229                         reg = <0x3290000 0x10000>;
 230                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 231                         clock-names = "pwm";
 232                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 233                         reset-names = "pwm";
 234                         status = "disabled";
 235                         #pwm-cells = <2>;
 236                 };
 237
 238                 pwm3: pwm@32a0000 {
 239                         compatible = "nvidia,tegra194-pwm",
 240                                      "nvidia,tegra186-pwm";
 241                         reg = <0x32a0000 0x10000>;
 242                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 243                         clock-names = "pwm";
 244                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 245                         reset-names = "pwm";
 246                         status = "disabled";
 247                         #pwm-cells = <2>;
 248                 };
 249
 250                 pwm5: pwm@32c0000 {
 251                         compatible = "nvidia,tegra194-pwm",
 252                                      "nvidia,tegra186-pwm";
 253                         reg = <0x32c0000 0x10000>;
 254                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 255                         clock-names = "pwm";
 256                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 257                         reset-names = "pwm";
 258                         status = "disabled";
 259                         #pwm-cells = <2>;
 260                 };
 261
 262                 pwm6: pwm@32d0000 {
 263                         compatible = "nvidia,tegra194-pwm",
 264                                      "nvidia,tegra186-pwm";
 265                         reg = <0x32d0000 0x10000>;
 266                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 267                         clock-names = "pwm";
 268                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 269                         reset-names = "pwm";
 270                         status = "disabled";
 271                         #pwm-cells = <2>;
 272                 };
 273
 274                 pwm7: pwm@32e0000 {
 275                         compatible = "nvidia,tegra194-pwm",
 276                                      "nvidia,tegra186-pwm";
 277                         reg = <0x32e0000 0x10000>;
 278                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 279                         clock-names = "pwm";
 280                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 281                         reset-names = "pwm";
 282                         status = "disabled";
 283                         #pwm-cells = <2>;
 284                 };
 285
 286                 pwm8: pwm@32f0000 {
 287                         compatible = "nvidia,tegra194-pwm",
 288                                      "nvidia,tegra186-pwm";
 289                         reg = <0x32f0000 0x10000>;
 290                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
 291                         clock-names = "pwm";
 292                         resets = <&bpmp TEGRA194_RESET_PWM8>;
 293                         reset-names = "pwm";
 294                         status = "disabled";
 295                         #pwm-cells = <2>;
 296                 };
 297
 298                 sdmmc1: sdhci@3400000 {
 299                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 300                         reg = <0x03400000 0x10000>;
 301                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
 303                         clock-names = "sdhci";
 304                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 305                         reset-names = "sdhci";
 306                         nvidia,pad-autocal-pull-up-offset-3v3-timeout =
 307                                                                         <0x07>;
 308                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 309                                                                         <0x07>;
 310                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 311                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 312                                                                         <0x07>;
 313                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 314                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 315                         nvidia,default-tap = <0x9>;
 316                         nvidia,default-trim = <0x5>;
 317                         status = "disabled";
 318                 };
 319
 320                 sdmmc3: sdhci@3440000 {
 321                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 322                         reg = <0x03440000 0x10000>;
 323                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
 325                         clock-names = "sdhci";
 326                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 327                         reset-names = "sdhci";
 328                         nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 329                         nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 330                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 331                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 332                                                                         <0x07>;
 333                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 334                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 335                                                                         <0x07>;
 336                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 337                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 338                         nvidia,default-tap = <0x9>;
 339                         nvidia,default-trim = <0x5>;
 340                         status = "disabled";
 341                 };
 342
 343                 sdmmc4: sdhci@3460000 {
 344                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 345                         reg = <0x03460000 0x10000>;
 346                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
 348                         clock-names = "sdhci";
 349                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 350                                           <&bpmp TEGRA194_CLK_PLLC4>;
 351                         assigned-clock-parents =
 352                                           <&bpmp TEGRA194_CLK_PLLC4>;
 353                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 354                         reset-names = "sdhci";
 355                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 356                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 357                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 358                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 359                                                                         <0x0a>;
 360                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 361                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 362                                                                         <0x0a>;
 363                         nvidia,default-tap = <0x8>;
 364                         nvidia,default-trim = <0x14>;
 365                         nvidia,dqs-trim = <40>;
 366                         supports-cqe;
 367                         status = "disabled";
 368                 };
 369
 370                 hda@3510000 {
 371                         compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
 372                         reg = <0x3510000 0x10000>;
 373                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&bpmp TEGRA194_CLK_HDA>,
 375                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
 376                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
 377                         clock-names = "hda", "hda2codec_2x", "hda2hdmi";
 378                         resets = <&bpmp TEGRA194_RESET_HDA>,
 379                                  <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
 380                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
 381                         reset-names = "hda", "hda2codec_2x", "hda2hdmi";
 382                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 383                         status = "disabled";
 384                 };
 385
 386                 gic: interrupt-controller@3881000 {
 387                         compatible = "arm,gic-400";
 388                         #interrupt-cells = <3>;
 389                         interrupt-controller;
 390                         reg = <0x03881000 0x1000>,
 391                               <0x03882000 0x2000>,
 392                               <0x03884000 0x2000>,
 393                               <0x03886000 0x2000>;
 394                         interrupts = <GIC_PPI 9
 395                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 396                         interrupt-parent = <&gic>;
 397                 };
 398
 399                 cec@3960000 {
 400                         compatible = "nvidia,tegra194-cec";
 401                         reg = <0x03960000 0x10000>;
 402                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 403                         clocks = <&bpmp TEGRA194_CLK_CEC>;
 404                         clock-names = "cec";
 405                         status = "disabled";
 406                 };
 407
 408                 hsp_top0: hsp@3c00000 {
 409                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 410                         reg = <0x03c00000 0xa0000>;
 411                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 412                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 413                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 414                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 415                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 416                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 417                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 418                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 419                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 420                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
 421                                           "shared3", "shared4", "shared5", "shared6",
 422                                           "shared7";
 423                         #mbox-cells = <2>;
 424                 };
 425
 426                 hsp_aon: hsp@c150000 {
 427                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 428                         reg = <0x0c150000 0xa0000>;
 429                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 430                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 431                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 432                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 433                         /*
 434                          * Shared interrupt 0 is routed only to AON/SPE, so
 435                          * we only have 4 shared interrupts for the CCPLEX.
 436                          */
 437                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
 438                         #mbox-cells = <2>;
 439                 };
 440
 441                 gen2_i2c: i2c@c240000 {
 442                         compatible = "nvidia,tegra194-i2c";
 443                         reg = <0x0c240000 0x10000>;
 444                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
 448                         clock-names = "div-clk";
 449                         resets = <&bpmp TEGRA194_RESET_I2C2>;
 450                         reset-names = "i2c";
 451                         status = "disabled";
 452                 };
 453
 454                 gen8_i2c: i2c@c250000 {
 455                         compatible = "nvidia,tegra194-i2c";
 456                         reg = <0x0c250000 0x10000>;
 457                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 458                         #address-cells = <1>;
 459                         #size-cells = <0>;
 460                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
 461                         clock-names = "div-clk";
 462                         resets = <&bpmp TEGRA194_RESET_I2C8>;
 463                         reset-names = "i2c";
 464                         status = "disabled";
 465                 };
 466
 467                 uartc: serial@c280000 {
 468                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 469                         reg = <0x0c280000 0x40>;
 470                         reg-shift = <2>;
 471                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 472                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
 473                         clock-names = "serial";
 474                         resets = <&bpmp TEGRA194_RESET_UARTC>;
 475                         reset-names = "serial";
 476                         status = "disabled";
 477                 };
 478
 479                 uartg: serial@c290000 {
 480                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 481                         reg = <0x0c290000 0x40>;
 482                         reg-shift = <2>;
 483                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
 485                         clock-names = "serial";
 486                         resets = <&bpmp TEGRA194_RESET_UARTG>;
 487                         reset-names = "serial";
 488                         status = "disabled";
 489                 };
 490
 491                 rtc: rtc@c2a0000 {
 492                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
 493                         reg = <0x0c2a0000 0x10000>;
 494                         interrupt-parent = <&pmc>;
 495                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 496                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
 497                         clock-names = "rtc";
 498                         status = "disabled";
 499                 };
 500
 501                 gpio_aon: gpio@c2f0000 {
 502                         compatible = "nvidia,tegra194-gpio-aon";
 503                         reg-names = "security", "gpio";
 504                         reg = <0xc2f0000 0x1000>,
 505                               <0xc2f1000 0x1000>;
 506                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 507                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 508                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 509                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 510                         gpio-controller;
 511                         #gpio-cells = <2>;
 512                         interrupt-controller;
 513                         #interrupt-cells = <2>;
 514                 };
 515
 516                 pwm4: pwm@c340000 {
 517                         compatible = "nvidia,tegra194-pwm",
 518                                      "nvidia,tegra186-pwm";
 519                         reg = <0xc340000 0x10000>;
 520                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
 521                         clock-names = "pwm";
 522                         resets = <&bpmp TEGRA194_RESET_PWM4>;
 523                         reset-names = "pwm";
 524                         status = "disabled";
 525                         #pwm-cells = <2>;
 526                 };
 527
 528                 pmc: pmc@c360000 {
 529                         compatible = "nvidia,tegra194-pmc";
 530                         reg = <0x0c360000 0x10000>,
 531                               <0x0c370000 0x10000>,
 532                               <0x0c380000 0x10000>,
 533                               <0x0c390000 0x10000>,
 534                               <0x0c3a0000 0x10000>;
 535                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
 536
 537                         #interrupt-cells = <2>;
 538                         interrupt-controller;
 539                 };
 540
 541                 host1x@13e00000 {
 542                         compatible = "nvidia,tegra194-host1x", "simple-bus";
 543                         reg = <0x13e00000 0x10000>,
 544                               <0x13e10000 0x10000>;
 545                         reg-names = "hypervisor", "vm";
 546                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 548                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
 549                         clock-names = "host1x";
 550                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
 551                         reset-names = "host1x";
 552
 553                         #address-cells = <1>;
 554                         #size-cells = <1>;
 555
 556                         ranges = <0x15000000 0x15000000 0x01000000>;
 557
 558                         display-hub@15200000 {
 559                                 compatible = "nvidia,tegra194-display", "simple-bus";
 560                                 reg = <0x15200000 0x00040000>;
 561                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
 562                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
 563                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
 564                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
 565                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
 566                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
 567                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
 568                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 569                                               "wgrp3", "wgrp4", "wgrp5";
 570                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
 571                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
 572                                 clock-names = "disp", "hub";
 573                                 status = "disabled";
 574
 575                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 576
 577                                 #address-cells = <1>;
 578                                 #size-cells = <1>;
 579
 580                                 ranges = <0x15200000 0x15200000 0x40000>;
 581
 582                                 display@15200000 {
 583                                         compatible = "nvidia,tegra194-dc";
 584                                         reg = <0x15200000 0x10000>;
 585                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 586                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
 587                                         clock-names = "dc";
 588                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
 589                                         reset-names = "dc";
 590
 591                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 592
 593                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 594                                         nvidia,head = <0>;
 595                                 };
 596
 597                                 display@15210000 {
 598                                         compatible = "nvidia,tegra194-dc";
 599                                         reg = <0x15210000 0x10000>;
 600                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 601                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
 602                                         clock-names = "dc";
 603                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
 604                                         reset-names = "dc";
 605
 606                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
 607
 608                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 609                                         nvidia,head = <1>;
 610                                 };
 611
 612                                 display@15220000 {
 613                                         compatible = "nvidia,tegra194-dc";
 614                                         reg = <0x15220000 0x10000>;
 615                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 616                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
 617                                         clock-names = "dc";
 618                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
 619                                         reset-names = "dc";
 620
 621                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 622
 623                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 624                                         nvidia,head = <2>;
 625                                 };
 626
 627                                 display@15230000 {
 628                                         compatible = "nvidia,tegra194-dc";
 629                                         reg = <0x15230000 0x10000>;
 630                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 631                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
 632                                         clock-names = "dc";
 633                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
 634                                         reset-names = "dc";
 635
 636                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 637
 638                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 639                                         nvidia,head = <3>;
 640                                 };
 641                         };
 642
 643                         vic@15340000 {
 644                                 compatible = "nvidia,tegra194-vic";
 645                                 reg = <0x15340000 0x00040000>;
 646                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 647                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
 648                                 clock-names = "vic";
 649                                 resets = <&bpmp TEGRA194_RESET_VIC>;
 650                                 reset-names = "vic";
 651
 652                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
 653                         };
 654
 655                         dpaux0: dpaux@155c0000 {
 656                                 compatible = "nvidia,tegra194-dpaux";
 657                                 reg = <0x155c0000 0x10000>;
 658                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 659                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
 660                                          <&bpmp TEGRA194_CLK_PLLDP>;
 661                                 clock-names = "dpaux", "parent";
 662                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
 663                                 reset-names = "dpaux";
 664                                 status = "disabled";
 665
 666                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 667
 668                                 state_dpaux0_aux: pinmux-aux {
 669                                         groups = "dpaux-io";
 670                                         function = "aux";
 671                                 };
 672
 673                                 state_dpaux0_i2c: pinmux-i2c {
 674                                         groups = "dpaux-io";
 675                                         function = "i2c";
 676                                 };
 677
 678                                 state_dpaux0_off: pinmux-off {
 679                                         groups = "dpaux-io";
 680                                         function = "off";
 681                                 };
 682
 683                                 i2c-bus {
 684                                         #address-cells = <1>;
 685                                         #size-cells = <0>;
 686                                 };
 687                         };
 688
 689                         dpaux1: dpaux@155d0000 {
 690                                 compatible = "nvidia,tegra194-dpaux";
 691                                 reg = <0x155d0000 0x10000>;
 692                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 693                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
 694                                          <&bpmp TEGRA194_CLK_PLLDP>;
 695                                 clock-names = "dpaux", "parent";
 696                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
 697                                 reset-names = "dpaux";
 698                                 status = "disabled";
 699
 700                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 701
 702                                 state_dpaux1_aux: pinmux-aux {
 703                                         groups = "dpaux-io";
 704                                         function = "aux";
 705                                 };
 706
 707                                 state_dpaux1_i2c: pinmux-i2c {
 708                                         groups = "dpaux-io";
 709                                         function = "i2c";
 710                                 };
 711
 712                                 state_dpaux1_off: pinmux-off {
 713                                         groups = "dpaux-io";
 714                                         function = "off";
 715                                 };
 716
 717                                 i2c-bus {
 718                                         #address-cells = <1>;
 719                                         #size-cells = <0>;
 720                                 };
 721                         };
 722
 723                         dpaux2: dpaux@155e0000 {
 724                                 compatible = "nvidia,tegra194-dpaux";
 725                                 reg = <0x155e0000 0x10000>;
 726                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
 727                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
 728                                          <&bpmp TEGRA194_CLK_PLLDP>;
 729                                 clock-names = "dpaux", "parent";
 730                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
 731                                 reset-names = "dpaux";
 732                                 status = "disabled";
 733
 734                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 735
 736                                 state_dpaux2_aux: pinmux-aux {
 737                                         groups = "dpaux-io";
 738                                         function = "aux";
 739                                 };
 740
 741                                 state_dpaux2_i2c: pinmux-i2c {
 742                                         groups = "dpaux-io";
 743                                         function = "i2c";
 744                                 };
 745
 746                                 state_dpaux2_off: pinmux-off {
 747                                         groups = "dpaux-io";
 748                                         function = "off";
 749                                 };
 750
 751                                 i2c-bus {
 752                                         #address-cells = <1>;
 753                                         #size-cells = <0>;
 754                                 };
 755                         };
 756
 757                         dpaux3: dpaux@155f0000 {
 758                                 compatible = "nvidia,tegra194-dpaux";
 759                                 reg = <0x155f0000 0x10000>;
 760                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 761                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
 762                                          <&bpmp TEGRA194_CLK_PLLDP>;
 763                                 clock-names = "dpaux", "parent";
 764                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
 765                                 reset-names = "dpaux";
 766                                 status = "disabled";
 767
 768                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 769
 770                                 state_dpaux3_aux: pinmux-aux {
 771                                         groups = "dpaux-io";
 772                                         function = "aux";
 773                                 };
 774
 775                                 state_dpaux3_i2c: pinmux-i2c {
 776                                         groups = "dpaux-io";
 777                                         function = "i2c";
 778                                 };
 779
 780                                 state_dpaux3_off: pinmux-off {
 781                                         groups = "dpaux-io";
 782                                         function = "off";
 783                                 };
 784
 785                                 i2c-bus {
 786                                         #address-cells = <1>;
 787                                         #size-cells = <0>;
 788                                 };
 789                         };
 790
 791                         sor0: sor@15b00000 {
 792                                 compatible = "nvidia,tegra194-sor";
 793                                 reg = <0x15b00000 0x40000>;
 794                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
 796                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
 797                                          <&bpmp TEGRA194_CLK_PLLD>,
 798                                          <&bpmp TEGRA194_CLK_PLLDP>,
 799                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 800                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
 801                                 clock-names = "sor", "out", "parent", "dp", "safe",
 802                                               "pad";
 803                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
 804                                 reset-names = "sor";
 805                                 pinctrl-0 = <&state_dpaux0_aux>;
 806                                 pinctrl-1 = <&state_dpaux0_i2c>;
 807                                 pinctrl-2 = <&state_dpaux0_off>;
 808                                 pinctrl-names = "aux", "i2c", "off";
 809                                 status = "disabled";
 810
 811                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 812                                 nvidia,interface = <0>;
 813                         };
 814
 815                         sor1: sor@15b40000 {
 816                                 compatible = "nvidia,tegra194-sor";
 817                                 reg = <0x155c0000 0x40000>;
 818                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 819                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
 820                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
 821                                          <&bpmp TEGRA194_CLK_PLLD2>,
 822                                          <&bpmp TEGRA194_CLK_PLLDP>,
 823                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 824                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
 825                                 clock-names = "sor", "out", "parent", "dp", "safe",
 826                                               "pad";
 827                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
 828                                 reset-names = "sor";
 829                                 pinctrl-0 = <&state_dpaux1_aux>;
 830                                 pinctrl-1 = <&state_dpaux1_i2c>;
 831                                 pinctrl-2 = <&state_dpaux1_off>;
 832                                 pinctrl-names = "aux", "i2c", "off";
 833                                 status = "disabled";
 834
 835                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 836                                 nvidia,interface = <1>;
 837                         };
 838
 839                         sor2: sor@15b80000 {
 840                                 compatible = "nvidia,tegra194-sor";
 841                                 reg = <0x15b80000 0x40000>;
 842                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 843                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
 844                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
 845                                          <&bpmp TEGRA194_CLK_PLLD3>,
 846                                          <&bpmp TEGRA194_CLK_PLLDP>,
 847                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 848                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
 849                                 clock-names = "sor", "out", "parent", "dp", "safe",
 850                                               "pad";
 851                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
 852                                 reset-names = "sor";
 853                                 pinctrl-0 = <&state_dpaux2_aux>;
 854                                 pinctrl-1 = <&state_dpaux2_i2c>;
 855                                 pinctrl-2 = <&state_dpaux2_off>;
 856                                 pinctrl-names = "aux", "i2c", "off";
 857                                 status = "disabled";
 858
 859                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 860                                 nvidia,interface = <2>;
 861                         };
 862
 863                         sor3: sor@15bc0000 {
 864                                 compatible = "nvidia,tegra194-sor";
 865                                 reg = <0x15bc0000 0x40000>;
 866                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 867                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
 868                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
 869                                          <&bpmp TEGRA194_CLK_PLLD4>,
 870                                          <&bpmp TEGRA194_CLK_PLLDP>,
 871                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 872                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
 873                                 clock-names = "sor", "out", "parent", "dp", "safe",
 874                                               "pad";
 875                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
 876                                 reset-names = "sor";
 877                                 pinctrl-0 = <&state_dpaux3_aux>;
 878                                 pinctrl-1 = <&state_dpaux3_i2c>;
 879                                 pinctrl-2 = <&state_dpaux3_off>;
 880                                 pinctrl-names = "aux", "i2c", "off";
 881                                 status = "disabled";
 882
 883                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 884                                 nvidia,interface = <3>;
 885                         };
 886                 };
 887         };
 888
 889         sysram@40000000 {
 890                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
 891                 reg = <0x0 0x40000000 0x0 0x50000>;
 892                 #address-cells = <1>;
 893                 #size-cells = <1>;
 894                 ranges = <0x0 0x0 0x40000000 0x50000>;
 895
 896                 cpu_bpmp_tx: shmem@4e000 {
 897                         compatible = "nvidia,tegra194-bpmp-shmem";
 898                         reg = <0x4e000 0x1000>;
 899                         label = "cpu-bpmp-tx";
 900                         pool;
 901                 };
 902
 903                 cpu_bpmp_rx: shmem@4f000 {
 904                         compatible = "nvidia,tegra194-bpmp-shmem";
 905                         reg = <0x4f000 0x1000>;
 906                         label = "cpu-bpmp-rx";
 907                         pool;
 908                 };
 909         };
 910
 911         bpmp: bpmp {
 912                 compatible = "nvidia,tegra186-bpmp";
 913                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
 914                                     TEGRA_HSP_DB_MASTER_BPMP>;
 915                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
 916                 #clock-cells = <1>;
 917                 #reset-cells = <1>;
 918                 #power-domain-cells = <1>;
 919
 920                 bpmp_i2c: i2c {
 921                         compatible = "nvidia,tegra186-bpmp-i2c";
 922                         nvidia,bpmp-bus-id = <5>;
 923                         #address-cells = <1>;
 924                         #size-cells = <0>;
 925                 };
 926
 927                 bpmp_thermal: thermal {
 928                         compatible = "nvidia,tegra186-bpmp-thermal";
 929                         #thermal-sensor-cells = <1>;
 930                 };
 931         };
 932
 933         cpus {
 934                 #address-cells = <1>;
 935                 #size-cells = <0>;
 936
 937                 cpu@0 {
 938                         compatible = "nvidia,tegra194-carmel";
 939                         device_type = "cpu";
 940                         reg = <0x10000>;
 941                         enable-method = "psci";
 942                 };
 943
 944                 cpu@1 {
 945                         compatible = "nvidia,tegra194-carmel";
 946                         device_type = "cpu";
 947                         reg = <0x10001>;
 948                         enable-method = "psci";
 949                 };
 950
 951                 cpu@2 {
 952                         compatible = "nvidia,tegra194-carmel";
 953                         device_type = "cpu";
 954                         reg = <0x100>;
 955                         enable-method = "psci";
 956                 };
 957
 958                 cpu@3 {
 959                         compatible = "nvidia,tegra194-carmel";
 960                         device_type = "cpu";
 961                         reg = <0x101>;
 962                         enable-method = "psci";
 963                 };
 964
 965                 cpu@4 {
 966                         compatible = "nvidia,tegra194-carmel";
 967                         device_type = "cpu";
 968                         reg = <0x200>;
 969                         enable-method = "psci";
 970                 };
 971
 972                 cpu@5 {
 973                         compatible = "nvidia,tegra194-carmel";
 974                         device_type = "cpu";
 975                         reg = <0x201>;
 976                         enable-method = "psci";
 977                 };
 978
 979                 cpu@6 {
 980                         compatible = "nvidia,tegra194-carmel";
 981                         device_type = "cpu";
 982                         reg = <0x10300>;
 983                         enable-method = "psci";
 984                 };
 985
 986                 cpu@7 {
 987                         compatible = "nvidia,tegra194-carmel";
 988                         device_type = "cpu";
 989                         reg = <0x10301>;
 990                         enable-method = "psci";
 991                 };
 992         };
 993
 994         psci {
 995                 compatible = "arm,psci-1.0";
 996                 status = "okay";
 997                 method = "smc";
 998         };
 999
1000         tcu: tcu {
1001                 compatible = "nvidia,tegra194-tcu";
1002                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
1003                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
1004                 mbox-names = "rx", "tx";
1005         };
1006
1007         thermal-zones {
1008                 cpu {
1009                         thermal-sensors = <&{/bpmp/thermal}
1010                                            TEGRA194_BPMP_THERMAL_ZONE_CPU>;
1011                         status = "disabled";
1012                 };
1013
1014                 gpu {
1015                         thermal-sensors = <&{/bpmp/thermal}
1016                                            TEGRA194_BPMP_THERMAL_ZONE_GPU>;
1017                         status = "disabled";
1018                 };
1019
1020                 aux {
1021                         thermal-sensors = <&{/bpmp/thermal}
1022                                            TEGRA194_BPMP_THERMAL_ZONE_AUX>;
1023                         status = "disabled";
1024                 };
1025
1026                 pllx {
1027                         thermal-sensors = <&{/bpmp/thermal}
1028                                            TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
1029                         status = "disabled";
1030                 };
1031
1032                 ao {
1033                         thermal-sensors = <&{/bpmp/thermal}
1034                                            TEGRA194_BPMP_THERMAL_ZONE_AO>;
1035                         status = "disabled";
1036                 };
1037
1038                 tj {
1039                         thermal-sensors = <&{/bpmp/thermal}
1040                                            TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
1041                         status = "disabled";
1042                 };
1043         };
1044
1045         timer {
1046                 compatible = "arm,armv8-timer";
1047                 interrupts = <GIC_PPI 13
1048                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1049                              <GIC_PPI 14
1050                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1051                              <GIC_PPI 11
1052                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1053                              <GIC_PPI 10
1054                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1055                 interrupt-parent = <&gic>;
1056         };
1057 };