1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
13 compatible = "nvidia,tegra186";
14 interrupt-parent = <&gic>;
19 compatible = "nvidia,tegra186-misc";
20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
25 compatible = "nvidia,tegra186-gpio";
26 reg-names = "security", "gpio";
27 reg = <0x0 0x2200000 0x0 0x10000>,
28 <0x0 0x2210000 0x0 0x10000>;
29 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
30 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
35 #interrupt-cells = <2>;
42 compatible = "nvidia,tegra186-eqos",
43 "snps,dwc-qos-ethernet-4.10";
44 reg = <0x0 0x02490000 0x0 0x10000>;
45 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
46 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
47 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
48 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
49 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
50 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
51 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
52 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
53 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
54 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
55 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
56 <&bpmp TEGRA186_CLK_EQOS_AXI>,
57 <&bpmp TEGRA186_CLK_EQOS_RX>,
58 <&bpmp TEGRA186_CLK_EQOS_TX>,
59 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
61 resets = <&bpmp TEGRA186_RESET_EQOS>;
65 snps,write-requests = <1>;
66 snps,read-requests = <3>;
67 snps,burst-map = <0x7>;
72 memory-controller@2c00000 {
73 compatible = "nvidia,tegra186-mc";
74 reg = <0x0 0x02c00000 0x0 0xb0000>;
78 uarta: serial@3100000 {
79 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
80 reg = <0x0 0x03100000 0x0 0x40>;
82 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
83 clocks = <&bpmp TEGRA186_CLK_UARTA>;
84 clock-names = "serial";
85 resets = <&bpmp TEGRA186_RESET_UARTA>;
86 reset-names = "serial";
90 uartb: serial@3110000 {
91 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
92 reg = <0x0 0x03110000 0x0 0x40>;
94 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&bpmp TEGRA186_CLK_UARTB>;
96 clock-names = "serial";
97 resets = <&bpmp TEGRA186_RESET_UARTB>;
98 reset-names = "serial";
102 uartd: serial@3130000 {
103 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
104 reg = <0x0 0x03130000 0x0 0x40>;
106 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
107 clocks = <&bpmp TEGRA186_CLK_UARTD>;
108 clock-names = "serial";
109 resets = <&bpmp TEGRA186_RESET_UARTD>;
110 reset-names = "serial";
114 uarte: serial@3140000 {
115 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
116 reg = <0x0 0x03140000 0x0 0x40>;
118 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&bpmp TEGRA186_CLK_UARTE>;
120 clock-names = "serial";
121 resets = <&bpmp TEGRA186_RESET_UARTE>;
122 reset-names = "serial";
126 uartf: serial@3150000 {
127 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
128 reg = <0x0 0x03150000 0x0 0x40>;
130 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&bpmp TEGRA186_CLK_UARTF>;
132 clock-names = "serial";
133 resets = <&bpmp TEGRA186_RESET_UARTF>;
134 reset-names = "serial";
138 gen1_i2c: i2c@3160000 {
139 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
140 reg = <0x0 0x03160000 0x0 0x10000>;
141 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
142 #address-cells = <1>;
144 clocks = <&bpmp TEGRA186_CLK_I2C1>;
145 clock-names = "div-clk";
146 resets = <&bpmp TEGRA186_RESET_I2C1>;
151 cam_i2c: i2c@3180000 {
152 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
153 reg = <0x0 0x03180000 0x0 0x10000>;
154 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
155 #address-cells = <1>;
157 clocks = <&bpmp TEGRA186_CLK_I2C3>;
158 clock-names = "div-clk";
159 resets = <&bpmp TEGRA186_RESET_I2C3>;
164 /* shares pads with dpaux1 */
165 dp_aux_ch1_i2c: i2c@3190000 {
166 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
167 reg = <0x0 0x03190000 0x0 0x10000>;
168 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
169 #address-cells = <1>;
171 clocks = <&bpmp TEGRA186_CLK_I2C4>;
172 clock-names = "div-clk";
173 resets = <&bpmp TEGRA186_RESET_I2C4>;
178 /* controlled by BPMP, should not be enabled */
179 pwr_i2c: i2c@31a0000 {
180 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
181 reg = <0x0 0x031a0000 0x0 0x10000>;
182 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
183 #address-cells = <1>;
185 clocks = <&bpmp TEGRA186_CLK_I2C5>;
186 clock-names = "div-clk";
187 resets = <&bpmp TEGRA186_RESET_I2C5>;
192 /* shares pads with dpaux0 */
193 dp_aux_ch0_i2c: i2c@31b0000 {
194 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
195 reg = <0x0 0x031b0000 0x0 0x10000>;
196 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
197 #address-cells = <1>;
199 clocks = <&bpmp TEGRA186_CLK_I2C6>;
200 clock-names = "div-clk";
201 resets = <&bpmp TEGRA186_RESET_I2C6>;
206 gen7_i2c: i2c@31c0000 {
207 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
208 reg = <0x0 0x031c0000 0x0 0x10000>;
209 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
210 #address-cells = <1>;
212 clocks = <&bpmp TEGRA186_CLK_I2C7>;
213 clock-names = "div-clk";
214 resets = <&bpmp TEGRA186_RESET_I2C7>;
219 gen9_i2c: i2c@31e0000 {
220 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
221 reg = <0x0 0x031e0000 0x0 0x10000>;
222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
223 #address-cells = <1>;
225 clocks = <&bpmp TEGRA186_CLK_I2C9>;
226 clock-names = "div-clk";
227 resets = <&bpmp TEGRA186_RESET_I2C9>;
232 sdmmc1: sdhci@3400000 {
233 compatible = "nvidia,tegra186-sdhci";
234 reg = <0x0 0x03400000 0x0 0x10000>;
235 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
237 clock-names = "sdhci";
238 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
239 reset-names = "sdhci";
240 iommus = <&smmu TEGRA186_SID_SDMMC1>;
241 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
242 pinctrl-0 = <&sdmmc1_3v3>;
243 pinctrl-1 = <&sdmmc1_1v8>;
244 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
245 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
246 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
247 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
248 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
249 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
250 nvidia,default-tap = <0x5>;
251 nvidia,default-trim = <0xb>;
252 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
253 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
254 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
258 sdmmc2: sdhci@3420000 {
259 compatible = "nvidia,tegra186-sdhci";
260 reg = <0x0 0x03420000 0x0 0x10000>;
261 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
263 clock-names = "sdhci";
264 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
265 reset-names = "sdhci";
266 iommus = <&smmu TEGRA186_SID_SDMMC2>;
267 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
268 pinctrl-0 = <&sdmmc2_3v3>;
269 pinctrl-1 = <&sdmmc2_1v8>;
270 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
271 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
272 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
273 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
274 nvidia,default-tap = <0x5>;
275 nvidia,default-trim = <0xb>;
279 sdmmc3: sdhci@3440000 {
280 compatible = "nvidia,tegra186-sdhci";
281 reg = <0x0 0x03440000 0x0 0x10000>;
282 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
284 clock-names = "sdhci";
285 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
286 reset-names = "sdhci";
287 iommus = <&smmu TEGRA186_SID_SDMMC3>;
288 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
289 pinctrl-0 = <&sdmmc3_3v3>;
290 pinctrl-1 = <&sdmmc3_1v8>;
291 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
292 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
293 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
294 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
295 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
296 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
297 nvidia,default-tap = <0x5>;
298 nvidia,default-trim = <0xb>;
302 sdmmc4: sdhci@3460000 {
303 compatible = "nvidia,tegra186-sdhci";
304 reg = <0x0 0x03460000 0x0 0x10000>;
305 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
307 clock-names = "sdhci";
308 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
309 <&bpmp TEGRA186_CLK_PLLC4_VCO>;
310 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
311 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
312 reset-names = "sdhci";
313 iommus = <&smmu TEGRA186_SID_SDMMC4>;
314 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
315 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
316 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
317 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
318 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
319 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
320 nvidia,default-tap = <0x5>;
321 nvidia,default-trim = <0x9>;
322 nvidia,dqs-trim = <63>;
329 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
330 reg = <0x0 0x03510000 0x0 0x10000>;
331 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&bpmp TEGRA186_CLK_HDA>,
333 <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
334 <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
335 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
336 resets = <&bpmp TEGRA186_RESET_HDA>,
337 <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
338 <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
339 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
340 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
345 compatible = "nvidia,tegra186-efuse";
346 reg = <0x0 0x03820000 0x0 0x10000>;
347 clocks = <&bpmp TEGRA186_CLK_FUSE>;
348 clock-names = "fuse";
351 gic: interrupt-controller@3881000 {
352 compatible = "arm,gic-400";
353 #interrupt-cells = <3>;
354 interrupt-controller;
355 reg = <0x0 0x03881000 0x0 0x1000>,
356 <0x0 0x03882000 0x0 0x2000>;
357 interrupts = <GIC_PPI 9
358 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
359 interrupt-parent = <&gic>;
363 compatible = "nvidia,tegra186-cec";
364 reg = <0x0 0x03960000 0x0 0x10000>;
365 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&bpmp TEGRA186_CLK_CEC>;
371 hsp_top0: hsp@3c00000 {
372 compatible = "nvidia,tegra186-hsp";
373 reg = <0x0 0x03c00000 0x0 0xa0000>;
374 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-names = "doorbell";
380 gen2_i2c: i2c@c240000 {
381 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
382 reg = <0x0 0x0c240000 0x0 0x10000>;
383 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
384 #address-cells = <1>;
386 clocks = <&bpmp TEGRA186_CLK_I2C2>;
387 clock-names = "div-clk";
388 resets = <&bpmp TEGRA186_RESET_I2C2>;
393 gen8_i2c: i2c@c250000 {
394 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
395 reg = <0x0 0x0c250000 0x0 0x10000>;
396 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>;
399 clocks = <&bpmp TEGRA186_CLK_I2C8>;
400 clock-names = "div-clk";
401 resets = <&bpmp TEGRA186_RESET_I2C8>;
406 uartc: serial@c280000 {
407 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
408 reg = <0x0 0x0c280000 0x0 0x40>;
410 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&bpmp TEGRA186_CLK_UARTC>;
412 clock-names = "serial";
413 resets = <&bpmp TEGRA186_RESET_UARTC>;
414 reset-names = "serial";
418 uartg: serial@c290000 {
419 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
420 reg = <0x0 0x0c290000 0x0 0x40>;
422 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&bpmp TEGRA186_CLK_UARTG>;
424 clock-names = "serial";
425 resets = <&bpmp TEGRA186_RESET_UARTG>;
426 reset-names = "serial";
431 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
432 reg = <0 0x0c2a0000 0 0x10000>;
433 interrupt-parent = <&pmc>;
434 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
440 gpio_aon: gpio@c2f0000 {
441 compatible = "nvidia,tegra186-gpio-aon";
442 reg-names = "security", "gpio";
443 reg = <0x0 0xc2f0000 0x0 0x1000>,
444 <0x0 0xc2f1000 0x0 0x1000>;
445 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
453 compatible = "nvidia,tegra186-pmc";
454 reg = <0 0x0c360000 0 0x10000>,
455 <0 0x0c370000 0 0x10000>,
456 <0 0x0c380000 0 0x10000>,
457 <0 0x0c390000 0 0x10000>;
458 reg-names = "pmc", "wake", "aotag", "scratch";
460 #interrupt-cells = <2>;
461 interrupt-controller;
463 sdmmc1_3v3: sdmmc1-3v3 {
465 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
468 sdmmc1_1v8: sdmmc1-1v8 {
470 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
473 sdmmc2_3v3: sdmmc2-3v3 {
475 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
478 sdmmc2_1v8: sdmmc2-1v8 {
480 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
483 sdmmc3_3v3: sdmmc3-3v3 {
485 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
488 sdmmc3_1v8: sdmmc3-1v8 {
490 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
495 compatible = "nvidia,tegra186-ccplex-cluster";
496 reg = <0x0 0x0e000000 0x0 0x3fffff>;
498 nvidia,bpmp = <&bpmp>;
502 compatible = "nvidia,tegra186-pcie";
503 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
505 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
506 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
507 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
508 reg-names = "pads", "afi", "cs";
510 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
511 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
512 interrupt-names = "intr", "msi";
514 #interrupt-cells = <1>;
515 interrupt-map-mask = <0 0 0 0>;
516 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
518 bus-range = <0x00 0xff>;
519 #address-cells = <3>;
522 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
523 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
524 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
525 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
526 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
527 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
529 clocks = <&bpmp TEGRA186_CLK_AFI>,
530 <&bpmp TEGRA186_CLK_PCIE>,
531 <&bpmp TEGRA186_CLK_PLLE>;
532 clock-names = "afi", "pex", "pll_e";
534 resets = <&bpmp TEGRA186_RESET_AFI>,
535 <&bpmp TEGRA186_RESET_PCIE>,
536 <&bpmp TEGRA186_RESET_PCIEXCLK>;
537 reset-names = "afi", "pex", "pcie_x";
543 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
544 reg = <0x000800 0 0 0 0>;
547 #address-cells = <3>;
551 nvidia,num-lanes = <2>;
556 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
557 reg = <0x001000 0 0 0 0>;
560 #address-cells = <3>;
564 nvidia,num-lanes = <1>;
569 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
570 reg = <0x001800 0 0 0 0>;
573 #address-cells = <3>;
577 nvidia,num-lanes = <1>;
581 smmu: iommu@12000000 {
582 compatible = "arm,mmu-500";
583 reg = <0 0x12000000 0 0x800000>;
584 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
598 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
600 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
601 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
603 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
620 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
621 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
622 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
625 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
626 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
632 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
633 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
634 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
649 stream-match-mask = <0x7f80>;
650 #global-interrupts = <1>;
655 compatible = "nvidia,tegra186-host1x", "simple-bus";
656 reg = <0x0 0x13e00000 0x0 0x10000>,
657 <0x0 0x13e10000 0x0 0x10000>;
658 reg-names = "hypervisor", "vm";
659 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
662 clock-names = "host1x";
663 resets = <&bpmp TEGRA186_RESET_HOST1X>;
664 reset-names = "host1x";
666 #address-cells = <1>;
669 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
670 iommus = <&smmu TEGRA186_SID_HOST1X>;
672 dpaux1: dpaux@15040000 {
673 compatible = "nvidia,tegra186-dpaux";
674 reg = <0x15040000 0x10000>;
675 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
677 <&bpmp TEGRA186_CLK_PLLDP>;
678 clock-names = "dpaux", "parent";
679 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
680 reset-names = "dpaux";
683 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
685 state_dpaux1_aux: pinmux-aux {
690 state_dpaux1_i2c: pinmux-i2c {
695 state_dpaux1_off: pinmux-off {
701 #address-cells = <1>;
706 display-hub@15200000 {
707 compatible = "nvidia,tegra186-display", "simple-bus";
708 reg = <0x15200000 0x00040000>;
709 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
710 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
711 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
712 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
713 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
714 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
715 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
716 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
717 "wgrp3", "wgrp4", "wgrp5";
718 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
719 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
720 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
721 clock-names = "disp", "dsc", "hub";
724 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
726 #address-cells = <1>;
729 ranges = <0x15200000 0x15200000 0x40000>;
732 compatible = "nvidia,tegra186-dc";
733 reg = <0x15200000 0x10000>;
734 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
737 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
740 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
741 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
743 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
748 compatible = "nvidia,tegra186-dc";
749 reg = <0x15210000 0x10000>;
750 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
751 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
753 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
756 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
757 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
759 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
764 compatible = "nvidia,tegra186-dc";
765 reg = <0x15220000 0x10000>;
766 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
767 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
769 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
772 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
773 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
775 nvidia,outputs = <&sor0 &sor1>;
781 compatible = "nvidia,tegra186-dsi";
782 reg = <0x15300000 0x10000>;
783 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&bpmp TEGRA186_CLK_DSI>,
785 <&bpmp TEGRA186_CLK_DSIA_LP>,
786 <&bpmp TEGRA186_CLK_PLLD>;
787 clock-names = "dsi", "lp", "parent";
788 resets = <&bpmp TEGRA186_RESET_DSI>;
792 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
796 compatible = "nvidia,tegra186-vic";
797 reg = <0x15340000 0x40000>;
798 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&bpmp TEGRA186_CLK_VIC>;
801 resets = <&bpmp TEGRA186_RESET_VIC>;
804 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
808 compatible = "nvidia,tegra186-dsi";
809 reg = <0x15400000 0x10000>;
810 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&bpmp TEGRA186_CLK_DSIB>,
812 <&bpmp TEGRA186_CLK_DSIB_LP>,
813 <&bpmp TEGRA186_CLK_PLLD>;
814 clock-names = "dsi", "lp", "parent";
815 resets = <&bpmp TEGRA186_RESET_DSIB>;
819 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
823 compatible = "nvidia,tegra186-sor";
824 reg = <0x15540000 0x10000>;
825 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&bpmp TEGRA186_CLK_SOR0>,
827 <&bpmp TEGRA186_CLK_SOR0_OUT>,
828 <&bpmp TEGRA186_CLK_PLLD2>,
829 <&bpmp TEGRA186_CLK_PLLDP>,
830 <&bpmp TEGRA186_CLK_SOR_SAFE>,
831 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
832 clock-names = "sor", "out", "parent", "dp", "safe",
834 resets = <&bpmp TEGRA186_RESET_SOR0>;
836 pinctrl-0 = <&state_dpaux_aux>;
837 pinctrl-1 = <&state_dpaux_i2c>;
838 pinctrl-2 = <&state_dpaux_off>;
839 pinctrl-names = "aux", "i2c", "off";
842 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
843 nvidia,interface = <0>;
847 compatible = "nvidia,tegra186-sor1";
848 reg = <0x15580000 0x10000>;
849 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&bpmp TEGRA186_CLK_SOR1>,
851 <&bpmp TEGRA186_CLK_SOR1_OUT>,
852 <&bpmp TEGRA186_CLK_PLLD3>,
853 <&bpmp TEGRA186_CLK_PLLDP>,
854 <&bpmp TEGRA186_CLK_SOR_SAFE>,
855 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
856 clock-names = "sor", "out", "parent", "dp", "safe",
858 resets = <&bpmp TEGRA186_RESET_SOR1>;
860 pinctrl-0 = <&state_dpaux1_aux>;
861 pinctrl-1 = <&state_dpaux1_i2c>;
862 pinctrl-2 = <&state_dpaux1_off>;
863 pinctrl-names = "aux", "i2c", "off";
866 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
867 nvidia,interface = <1>;
870 dpaux: dpaux@155c0000 {
871 compatible = "nvidia,tegra186-dpaux";
872 reg = <0x155c0000 0x10000>;
873 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
875 <&bpmp TEGRA186_CLK_PLLDP>;
876 clock-names = "dpaux", "parent";
877 resets = <&bpmp TEGRA186_RESET_DPAUX>;
878 reset-names = "dpaux";
881 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
883 state_dpaux_aux: pinmux-aux {
888 state_dpaux_i2c: pinmux-i2c {
893 state_dpaux_off: pinmux-off {
899 #address-cells = <1>;
905 compatible = "nvidia,tegra186-dsi-padctl";
906 reg = <0x15880000 0x10000>;
907 resets = <&bpmp TEGRA186_RESET_DSI>;
913 compatible = "nvidia,tegra186-dsi";
914 reg = <0x15900000 0x10000>;
915 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&bpmp TEGRA186_CLK_DSIC>,
917 <&bpmp TEGRA186_CLK_DSIC_LP>,
918 <&bpmp TEGRA186_CLK_PLLD>;
919 clock-names = "dsi", "lp", "parent";
920 resets = <&bpmp TEGRA186_RESET_DSIC>;
924 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
928 compatible = "nvidia,tegra186-dsi";
929 reg = <0x15940000 0x10000>;
930 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&bpmp TEGRA186_CLK_DSID>,
932 <&bpmp TEGRA186_CLK_DSID_LP>,
933 <&bpmp TEGRA186_CLK_PLLD>;
934 clock-names = "dsi", "lp", "parent";
935 resets = <&bpmp TEGRA186_RESET_DSID>;
939 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
944 compatible = "nvidia,gp10b";
945 reg = <0x0 0x17000000 0x0 0x1000000>,
946 <0x0 0x18000000 0x0 0x1000000>;
947 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
948 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
949 interrupt-names = "stall", "nonstall";
951 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
952 <&bpmp TEGRA186_CLK_GPU>;
953 clock-names = "gpu", "pwr";
954 resets = <&bpmp TEGRA186_RESET_GPU>;
958 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
962 compatible = "nvidia,tegra186-sysram", "mmio-sram";
963 reg = <0x0 0x30000000 0x0 0x50000>;
964 #address-cells = <2>;
966 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
968 cpu_bpmp_tx: shmem@4e000 {
969 compatible = "nvidia,tegra186-bpmp-shmem";
970 reg = <0x0 0x4e000 0x0 0x1000>;
971 label = "cpu-bpmp-tx";
975 cpu_bpmp_rx: shmem@4f000 {
976 compatible = "nvidia,tegra186-bpmp-shmem";
977 reg = <0x0 0x4f000 0x0 0x1000>;
978 label = "cpu-bpmp-rx";
984 #address-cells = <1>;
988 compatible = "nvidia,tegra186-denver";
994 compatible = "nvidia,tegra186-denver";
1000 compatible = "arm,cortex-a57";
1001 device_type = "cpu";
1006 compatible = "arm,cortex-a57";
1007 device_type = "cpu";
1012 compatible = "arm,cortex-a57";
1013 device_type = "cpu";
1018 compatible = "arm,cortex-a57";
1019 device_type = "cpu";
1025 compatible = "nvidia,tegra186-bpmp";
1026 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1027 TEGRA_HSP_DB_MASTER_BPMP>;
1028 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1031 #power-domain-cells = <1>;
1034 compatible = "nvidia,tegra186-bpmp-i2c";
1035 nvidia,bpmp-bus-id = <5>;
1036 #address-cells = <1>;
1038 status = "disabled";
1041 bpmp_thermal: thermal {
1042 compatible = "nvidia,tegra186-bpmp-thermal";
1043 #thermal-sensor-cells = <1>;
1049 polling-delay = <0>;
1050 polling-delay-passive = <1000>;
1053 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1057 temperature = <101000>;
1068 polling-delay = <0>;
1069 polling-delay-passive = <1000>;
1072 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1076 temperature = <101000>;
1087 polling-delay = <0>;
1088 polling-delay-passive = <1000>;
1091 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1095 temperature = <101000>;
1106 polling-delay = <0>;
1107 polling-delay-passive = <1000>;
1110 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1114 temperature = <101000>;
1125 polling-delay = <0>;
1126 polling-delay-passive = <1000>;
1129 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1133 temperature = <101000>;
1145 compatible = "arm,armv8-timer";
1146 interrupts = <GIC_PPI 13
1147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1149 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1151 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1153 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1154 interrupt-parent = <&gic>;