arch/arm64/boot/dts/nvidia/tegra186.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra186-clock.h>
   3 #include <dt-bindings/gpio/tegra186-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/power/tegra186-powergate.h>
   7 #include <dt-bindings/reset/tegra186-reset.h>
   8
   9 / {
  10         compatible = "nvidia,tegra186";
  11         interrupt-parent = <&gic>;
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         gpio: gpio@2200000 {
  16                 compatible = "nvidia,tegra186-gpio";
  17                 reg-names = "security", "gpio";
  18                 reg = <0x0 0x2200000 0x0 0x10000>,
  19                       <0x0 0x2210000 0x0 0x10000>;
  20                 interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
  21                              <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
  22                              <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
  23                              <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
  24                              <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
  25                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  26                 #interrupt-cells = <2>;
  27                 interrupt-controller;
  28                 #gpio-cells = <2>;
  29                 gpio-controller;
  30         };
  31
  32         ethernet@2490000 {
  33                 compatible = "nvidia,tegra186-eqos",
  34                              "snps,dwc-qos-ethernet-4.10";
  35                 reg = <0x0 0x02490000 0x0 0x10000>;
  36                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
  37                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
  38                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
  39                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
  40                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
  41                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
  42                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
  43                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
  44                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
  45                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
  46                 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  47                          <&bpmp TEGRA186_CLK_EQOS_AXI>,
  48                          <&bpmp TEGRA186_CLK_EQOS_RX>,
  49                          <&bpmp TEGRA186_CLK_EQOS_TX>,
  50                          <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
  51                 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  52                 resets = <&bpmp TEGRA186_RESET_EQOS>;
  53                 reset-names = "eqos";
  54                 status = "disabled";
  55
  56                 snps,write-requests = <1>;
  57                 snps,read-requests = <3>;
  58                 snps,burst-map = <0x7>;
  59                 snps,txpbl = <32>;
  60                 snps,rxpbl = <8>;
  61         };
  62
  63         uarta: serial@3100000 {
  64                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  65                 reg = <0x0 0x03100000 0x0 0x40>;
  66                 reg-shift = <2>;
  67                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  68                 clocks = <&bpmp TEGRA186_CLK_UARTA>;
  69                 clock-names = "serial";
  70                 resets = <&bpmp TEGRA186_RESET_UARTA>;
  71                 reset-names = "serial";
  72                 status = "disabled";
  73         };
  74
  75         uartb: serial@3110000 {
  76                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  77                 reg = <0x0 0x03110000 0x0 0x40>;
  78                 reg-shift = <2>;
  79                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  80                 clocks = <&bpmp TEGRA186_CLK_UARTB>;
  81                 clock-names = "serial";
  82                 resets = <&bpmp TEGRA186_RESET_UARTB>;
  83                 reset-names = "serial";
  84                 status = "disabled";
  85         };
  86
  87         uartd: serial@3130000 {
  88                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  89                 reg = <0x0 0x03130000 0x0 0x40>;
  90                 reg-shift = <2>;
  91                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  92                 clocks = <&bpmp TEGRA186_CLK_UARTD>;
  93                 clock-names = "serial";
  94                 resets = <&bpmp TEGRA186_RESET_UARTD>;
  95                 reset-names = "serial";
  96                 status = "disabled";
  97         };
  98
  99         uarte: serial@3140000 {
 100                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 101                 reg = <0x0 0x03140000 0x0 0x40>;
 102                 reg-shift = <2>;
 103                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 104                 clocks = <&bpmp TEGRA186_CLK_UARTE>;
 105                 clock-names = "serial";
 106                 resets = <&bpmp TEGRA186_RESET_UARTE>;
 107                 reset-names = "serial";
 108                 status = "disabled";
 109         };
 110
 111         uartf: serial@3150000 {
 112                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 113                 reg = <0x0 0x03150000 0x0 0x40>;
 114                 reg-shift = <2>;
 115                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 116                 clocks = <&bpmp TEGRA186_CLK_UARTF>;
 117                 clock-names = "serial";
 118                 resets = <&bpmp TEGRA186_RESET_UARTF>;
 119                 reset-names = "serial";
 120                 status = "disabled";
 121         };
 122
 123         gen1_i2c: i2c@3160000 {
 124                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 125                 reg = <0x0 0x03160000 0x0 0x10000>;
 126                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 127                 #address-cells = <1>;
 128                 #size-cells = <0>;
 129                 clocks = <&bpmp TEGRA186_CLK_I2C1>;
 130                 clock-names = "div-clk";
 131                 resets = <&bpmp TEGRA186_RESET_I2C1>;
 132                 reset-names = "i2c";
 133                 status = "disabled";
 134         };
 135
 136         cam_i2c: i2c@3180000 {
 137                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 138                 reg = <0x0 0x03180000 0x0 0x10000>;
 139                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 140                 #address-cells = <1>;
 141                 #size-cells = <0>;
 142                 clocks = <&bpmp TEGRA186_CLK_I2C3>;
 143                 clock-names = "div-clk";
 144                 resets = <&bpmp TEGRA186_RESET_I2C3>;
 145                 reset-names = "i2c";
 146                 status = "disabled";
 147         };
 148
 149         /* shares pads with dpaux1 */
 150         dp_aux_ch1_i2c: i2c@3190000 {
 151                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 152                 reg = <0x0 0x03190000 0x0 0x10000>;
 153                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156                 clocks = <&bpmp TEGRA186_CLK_I2C4>;
 157                 clock-names = "div-clk";
 158                 resets = <&bpmp TEGRA186_RESET_I2C4>;
 159                 reset-names = "i2c";
 160                 status = "disabled";
 161         };
 162
 163         /* controlled by BPMP, should not be enabled */
 164         pwr_i2c: i2c@31a0000 {
 165                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 166                 reg = <0x0 0x031a0000 0x0 0x10000>;
 167                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170                 clocks = <&bpmp TEGRA186_CLK_I2C5>;
 171                 clock-names = "div-clk";
 172                 resets = <&bpmp TEGRA186_RESET_I2C5>;
 173                 reset-names = "i2c";
 174                 status = "disabled";
 175         };
 176
 177         /* shares pads with dpaux0 */
 178         dp_aux_ch0_i2c: i2c@31b0000 {
 179                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 180                 reg = <0x0 0x031b0000 0x0 0x10000>;
 181                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 clocks = <&bpmp TEGRA186_CLK_I2C6>;
 185                 clock-names = "div-clk";
 186                 resets = <&bpmp TEGRA186_RESET_I2C6>;
 187                 reset-names = "i2c";
 188                 status = "disabled";
 189         };
 190
 191         gen7_i2c: i2c@31c0000 {
 192                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 193                 reg = <0x0 0x031c0000 0x0 0x10000>;
 194                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 clocks = <&bpmp TEGRA186_CLK_I2C7>;
 198                 clock-names = "div-clk";
 199                 resets = <&bpmp TEGRA186_RESET_I2C7>;
 200                 reset-names = "i2c";
 201                 status = "disabled";
 202         };
 203
 204         gen9_i2c: i2c@31e0000 {
 205                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 206                 reg = <0x0 0x031e0000 0x0 0x10000>;
 207                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210                 clocks = <&bpmp TEGRA186_CLK_I2C9>;
 211                 clock-names = "div-clk";
 212                 resets = <&bpmp TEGRA186_RESET_I2C9>;
 213                 reset-names = "i2c";
 214                 status = "disabled";
 215         };
 216
 217         sdmmc1: sdhci@3400000 {
 218                 compatible = "nvidia,tegra186-sdhci";
 219                 reg = <0x0 0x03400000 0x0 0x10000>;
 220                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
 222                 clock-names = "sdhci";
 223                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
 224                 reset-names = "sdhci";
 225                 status = "disabled";
 226         };
 227
 228         sdmmc2: sdhci@3420000 {
 229                 compatible = "nvidia,tegra186-sdhci";
 230                 reg = <0x0 0x03420000 0x0 0x10000>;
 231                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
 233                 clock-names = "sdhci";
 234                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
 235                 reset-names = "sdhci";
 236                 status = "disabled";
 237         };
 238
 239         sdmmc3: sdhci@3440000 {
 240                 compatible = "nvidia,tegra186-sdhci";
 241                 reg = <0x0 0x03440000 0x0 0x10000>;
 242                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
 244                 clock-names = "sdhci";
 245                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
 246                 reset-names = "sdhci";
 247                 status = "disabled";
 248         };
 249
 250         sdmmc4: sdhci@3460000 {
 251                 compatible = "nvidia,tegra186-sdhci";
 252                 reg = <0x0 0x03460000 0x0 0x10000>;
 253                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 254                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
 255                 clock-names = "sdhci";
 256                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
 257                 reset-names = "sdhci";
 258                 status = "disabled";
 259         };
 260
 261         gic: interrupt-controller@3881000 {
 262                 compatible = "arm,gic-400";
 263                 #interrupt-cells = <3>;
 264                 interrupt-controller;
 265                 reg = <0x0 0x03881000 0x0 0x1000>,
 266                       <0x0 0x03882000 0x0 0x2000>;
 267                 interrupts = <GIC_PPI 9
 268                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 269                 interrupt-parent = <&gic>;
 270         };
 271
 272         hsp_top0: hsp@3c00000 {
 273                 compatible = "nvidia,tegra186-hsp";
 274                 reg = <0x0 0x03c00000 0x0 0xa0000>;
 275                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 276                 interrupt-names = "doorbell";
 277                 #mbox-cells = <2>;
 278                 status = "disabled";
 279         };
 280
 281         gen2_i2c: i2c@c240000 {
 282                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 283                 reg = <0x0 0x0c240000 0x0 0x10000>;
 284                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 clocks = <&bpmp TEGRA186_CLK_I2C2>;
 288                 clock-names = "div-clk";
 289                 resets = <&bpmp TEGRA186_RESET_I2C2>;
 290                 reset-names = "i2c";
 291                 status = "disabled";
 292         };
 293
 294         gen8_i2c: i2c@c250000 {
 295                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 296                 reg = <0x0 0x0c250000 0x0 0x10000>;
 297                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 298                 #address-cells = <1>;
 299                 #size-cells = <0>;
 300                 clocks = <&bpmp TEGRA186_CLK_I2C8>;
 301                 clock-names = "div-clk";
 302                 resets = <&bpmp TEGRA186_RESET_I2C8>;
 303                 reset-names = "i2c";
 304                 status = "disabled";
 305         };
 306
 307         uartc: serial@c280000 {
 308                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 309                 reg = <0x0 0x0c280000 0x0 0x40>;
 310                 reg-shift = <2>;
 311                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&bpmp TEGRA186_CLK_UARTC>;
 313                 clock-names = "serial";
 314                 resets = <&bpmp TEGRA186_RESET_UARTC>;
 315                 reset-names = "serial";
 316                 status = "disabled";
 317         };
 318
 319         uartg: serial@c290000 {
 320                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 321                 reg = <0x0 0x0c290000 0x0 0x40>;
 322                 reg-shift = <2>;
 323                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&bpmp TEGRA186_CLK_UARTG>;
 325                 clock-names = "serial";
 326                 resets = <&bpmp TEGRA186_RESET_UARTG>;
 327                 reset-names = "serial";
 328                 status = "disabled";
 329         };
 330
 331         gpio_aon: gpio@c2f0000 {
 332                 compatible = "nvidia,tegra186-gpio-aon";
 333                 reg-names = "security", "gpio";
 334                 reg = <0x0 0xc2f0000 0x0 0x1000>,
 335                       <0x0 0xc2f1000 0x0 0x1000>;
 336                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 337                 gpio-controller;
 338                 #gpio-cells = <2>;
 339                 interrupt-controller;
 340                 #interrupt-cells = <2>;
 341         };
 342
 343         pmc@c360000 {
 344                 compatible = "nvidia,tegra186-pmc";
 345                 reg = <0 0x0c360000 0 0x10000>,
 346                       <0 0x0c370000 0 0x10000>,
 347                       <0 0x0c380000 0 0x10000>,
 348                       <0 0x0c390000 0 0x10000>;
 349                 reg-names = "pmc", "wake", "aotag", "scratch";
 350         };
 351
 352         ccplex@e000000 {
 353                 compatible = "nvidia,tegra186-ccplex-cluster";
 354                 reg = <0x0 0x0e000000 0x0 0x3fffff>;
 355
 356                 nvidia,bpmp = <&bpmp>;
 357         };
 358
 359         gpu@17000000 {
 360                 compatible = "nvidia,gp10b";
 361                 reg = <0x0 0x17000000 0x0 0x1000000>,
 362                       <0x0 0x18000000 0x0 0x1000000>;
 363                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
 364                               GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 365                 interrupt-names = "stall", "nonstall";
 366
 367                 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
 368                          <&bpmp TEGRA186_CLK_GPU>;
 369                 clock-names = "gpu", "pwr";
 370                 resets = <&bpmp TEGRA186_RESET_GPU>;
 371                 reset-names = "gpu";
 372                 status = "disabled";
 373
 374                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
 375         };
 376
 377         sysram@30000000 {
 378                 compatible = "nvidia,tegra186-sysram", "mmio-sram";
 379                 reg = <0x0 0x30000000 0x0 0x50000>;
 380                 #address-cells = <2>;
 381                 #size-cells = <2>;
 382                 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
 383
 384                 cpu_bpmp_tx: shmem@4e000 {
 385                         compatible = "nvidia,tegra186-bpmp-shmem";
 386                         reg = <0x0 0x4e000 0x0 0x1000>;
 387                         label = "cpu-bpmp-tx";
 388                         pool;
 389                 };
 390
 391                 cpu_bpmp_rx: shmem@4f000 {
 392                         compatible = "nvidia,tegra186-bpmp-shmem";
 393                         reg = <0x0 0x4f000 0x0 0x1000>;
 394                         label = "cpu-bpmp-rx";
 395                         pool;
 396                 };
 397         };
 398
 399         cpus {
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402
 403                 cpu@0 {
 404                         compatible = "nvidia,tegra186-denver", "arm,armv8";
 405                         device_type = "cpu";
 406                         reg = <0x000>;
 407                 };
 408
 409                 cpu@1 {
 410                         compatible = "nvidia,tegra186-denver", "arm,armv8";
 411                         device_type = "cpu";
 412                         reg = <0x001>;
 413                 };
 414
 415                 cpu@2 {
 416                         compatible = "arm,cortex-a57", "arm,armv8";
 417                         device_type = "cpu";
 418                         reg = <0x100>;
 419                 };
 420
 421                 cpu@3 {
 422                         compatible = "arm,cortex-a57", "arm,armv8";
 423                         device_type = "cpu";
 424                         reg = <0x101>;
 425                 };
 426
 427                 cpu@4 {
 428                         compatible = "arm,cortex-a57", "arm,armv8";
 429                         device_type = "cpu";
 430                         reg = <0x102>;
 431                 };
 432
 433                 cpu@5 {
 434                         compatible = "arm,cortex-a57", "arm,armv8";
 435                         device_type = "cpu";
 436                         reg = <0x103>;
 437                 };
 438         };
 439
 440         bpmp: bpmp {
 441                 compatible = "nvidia,tegra186-bpmp";
 442                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
 443                                     TEGRA_HSP_DB_MASTER_BPMP>;
 444                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
 445                 #clock-cells = <1>;
 446                 #reset-cells = <1>;
 447
 448                 bpmp_i2c: i2c {
 449                         compatible = "nvidia,tegra186-bpmp-i2c";
 450                         nvidia,bpmp-bus-id = <5>;
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         status = "disabled";
 454                 };
 455         };
 456
 457         timer {
 458                 compatible = "arm,armv8-timer";
 459                 interrupts = <GIC_PPI 13
 460                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 461                              <GIC_PPI 14
 462                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 463                              <GIC_PPI 11
 464                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 465                              <GIC_PPI 10
 466                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 467                 interrupt-parent = <&gic>;
 468         };
 469 };