arch/arm64/boot/dts/nvidia/tegra186.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra186-clock.h>
   3 #include <dt-bindings/gpio/tegra186-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/power/tegra186-powergate.h>
   7 #include <dt-bindings/reset/tegra186-reset.h>
   8 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
   9
  10 / {
  11         compatible = "nvidia,tegra186";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         gpio: gpio@2200000 {
  17                 compatible = "nvidia,tegra186-gpio";
  18                 reg-names = "security", "gpio";
  19                 reg = <0x0 0x2200000 0x0 0x10000>,
  20                       <0x0 0x2210000 0x0 0x10000>;
  21                 interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
  22                              <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
  23                              <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
  24                              <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
  25                              <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
  26                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  27                 #interrupt-cells = <2>;
  28                 interrupt-controller;
  29                 #gpio-cells = <2>;
  30                 gpio-controller;
  31         };
  32
  33         ethernet@2490000 {
  34                 compatible = "nvidia,tegra186-eqos",
  35                              "snps,dwc-qos-ethernet-4.10";
  36                 reg = <0x0 0x02490000 0x0 0x10000>;
  37                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
  38                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
  39                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
  40                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
  41                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
  42                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
  43                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
  44                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
  45                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
  46                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
  47                 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  48                          <&bpmp TEGRA186_CLK_EQOS_AXI>,
  49                          <&bpmp TEGRA186_CLK_EQOS_RX>,
  50                          <&bpmp TEGRA186_CLK_EQOS_TX>,
  51                          <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
  52                 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  53                 resets = <&bpmp TEGRA186_RESET_EQOS>;
  54                 reset-names = "eqos";
  55                 status = "disabled";
  56
  57                 snps,write-requests = <1>;
  58                 snps,read-requests = <3>;
  59                 snps,burst-map = <0x7>;
  60                 snps,txpbl = <32>;
  61                 snps,rxpbl = <8>;
  62         };
  63
  64         uarta: serial@3100000 {
  65                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  66                 reg = <0x0 0x03100000 0x0 0x40>;
  67                 reg-shift = <2>;
  68                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  69                 clocks = <&bpmp TEGRA186_CLK_UARTA>;
  70                 clock-names = "serial";
  71                 resets = <&bpmp TEGRA186_RESET_UARTA>;
  72                 reset-names = "serial";
  73                 status = "disabled";
  74         };
  75
  76         uartb: serial@3110000 {
  77                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  78                 reg = <0x0 0x03110000 0x0 0x40>;
  79                 reg-shift = <2>;
  80                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  81                 clocks = <&bpmp TEGRA186_CLK_UARTB>;
  82                 clock-names = "serial";
  83                 resets = <&bpmp TEGRA186_RESET_UARTB>;
  84                 reset-names = "serial";
  85                 status = "disabled";
  86         };
  87
  88         uartd: serial@3130000 {
  89                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
  90                 reg = <0x0 0x03130000 0x0 0x40>;
  91                 reg-shift = <2>;
  92                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  93                 clocks = <&bpmp TEGRA186_CLK_UARTD>;
  94                 clock-names = "serial";
  95                 resets = <&bpmp TEGRA186_RESET_UARTD>;
  96                 reset-names = "serial";
  97                 status = "disabled";
  98         };
  99
 100         uarte: serial@3140000 {
 101                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 102                 reg = <0x0 0x03140000 0x0 0x40>;
 103                 reg-shift = <2>;
 104                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 105                 clocks = <&bpmp TEGRA186_CLK_UARTE>;
 106                 clock-names = "serial";
 107                 resets = <&bpmp TEGRA186_RESET_UARTE>;
 108                 reset-names = "serial";
 109                 status = "disabled";
 110         };
 111
 112         uartf: serial@3150000 {
 113                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 114                 reg = <0x0 0x03150000 0x0 0x40>;
 115                 reg-shift = <2>;
 116                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 117                 clocks = <&bpmp TEGRA186_CLK_UARTF>;
 118                 clock-names = "serial";
 119                 resets = <&bpmp TEGRA186_RESET_UARTF>;
 120                 reset-names = "serial";
 121                 status = "disabled";
 122         };
 123
 124         gen1_i2c: i2c@3160000 {
 125                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 126                 reg = <0x0 0x03160000 0x0 0x10000>;
 127                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130                 clocks = <&bpmp TEGRA186_CLK_I2C1>;
 131                 clock-names = "div-clk";
 132                 resets = <&bpmp TEGRA186_RESET_I2C1>;
 133                 reset-names = "i2c";
 134                 status = "disabled";
 135         };
 136
 137         cam_i2c: i2c@3180000 {
 138                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 139                 reg = <0x0 0x03180000 0x0 0x10000>;
 140                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 141                 #address-cells = <1>;
 142                 #size-cells = <0>;
 143                 clocks = <&bpmp TEGRA186_CLK_I2C3>;
 144                 clock-names = "div-clk";
 145                 resets = <&bpmp TEGRA186_RESET_I2C3>;
 146                 reset-names = "i2c";
 147                 status = "disabled";
 148         };
 149
 150         /* shares pads with dpaux1 */
 151         dp_aux_ch1_i2c: i2c@3190000 {
 152                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 153                 reg = <0x0 0x03190000 0x0 0x10000>;
 154                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 155                 #address-cells = <1>;
 156                 #size-cells = <0>;
 157                 clocks = <&bpmp TEGRA186_CLK_I2C4>;
 158                 clock-names = "div-clk";
 159                 resets = <&bpmp TEGRA186_RESET_I2C4>;
 160                 reset-names = "i2c";
 161                 status = "disabled";
 162         };
 163
 164         /* controlled by BPMP, should not be enabled */
 165         pwr_i2c: i2c@31a0000 {
 166                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 167                 reg = <0x0 0x031a0000 0x0 0x10000>;
 168                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171                 clocks = <&bpmp TEGRA186_CLK_I2C5>;
 172                 clock-names = "div-clk";
 173                 resets = <&bpmp TEGRA186_RESET_I2C5>;
 174                 reset-names = "i2c";
 175                 status = "disabled";
 176         };
 177
 178         /* shares pads with dpaux0 */
 179         dp_aux_ch0_i2c: i2c@31b0000 {
 180                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 181                 reg = <0x0 0x031b0000 0x0 0x10000>;
 182                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 clocks = <&bpmp TEGRA186_CLK_I2C6>;
 186                 clock-names = "div-clk";
 187                 resets = <&bpmp TEGRA186_RESET_I2C6>;
 188                 reset-names = "i2c";
 189                 status = "disabled";
 190         };
 191
 192         gen7_i2c: i2c@31c0000 {
 193                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 194                 reg = <0x0 0x031c0000 0x0 0x10000>;
 195                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 clocks = <&bpmp TEGRA186_CLK_I2C7>;
 199                 clock-names = "div-clk";
 200                 resets = <&bpmp TEGRA186_RESET_I2C7>;
 201                 reset-names = "i2c";
 202                 status = "disabled";
 203         };
 204
 205         gen9_i2c: i2c@31e0000 {
 206                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 207                 reg = <0x0 0x031e0000 0x0 0x10000>;
 208                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 209                 #address-cells = <1>;
 210                 #size-cells = <0>;
 211                 clocks = <&bpmp TEGRA186_CLK_I2C9>;
 212                 clock-names = "div-clk";
 213                 resets = <&bpmp TEGRA186_RESET_I2C9>;
 214                 reset-names = "i2c";
 215                 status = "disabled";
 216         };
 217
 218         sdmmc1: sdhci@3400000 {
 219                 compatible = "nvidia,tegra186-sdhci";
 220                 reg = <0x0 0x03400000 0x0 0x10000>;
 221                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 222                 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
 223                 clock-names = "sdhci";
 224                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
 225                 reset-names = "sdhci";
 226                 status = "disabled";
 227         };
 228
 229         sdmmc2: sdhci@3420000 {
 230                 compatible = "nvidia,tegra186-sdhci";
 231                 reg = <0x0 0x03420000 0x0 0x10000>;
 232                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
 234                 clock-names = "sdhci";
 235                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
 236                 reset-names = "sdhci";
 237                 status = "disabled";
 238         };
 239
 240         sdmmc3: sdhci@3440000 {
 241                 compatible = "nvidia,tegra186-sdhci";
 242                 reg = <0x0 0x03440000 0x0 0x10000>;
 243                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 244                 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
 245                 clock-names = "sdhci";
 246                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
 247                 reset-names = "sdhci";
 248                 status = "disabled";
 249         };
 250
 251         sdmmc4: sdhci@3460000 {
 252                 compatible = "nvidia,tegra186-sdhci";
 253                 reg = <0x0 0x03460000 0x0 0x10000>;
 254                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
 256                 clock-names = "sdhci";
 257                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
 258                 reset-names = "sdhci";
 259                 status = "disabled";
 260         };
 261
 262         gic: interrupt-controller@3881000 {
 263                 compatible = "arm,gic-400";
 264                 #interrupt-cells = <3>;
 265                 interrupt-controller;
 266                 reg = <0x0 0x03881000 0x0 0x1000>,
 267                       <0x0 0x03882000 0x0 0x2000>;
 268                 interrupts = <GIC_PPI 9
 269                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 270                 interrupt-parent = <&gic>;
 271         };
 272
 273         hsp_top0: hsp@3c00000 {
 274                 compatible = "nvidia,tegra186-hsp";
 275                 reg = <0x0 0x03c00000 0x0 0xa0000>;
 276                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 277                 interrupt-names = "doorbell";
 278                 #mbox-cells = <2>;
 279                 status = "disabled";
 280         };
 281
 282         gen2_i2c: i2c@c240000 {
 283                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 284                 reg = <0x0 0x0c240000 0x0 0x10000>;
 285                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 clocks = <&bpmp TEGRA186_CLK_I2C2>;
 289                 clock-names = "div-clk";
 290                 resets = <&bpmp TEGRA186_RESET_I2C2>;
 291                 reset-names = "i2c";
 292                 status = "disabled";
 293         };
 294
 295         gen8_i2c: i2c@c250000 {
 296                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c";
 297                 reg = <0x0 0x0c250000 0x0 0x10000>;
 298                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 clocks = <&bpmp TEGRA186_CLK_I2C8>;
 302                 clock-names = "div-clk";
 303                 resets = <&bpmp TEGRA186_RESET_I2C8>;
 304                 reset-names = "i2c";
 305                 status = "disabled";
 306         };
 307
 308         uartc: serial@c280000 {
 309                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 310                 reg = <0x0 0x0c280000 0x0 0x40>;
 311                 reg-shift = <2>;
 312                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&bpmp TEGRA186_CLK_UARTC>;
 314                 clock-names = "serial";
 315                 resets = <&bpmp TEGRA186_RESET_UARTC>;
 316                 reset-names = "serial";
 317                 status = "disabled";
 318         };
 319
 320         uartg: serial@c290000 {
 321                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 322                 reg = <0x0 0x0c290000 0x0 0x40>;
 323                 reg-shift = <2>;
 324                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 325                 clocks = <&bpmp TEGRA186_CLK_UARTG>;
 326                 clock-names = "serial";
 327                 resets = <&bpmp TEGRA186_RESET_UARTG>;
 328                 reset-names = "serial";
 329                 status = "disabled";
 330         };
 331
 332         gpio_aon: gpio@c2f0000 {
 333                 compatible = "nvidia,tegra186-gpio-aon";
 334                 reg-names = "security", "gpio";
 335                 reg = <0x0 0xc2f0000 0x0 0x1000>,
 336                       <0x0 0xc2f1000 0x0 0x1000>;
 337                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 338                 gpio-controller;
 339                 #gpio-cells = <2>;
 340                 interrupt-controller;
 341                 #interrupt-cells = <2>;
 342         };
 343
 344         pmc@c360000 {
 345                 compatible = "nvidia,tegra186-pmc";
 346                 reg = <0 0x0c360000 0 0x10000>,
 347                       <0 0x0c370000 0 0x10000>,
 348                       <0 0x0c380000 0 0x10000>,
 349                       <0 0x0c390000 0 0x10000>;
 350                 reg-names = "pmc", "wake", "aotag", "scratch";
 351         };
 352
 353         ccplex@e000000 {
 354                 compatible = "nvidia,tegra186-ccplex-cluster";
 355                 reg = <0x0 0x0e000000 0x0 0x3fffff>;
 356
 357                 nvidia,bpmp = <&bpmp>;
 358         };
 359
 360         pcie@10003000 {
 361                 compatible = "nvidia,tegra186-pcie";
 362                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
 363                 device_type = "pci";
 364                 reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
 365                        0x0 0x10003800 0x0 0x00000800   /* AFI registers */
 366                        0x0 0x40000000 0x0 0x10000000>; /* configuration space */
 367                 reg-names = "pads", "afi", "cs";
 368
 369                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 370                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 371                 interrupt-names = "intr", "msi";
 372
 373                 #interrupt-cells = <1>;
 374                 interrupt-map-mask = <0 0 0 0>;
 375                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 376
 377                 bus-range = <0x00 0xff>;
 378                 #address-cells = <3>;
 379                 #size-cells = <2>;
 380
 381                 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
 382                           0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
 383                           0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
 384                           0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
 385                           0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
 386                           0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
 387
 388                 clocks = <&bpmp TEGRA186_CLK_AFI>,
 389                          <&bpmp TEGRA186_CLK_PCIE>,
 390                          <&bpmp TEGRA186_CLK_PLLE>;
 391                 clock-names = "afi", "pex", "pll_e";
 392
 393                 resets = <&bpmp TEGRA186_RESET_AFI>,
 394                          <&bpmp TEGRA186_RESET_PCIE>,
 395                          <&bpmp TEGRA186_RESET_PCIEXCLK>;
 396                 reset-names = "afi", "pex", "pcie_x";
 397
 398                 status = "disabled";
 399
 400                 pci@1,0 {
 401                         device_type = "pci";
 402                         assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
 403                         reg = <0x000800 0 0 0 0>;
 404                         status = "disabled";
 405
 406                         #address-cells = <3>;
 407                         #size-cells = <2>;
 408                         ranges;
 409
 410                         nvidia,num-lanes = <2>;
 411                 };
 412
 413                 pci@2,0 {
 414                         device_type = "pci";
 415                         assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
 416                         reg = <0x001000 0 0 0 0>;
 417                         status = "disabled";
 418
 419                         #address-cells = <3>;
 420                         #size-cells = <2>;
 421                         ranges;
 422
 423                         nvidia,num-lanes = <1>;
 424                 };
 425
 426                 pci@3,0 {
 427                         device_type = "pci";
 428                         assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
 429                         reg = <0x001800 0 0 0 0>;
 430                         status = "disabled";
 431
 432                         #address-cells = <3>;
 433                         #size-cells = <2>;
 434                         ranges;
 435
 436                         nvidia,num-lanes = <1>;
 437                 };
 438         };
 439
 440         host1x@13e00000 {
 441                 compatible = "nvidia,tegra186-host1x", "simple-bus";
 442                 reg = <0x0 0x13e00000 0x0 0x10000>,
 443                       <0x0 0x13e10000 0x0 0x10000>;
 444                 reg-names = "hypervisor", "vm";
 445                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 446                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 447                 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
 448                 clock-names = "host1x";
 449                 resets = <&bpmp TEGRA186_RESET_HOST1X>;
 450                 reset-names = "host1x";
 451
 452                 #address-cells = <1>;
 453                 #size-cells = <1>;
 454
 455                 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
 456
 457                 vic@15340000 {
 458                         compatible = "nvidia,tegra186-vic";
 459                         reg = <0x15340000 0x40000>;
 460                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 461                         clocks = <&bpmp TEGRA186_CLK_VIC>;
 462                         clock-names = "vic";
 463                         resets = <&bpmp TEGRA186_RESET_VIC>;
 464                         reset-names = "vic";
 465
 466                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
 467                 };
 468         };
 469
 470         gpu@17000000 {
 471                 compatible = "nvidia,gp10b";
 472                 reg = <0x0 0x17000000 0x0 0x1000000>,
 473                       <0x0 0x18000000 0x0 0x1000000>;
 474                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
 475                               GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 476                 interrupt-names = "stall", "nonstall";
 477
 478                 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
 479                          <&bpmp TEGRA186_CLK_GPU>;
 480                 clock-names = "gpu", "pwr";
 481                 resets = <&bpmp TEGRA186_RESET_GPU>;
 482                 reset-names = "gpu";
 483                 status = "disabled";
 484
 485                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
 486         };
 487
 488         sysram@30000000 {
 489                 compatible = "nvidia,tegra186-sysram", "mmio-sram";
 490                 reg = <0x0 0x30000000 0x0 0x50000>;
 491                 #address-cells = <2>;
 492                 #size-cells = <2>;
 493                 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
 494
 495                 cpu_bpmp_tx: shmem@4e000 {
 496                         compatible = "nvidia,tegra186-bpmp-shmem";
 497                         reg = <0x0 0x4e000 0x0 0x1000>;
 498                         label = "cpu-bpmp-tx";
 499                         pool;
 500                 };
 501
 502                 cpu_bpmp_rx: shmem@4f000 {
 503                         compatible = "nvidia,tegra186-bpmp-shmem";
 504                         reg = <0x0 0x4f000 0x0 0x1000>;
 505                         label = "cpu-bpmp-rx";
 506                         pool;
 507                 };
 508         };
 509
 510         cpus {
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513
 514                 cpu@0 {
 515                         compatible = "nvidia,tegra186-denver", "arm,armv8";
 516                         device_type = "cpu";
 517                         reg = <0x000>;
 518                 };
 519
 520                 cpu@1 {
 521                         compatible = "nvidia,tegra186-denver", "arm,armv8";
 522                         device_type = "cpu";
 523                         reg = <0x001>;
 524                 };
 525
 526                 cpu@2 {
 527                         compatible = "arm,cortex-a57", "arm,armv8";
 528                         device_type = "cpu";
 529                         reg = <0x100>;
 530                 };
 531
 532                 cpu@3 {
 533                         compatible = "arm,cortex-a57", "arm,armv8";
 534                         device_type = "cpu";
 535                         reg = <0x101>;
 536                 };
 537
 538                 cpu@4 {
 539                         compatible = "arm,cortex-a57", "arm,armv8";
 540                         device_type = "cpu";
 541                         reg = <0x102>;
 542                 };
 543
 544                 cpu@5 {
 545                         compatible = "arm,cortex-a57", "arm,armv8";
 546                         device_type = "cpu";
 547                         reg = <0x103>;
 548                 };
 549         };
 550
 551         bpmp: bpmp {
 552                 compatible = "nvidia,tegra186-bpmp";
 553                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
 554                                     TEGRA_HSP_DB_MASTER_BPMP>;
 555                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
 556                 #clock-cells = <1>;
 557                 #reset-cells = <1>;
 558                 #power-domain-cells = <1>;
 559
 560                 bpmp_i2c: i2c {
 561                         compatible = "nvidia,tegra186-bpmp-i2c";
 562                         nvidia,bpmp-bus-id = <5>;
 563                         #address-cells = <1>;
 564                         #size-cells = <0>;
 565                         status = "disabled";
 566                 };
 567
 568                 bpmp_thermal: thermal {
 569                         compatible = "nvidia,tegra186-bpmp-thermal";
 570                         #thermal-sensor-cells = <1>;
 571                 };
 572         };
 573
 574         thermal-zones {
 575                 a57 {
 576                         polling-delay = <0>;
 577                         polling-delay-passive = <1000>;
 578
 579                         thermal-sensors =
 580                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
 581
 582                         trips {
 583                                 critical {
 584                                         temperature = <101000>;
 585                                         hysteresis = <0>;
 586                                         type = "critical";
 587                                 };
 588                         };
 589
 590                         cooling-maps {
 591                         };
 592                 };
 593
 594                 denver {
 595                         polling-delay = <0>;
 596                         polling-delay-passive = <1000>;
 597
 598                         thermal-sensors =
 599                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
 600
 601                         trips {
 602                                 critical {
 603                                         temperature = <101000>;
 604                                         hysteresis = <0>;
 605                                         type = "critical";
 606                                 };
 607                         };
 608
 609                         cooling-maps {
 610                         };
 611                 };
 612
 613                 gpu {
 614                         polling-delay = <0>;
 615                         polling-delay-passive = <1000>;
 616
 617                         thermal-sensors =
 618                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
 619
 620                         trips {
 621                                 critical {
 622                                         temperature = <101000>;
 623                                         hysteresis = <0>;
 624                                         type = "critical";
 625                                 };
 626                         };
 627
 628                         cooling-maps {
 629                         };
 630                 };
 631
 632                 pll {
 633                         polling-delay = <0>;
 634                         polling-delay-passive = <1000>;
 635
 636                         thermal-sensors =
 637                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
 638
 639                         trips {
 640                                 critical {
 641                                         temperature = <101000>;
 642                                         hysteresis = <0>;
 643                                         type = "critical";
 644                                 };
 645                         };
 646
 647                         cooling-maps {
 648                         };
 649                 };
 650
 651                 always_on {
 652                         polling-delay = <0>;
 653                         polling-delay-passive = <1000>;
 654
 655                         thermal-sensors =
 656                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
 657
 658                         trips {
 659                                 critical {
 660                                         temperature = <101000>;
 661                                         hysteresis = <0>;
 662                                         type = "critical";
 663                                 };
 664                         };
 665
 666                         cooling-maps {
 667                         };
 668                 };
 669         };
 670
 671         timer {
 672                 compatible = "arm,armv8-timer";
 673                 interrupts = <GIC_PPI 13
 674                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 675                              <GIC_PPI 14
 676                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 677                              <GIC_PPI 11
 678                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 679                              <GIC_PPI 10
 680                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 681                 interrupt-parent = <&gic>;
 682         };
 683 };