arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include <dt-bindings/gce/mt8173-gce.h>
  22 #include "mt8173-pinfunc.h"
  23
  24 / {
  25         compatible = "mediatek,mt8173";
  26         interrupt-parent = <&sysirq>;
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         aliases {
  31                 ovl0 = &ovl0;
  32                 ovl1 = &ovl1;
  33                 rdma0 = &rdma0;
  34                 rdma1 = &rdma1;
  35                 rdma2 = &rdma2;
  36                 wdma0 = &wdma0;
  37                 wdma1 = &wdma1;
  38                 color0 = &color0;
  39                 color1 = &color1;
  40                 split0 = &split0;
  41                 split1 = &split1;
  42                 dpi0 = &dpi0;
  43                 dsi0 = &dsi0;
  44                 dsi1 = &dsi1;
  45                 mdp_rdma0 = &mdp_rdma0;
  46                 mdp_rdma1 = &mdp_rdma1;
  47                 mdp_rsz0 = &mdp_rsz0;
  48                 mdp_rsz1 = &mdp_rsz1;
  49                 mdp_rsz2 = &mdp_rsz2;
  50                 mdp_wdma0 = &mdp_wdma0;
  51                 mdp_wrot0 = &mdp_wrot0;
  52                 mdp_wrot1 = &mdp_wrot1;
  53         };
  54
  55         cluster0_opp: opp_table0 {
  56                 compatible = "operating-points-v2";
  57                 opp-shared;
  58                 opp-507000000 {
  59                         opp-hz = /bits/ 64 <507000000>;
  60                         opp-microvolt = <859000>;
  61                 };
  62                 opp-702000000 {
  63                         opp-hz = /bits/ 64 <702000000>;
  64                         opp-microvolt = <908000>;
  65                 };
  66                 opp-1001000000 {
  67                         opp-hz = /bits/ 64 <1001000000>;
  68                         opp-microvolt = <983000>;
  69                 };
  70                 opp-1105000000 {
  71                         opp-hz = /bits/ 64 <1105000000>;
  72                         opp-microvolt = <1009000>;
  73                 };
  74                 opp-1209000000 {
  75                         opp-hz = /bits/ 64 <1209000000>;
  76                         opp-microvolt = <1034000>;
  77                 };
  78                 opp-1300000000 {
  79                         opp-hz = /bits/ 64 <1300000000>;
  80                         opp-microvolt = <1057000>;
  81                 };
  82                 opp-1508000000 {
  83                         opp-hz = /bits/ 64 <1508000000>;
  84                         opp-microvolt = <1109000>;
  85                 };
  86                 opp-1703000000 {
  87                         opp-hz = /bits/ 64 <1703000000>;
  88                         opp-microvolt = <1125000>;
  89                 };
  90         };
  91
  92         cluster1_opp: opp_table1 {
  93                 compatible = "operating-points-v2";
  94                 opp-shared;
  95                 opp-507000000 {
  96                         opp-hz = /bits/ 64 <507000000>;
  97                         opp-microvolt = <828000>;
  98                 };
  99                 opp-702000000 {
 100                         opp-hz = /bits/ 64 <702000000>;
 101                         opp-microvolt = <867000>;
 102                 };
 103                 opp-1001000000 {
 104                         opp-hz = /bits/ 64 <1001000000>;
 105                         opp-microvolt = <927000>;
 106                 };
 107                 opp-1209000000 {
 108                         opp-hz = /bits/ 64 <1209000000>;
 109                         opp-microvolt = <968000>;
 110                 };
 111                 opp-1404000000 {
 112                         opp-hz = /bits/ 64 <1404000000>;
 113                         opp-microvolt = <1007000>;
 114                 };
 115                 opp-1612000000 {
 116                         opp-hz = /bits/ 64 <1612000000>;
 117                         opp-microvolt = <1049000>;
 118                 };
 119                 opp-1807000000 {
 120                         opp-hz = /bits/ 64 <1807000000>;
 121                         opp-microvolt = <1089000>;
 122                 };
 123                 opp-2106000000 {
 124                         opp-hz = /bits/ 64 <2106000000>;
 125                         opp-microvolt = <1125000>;
 126                 };
 127         };
 128
 129         cpus {
 130                 #address-cells = <1>;
 131                 #size-cells = <0>;
 132
 133                 cpu-map {
 134                         cluster0 {
 135                                 core0 {
 136                                         cpu = <&cpu0>;
 137                                 };
 138                                 core1 {
 139                                         cpu = <&cpu1>;
 140                                 };
 141                         };
 142
 143                         cluster1 {
 144                                 core0 {
 145                                         cpu = <&cpu2>;
 146                                 };
 147                                 core1 {
 148                                         cpu = <&cpu3>;
 149                                 };
 150                         };
 151                 };
 152
 153                 cpu0: cpu@0 {
 154                         device_type = "cpu";
 155                         compatible = "arm,cortex-a53";
 156                         reg = <0x000>;
 157                         enable-method = "psci";
 158                         cpu-idle-states = <&CPU_SLEEP_0>;
 159                         #cooling-cells = <2>;
 160                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 161                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 162                         clock-names = "cpu", "intermediate";
 163                         operating-points-v2 = <&cluster0_opp>;
 164                 };
 165
 166                 cpu1: cpu@1 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53";
 169                         reg = <0x001>;
 170                         enable-method = "psci";
 171                         cpu-idle-states = <&CPU_SLEEP_0>;
 172                         #cooling-cells = <2>;
 173                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 174                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 175                         clock-names = "cpu", "intermediate";
 176                         operating-points-v2 = <&cluster0_opp>;
 177                 };
 178
 179                 cpu2: cpu@100 {
 180                         device_type = "cpu";
 181                         compatible = "arm,cortex-a57";
 182                         reg = <0x100>;
 183                         enable-method = "psci";
 184                         cpu-idle-states = <&CPU_SLEEP_0>;
 185                         #cooling-cells = <2>;
 186                         clocks = <&infracfg CLK_INFRA_CA57SEL>,
 187                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 188                         clock-names = "cpu", "intermediate";
 189                         operating-points-v2 = <&cluster1_opp>;
 190                 };
 191
 192                 cpu3: cpu@101 {
 193                         device_type = "cpu";
 194                         compatible = "arm,cortex-a57";
 195                         reg = <0x101>;
 196                         enable-method = "psci";
 197                         cpu-idle-states = <&CPU_SLEEP_0>;
 198                         #cooling-cells = <2>;
 199                         clocks = <&infracfg CLK_INFRA_CA57SEL>,
 200                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 201                         clock-names = "cpu", "intermediate";
 202                         operating-points-v2 = <&cluster1_opp>;
 203                 };
 204
 205                 idle-states {
 206                         entry-method = "psci";
 207
 208                         CPU_SLEEP_0: cpu-sleep-0 {
 209                                 compatible = "arm,idle-state";
 210                                 local-timer-stop;
 211                                 entry-latency-us = <639>;
 212                                 exit-latency-us = <680>;
 213                                 min-residency-us = <1088>;
 214                                 arm,psci-suspend-param = <0x0010000>;
 215                         };
 216                 };
 217         };
 218
 219         psci {
 220                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 221                 method = "smc";
 222                 cpu_suspend   = <0x84000001>;
 223                 cpu_off       = <0x84000002>;
 224                 cpu_on        = <0x84000003>;
 225         };
 226
 227         clk26m: oscillator@0 {
 228                 compatible = "fixed-clock";
 229                 #clock-cells = <0>;
 230                 clock-frequency = <26000000>;
 231                 clock-output-names = "clk26m";
 232         };
 233
 234         clk32k: oscillator@1 {
 235                 compatible = "fixed-clock";
 236                 #clock-cells = <0>;
 237                 clock-frequency = <32000>;
 238                 clock-output-names = "clk32k";
 239         };
 240
 241         cpum_ck: oscillator@2 {
 242                 compatible = "fixed-clock";
 243                 #clock-cells = <0>;
 244                 clock-frequency = <0>;
 245                 clock-output-names = "cpum_ck";
 246         };
 247
 248         thermal-zones {
 249                 cpu_thermal: cpu_thermal {
 250                         polling-delay-passive = <1000>; /* milliseconds */
 251                         polling-delay = <1000>; /* milliseconds */
 252
 253                         thermal-sensors = <&thermal>;
 254                         sustainable-power = <1500>; /* milliwatts */
 255
 256                         trips {
 257                                 threshold: trip-point@0 {
 258                                         temperature = <68000>;
 259                                         hysteresis = <2000>;
 260                                         type = "passive";
 261                                 };
 262
 263                                 target: trip-point@1 {
 264                                         temperature = <85000>;
 265                                         hysteresis = <2000>;
 266                                         type = "passive";
 267                                 };
 268
 269                                 cpu_crit: cpu_crit@0 {
 270                                         temperature = <115000>;
 271                                         hysteresis = <2000>;
 272                                         type = "critical";
 273                                 };
 274                         };
 275
 276                         cooling-maps {
 277                                 map@0 {
 278                                         trip = <&target>;
 279                                         cooling-device = <&cpu0 0 0>,
 280                                                          <&cpu1 0 0>;
 281                                         contribution = <3072>;
 282                                 };
 283                                 map@1 {
 284                                         trip = <&target>;
 285                                         cooling-device = <&cpu2 0 0>,
 286                                                          <&cpu3 0 0>;
 287                                         contribution = <1024>;
 288                                 };
 289                         };
 290                 };
 291         };
 292
 293         reserved-memory {
 294                 #address-cells = <2>;
 295                 #size-cells = <2>;
 296                 ranges;
 297                 vpu_dma_reserved: vpu_dma_mem_region {
 298                         compatible = "shared-dma-pool";
 299                         reg = <0 0xb7000000 0 0x500000>;
 300                         alignment = <0x1000>;
 301                         no-map;
 302                 };
 303         };
 304
 305         timer {
 306                 compatible = "arm,armv8-timer";
 307                 interrupt-parent = <&gic>;
 308                 interrupts = <GIC_PPI 13
 309                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 310                              <GIC_PPI 14
 311                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 312                              <GIC_PPI 11
 313                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 314                              <GIC_PPI 10
 315                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 316         };
 317
 318         soc {
 319                 #address-cells = <2>;
 320                 #size-cells = <2>;
 321                 compatible = "simple-bus";
 322                 ranges;
 323
 324                 topckgen: clock-controller@10000000 {
 325                         compatible = "mediatek,mt8173-topckgen";
 326                         reg = <0 0x10000000 0 0x1000>;
 327                         #clock-cells = <1>;
 328                 };
 329
 330                 infracfg: power-controller@10001000 {
 331                         compatible = "mediatek,mt8173-infracfg", "syscon";
 332                         reg = <0 0x10001000 0 0x1000>;
 333                         #clock-cells = <1>;
 334                         #reset-cells = <1>;
 335                 };
 336
 337                 pericfg: power-controller@10003000 {
 338                         compatible = "mediatek,mt8173-pericfg", "syscon";
 339                         reg = <0 0x10003000 0 0x1000>;
 340                         #clock-cells = <1>;
 341                         #reset-cells = <1>;
 342                 };
 343
 344                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 345                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 346                         reg = <0 0x10005000 0 0x1000>;
 347                 };
 348
 349                 pio: pinctrl@10005000 {
 350                         compatible = "mediatek,mt8173-pinctrl";
 351                         reg = <0 0x1000b000 0 0x1000>;
 352                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 353                         pins-are-numbered;
 354                         gpio-controller;
 355                         #gpio-cells = <2>;
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 359                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 360                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 361
 362                         hdmi_pin: xxx {
 363
 364                                 /*hdmi htplg pin*/
 365                                 pins1 {
 366                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 367                                         input-enable;
 368                                         bias-pull-down;
 369                                 };
 370                         };
 371
 372                         i2c0_pins_a: i2c0 {
 373                                 pins1 {
 374                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 375                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 376                                         bias-disable;
 377                                 };
 378                         };
 379
 380                         i2c1_pins_a: i2c1 {
 381                                 pins1 {
 382                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 383                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 384                                         bias-disable;
 385                                 };
 386                         };
 387
 388                         i2c2_pins_a: i2c2 {
 389                                 pins1 {
 390                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 391                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 392                                         bias-disable;
 393                                 };
 394                         };
 395
 396                         i2c3_pins_a: i2c3 {
 397                                 pins1 {
 398                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 399                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 400                                         bias-disable;
 401                                 };
 402                         };
 403
 404                         i2c4_pins_a: i2c4 {
 405                                 pins1 {
 406                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 407                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 408                                         bias-disable;
 409                                 };
 410                         };
 411
 412                         i2c6_pins_a: i2c6 {
 413                                 pins1 {
 414                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 415                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 416                                         bias-disable;
 417                                 };
 418                         };
 419                 };
 420
 421                 scpsys: scpsys@10006000 {
 422                         compatible = "mediatek,mt8173-scpsys";
 423                         #power-domain-cells = <1>;
 424                         reg = <0 0x10006000 0 0x1000>;
 425                         clocks = <&clk26m>,
 426                                  <&topckgen CLK_TOP_MM_SEL>,
 427                                  <&topckgen CLK_TOP_VENC_SEL>,
 428                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 429                         clock-names = "mfg", "mm", "venc", "venc_lt";
 430                         infracfg = <&infracfg>;
 431                 };
 432
 433                 watchdog: watchdog@10007000 {
 434                         compatible = "mediatek,mt8173-wdt",
 435                                      "mediatek,mt6589-wdt";
 436                         reg = <0 0x10007000 0 0x100>;
 437                 };
 438
 439                 timer: timer@10008000 {
 440                         compatible = "mediatek,mt8173-timer",
 441                                      "mediatek,mt6577-timer";
 442                         reg = <0 0x10008000 0 0x1000>;
 443                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 444                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 445                                  <&topckgen CLK_TOP_RTC_SEL>;
 446                 };
 447
 448                 pwrap: pwrap@1000d000 {
 449                         compatible = "mediatek,mt8173-pwrap";
 450                         reg = <0 0x1000d000 0 0x1000>;
 451                         reg-names = "pwrap";
 452                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 453                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 454                         reset-names = "pwrap";
 455                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 456                         clock-names = "spi", "wrap";
 457                 };
 458
 459                 cec: cec@10013000 {
 460                         compatible = "mediatek,mt8173-cec";
 461                         reg = <0 0x10013000 0 0xbc>;
 462                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 463                         clocks = <&infracfg CLK_INFRA_CEC>;
 464                         status = "disabled";
 465                 };
 466
 467                 vpu: vpu@10020000 {
 468                         compatible = "mediatek,mt8173-vpu";
 469                         reg = <0 0x10020000 0 0x30000>,
 470                               <0 0x10050000 0 0x100>;
 471                         reg-names = "tcm", "cfg_reg";
 472                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 474                         clock-names = "main";
 475                         memory-region = <&vpu_dma_reserved>;
 476                 };
 477
 478                 sysirq: intpol-controller@10200620 {
 479                         compatible = "mediatek,mt8173-sysirq",
 480                                      "mediatek,mt6577-sysirq";
 481                         interrupt-controller;
 482                         #interrupt-cells = <3>;
 483                         interrupt-parent = <&gic>;
 484                         reg = <0 0x10200620 0 0x20>;
 485                 };
 486
 487                 iommu: iommu@10205000 {
 488                         compatible = "mediatek,mt8173-m4u";
 489                         reg = <0 0x10205000 0 0x1000>;
 490                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 491                         clocks = <&infracfg CLK_INFRA_M4U>;
 492                         clock-names = "bclk";
 493                         mediatek,larbs = <&larb0 &larb1 &larb2
 494                                           &larb3 &larb4 &larb5>;
 495                         #iommu-cells = <1>;
 496                 };
 497
 498                 efuse: efuse@10206000 {
 499                         compatible = "mediatek,mt8173-efuse";
 500                         reg = <0 0x10206000 0 0x1000>;
 501                         #address-cells = <1>;
 502                         #size-cells = <1>;
 503                         thermal_calibration: calib@528 {
 504                                 reg = <0x528 0xc>;
 505                         };
 506                 };
 507
 508                 apmixedsys: clock-controller@10209000 {
 509                         compatible = "mediatek,mt8173-apmixedsys";
 510                         reg = <0 0x10209000 0 0x1000>;
 511                         #clock-cells = <1>;
 512                 };
 513
 514                 hdmi_phy: hdmi-phy@10209100 {
 515                         compatible = "mediatek,mt8173-hdmi-phy";
 516                         reg = <0 0x10209100 0 0x24>;
 517                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 518                         clock-names = "pll_ref";
 519                         clock-output-names = "hdmitx_dig_cts";
 520                         mediatek,ibias = <0xa>;
 521                         mediatek,ibias_up = <0x1c>;
 522                         #clock-cells = <0>;
 523                         #phy-cells = <0>;
 524                         status = "disabled";
 525                 };
 526
 527                 gce: mailbox@10212000 {
 528                         compatible = "mediatek,mt8173-gce";
 529                         reg = <0 0x10212000 0 0x1000>;
 530                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
 531                         clocks = <&infracfg CLK_INFRA_GCE>;
 532                         clock-names = "gce";
 533                         #mbox-cells = <3>;
 534                 };
 535
 536                 mipi_tx0: mipi-dphy@10215000 {
 537                         compatible = "mediatek,mt8173-mipi-tx";
 538                         reg = <0 0x10215000 0 0x1000>;
 539                         clocks = <&clk26m>;
 540                         clock-output-names = "mipi_tx0_pll";
 541                         #clock-cells = <0>;
 542                         #phy-cells = <0>;
 543                         status = "disabled";
 544                 };
 545
 546                 mipi_tx1: mipi-dphy@10216000 {
 547                         compatible = "mediatek,mt8173-mipi-tx";
 548                         reg = <0 0x10216000 0 0x1000>;
 549                         clocks = <&clk26m>;
 550                         clock-output-names = "mipi_tx1_pll";
 551                         #clock-cells = <0>;
 552                         #phy-cells = <0>;
 553                         status = "disabled";
 554                 };
 555
 556                 gic: interrupt-controller@10220000 {
 557                         compatible = "arm,gic-400";
 558                         #interrupt-cells = <3>;
 559                         interrupt-parent = <&gic>;
 560                         interrupt-controller;
 561                         reg = <0 0x10221000 0 0x1000>,
 562                               <0 0x10222000 0 0x2000>,
 563                               <0 0x10224000 0 0x2000>,
 564                               <0 0x10226000 0 0x2000>;
 565                         interrupts = <GIC_PPI 9
 566                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 567                 };
 568
 569                 auxadc: auxadc@11001000 {
 570                         compatible = "mediatek,mt8173-auxadc";
 571                         reg = <0 0x11001000 0 0x1000>;
 572                         clocks = <&pericfg CLK_PERI_AUXADC>;
 573                         clock-names = "main";
 574                         #io-channel-cells = <1>;
 575                 };
 576
 577                 uart0: serial@11002000 {
 578                         compatible = "mediatek,mt8173-uart",
 579                                      "mediatek,mt6577-uart";
 580                         reg = <0 0x11002000 0 0x400>;
 581                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 582                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 583                         clock-names = "baud", "bus";
 584                         status = "disabled";
 585                 };
 586
 587                 uart1: serial@11003000 {
 588                         compatible = "mediatek,mt8173-uart",
 589                                      "mediatek,mt6577-uart";
 590                         reg = <0 0x11003000 0 0x400>;
 591                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 592                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 593                         clock-names = "baud", "bus";
 594                         status = "disabled";
 595                 };
 596
 597                 uart2: serial@11004000 {
 598                         compatible = "mediatek,mt8173-uart",
 599                                      "mediatek,mt6577-uart";
 600                         reg = <0 0x11004000 0 0x400>;
 601                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 602                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 603                         clock-names = "baud", "bus";
 604                         status = "disabled";
 605                 };
 606
 607                 uart3: serial@11005000 {
 608                         compatible = "mediatek,mt8173-uart",
 609                                      "mediatek,mt6577-uart";
 610                         reg = <0 0x11005000 0 0x400>;
 611                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 612                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 613                         clock-names = "baud", "bus";
 614                         status = "disabled";
 615                 };
 616
 617                 i2c0: i2c@11007000 {
 618                         compatible = "mediatek,mt8173-i2c";
 619                         reg = <0 0x11007000 0 0x70>,
 620                               <0 0x11000100 0 0x80>;
 621                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 622                         clock-div = <16>;
 623                         clocks = <&pericfg CLK_PERI_I2C0>,
 624                                  <&pericfg CLK_PERI_AP_DMA>;
 625                         clock-names = "main", "dma";
 626                         pinctrl-names = "default";
 627                         pinctrl-0 = <&i2c0_pins_a>;
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630                         status = "disabled";
 631                 };
 632
 633                 i2c1: i2c@11008000 {
 634                         compatible = "mediatek,mt8173-i2c";
 635                         reg = <0 0x11008000 0 0x70>,
 636                               <0 0x11000180 0 0x80>;
 637                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 638                         clock-div = <16>;
 639                         clocks = <&pericfg CLK_PERI_I2C1>,
 640                                  <&pericfg CLK_PERI_AP_DMA>;
 641                         clock-names = "main", "dma";
 642                         pinctrl-names = "default";
 643                         pinctrl-0 = <&i2c1_pins_a>;
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         status = "disabled";
 647                 };
 648
 649                 i2c2: i2c@11009000 {
 650                         compatible = "mediatek,mt8173-i2c";
 651                         reg = <0 0x11009000 0 0x70>,
 652                               <0 0x11000200 0 0x80>;
 653                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 654                         clock-div = <16>;
 655                         clocks = <&pericfg CLK_PERI_I2C2>,
 656                                  <&pericfg CLK_PERI_AP_DMA>;
 657                         clock-names = "main", "dma";
 658                         pinctrl-names = "default";
 659                         pinctrl-0 = <&i2c2_pins_a>;
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         status = "disabled";
 663                 };
 664
 665                 spi: spi@1100a000 {
 666                         compatible = "mediatek,mt8173-spi";
 667                         #address-cells = <1>;
 668                         #size-cells = <0>;
 669                         reg = <0 0x1100a000 0 0x1000>;
 670                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 671                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 672                                  <&topckgen CLK_TOP_SPI_SEL>,
 673                                  <&pericfg CLK_PERI_SPI0>;
 674                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 675                         status = "disabled";
 676                 };
 677
 678                 thermal: thermal@1100b000 {
 679                         #thermal-sensor-cells = <0>;
 680                         compatible = "mediatek,mt8173-thermal";
 681                         reg = <0 0x1100b000 0 0x1000>;
 682                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 683                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 684                         clock-names = "therm", "auxadc";
 685                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 686                         mediatek,auxadc = <&auxadc>;
 687                         mediatek,apmixedsys = <&apmixedsys>;
 688                         nvmem-cells = <&thermal_calibration>;
 689                         nvmem-cell-names = "calibration-data";
 690                 };
 691
 692                 nor_flash: spi@1100d000 {
 693                         compatible = "mediatek,mt8173-nor";
 694                         reg = <0 0x1100d000 0 0xe0>;
 695                         clocks = <&pericfg CLK_PERI_SPI>,
 696                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 697                         clock-names = "spi", "sf";
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                         status = "disabled";
 701                 };
 702
 703                 i2c3: i2c@11010000 {
 704                         compatible = "mediatek,mt8173-i2c";
 705                         reg = <0 0x11010000 0 0x70>,
 706                               <0 0x11000280 0 0x80>;
 707                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 708                         clock-div = <16>;
 709                         clocks = <&pericfg CLK_PERI_I2C3>,
 710                                  <&pericfg CLK_PERI_AP_DMA>;
 711                         clock-names = "main", "dma";
 712                         pinctrl-names = "default";
 713                         pinctrl-0 = <&i2c3_pins_a>;
 714                         #address-cells = <1>;
 715                         #size-cells = <0>;
 716                         status = "disabled";
 717                 };
 718
 719                 i2c4: i2c@11011000 {
 720                         compatible = "mediatek,mt8173-i2c";
 721                         reg = <0 0x11011000 0 0x70>,
 722                               <0 0x11000300 0 0x80>;
 723                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 724                         clock-div = <16>;
 725                         clocks = <&pericfg CLK_PERI_I2C4>,
 726                                  <&pericfg CLK_PERI_AP_DMA>;
 727                         clock-names = "main", "dma";
 728                         pinctrl-names = "default";
 729                         pinctrl-0 = <&i2c4_pins_a>;
 730                         #address-cells = <1>;
 731                         #size-cells = <0>;
 732                         status = "disabled";
 733                 };
 734
 735                 hdmiddc0: i2c@11012000 {
 736                         compatible = "mediatek,mt8173-hdmi-ddc";
 737                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 738                         reg = <0 0x11012000 0 0x1C>;
 739                         clocks = <&pericfg CLK_PERI_I2C5>;
 740                         clock-names = "ddc-i2c";
 741                 };
 742
 743                 i2c6: i2c@11013000 {
 744                         compatible = "mediatek,mt8173-i2c";
 745                         reg = <0 0x11013000 0 0x70>,
 746                               <0 0x11000080 0 0x80>;
 747                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 748                         clock-div = <16>;
 749                         clocks = <&pericfg CLK_PERI_I2C6>,
 750                                  <&pericfg CLK_PERI_AP_DMA>;
 751                         clock-names = "main", "dma";
 752                         pinctrl-names = "default";
 753                         pinctrl-0 = <&i2c6_pins_a>;
 754                         #address-cells = <1>;
 755                         #size-cells = <0>;
 756                         status = "disabled";
 757                 };
 758
 759                 afe: audio-controller@11220000  {
 760                         compatible = "mediatek,mt8173-afe-pcm";
 761                         reg = <0 0x11220000 0 0x1000>;
 762                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 763                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 764                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 765                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 766                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 767                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 768                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 769                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 770                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 771                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 772                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 773                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 774                         clock-names = "infra_sys_audio_clk",
 775                                       "top_pdn_audio",
 776                                       "top_pdn_aud_intbus",
 777                                       "bck0",
 778                                       "bck1",
 779                                       "i2s0_m",
 780                                       "i2s1_m",
 781                                       "i2s2_m",
 782                                       "i2s3_m",
 783                                       "i2s3_b";
 784                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 785                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 786                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 787                                                  <&topckgen CLK_TOP_APLL2>;
 788                 };
 789
 790                 mmc0: mmc@11230000 {
 791                         compatible = "mediatek,mt8173-mmc";
 792                         reg = <0 0x11230000 0 0x1000>;
 793                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 794                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 795                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 796                         clock-names = "source", "hclk";
 797                         status = "disabled";
 798                 };
 799
 800                 mmc1: mmc@11240000 {
 801                         compatible = "mediatek,mt8173-mmc";
 802                         reg = <0 0x11240000 0 0x1000>;
 803                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 804                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 805                                  <&topckgen CLK_TOP_AXI_SEL>;
 806                         clock-names = "source", "hclk";
 807                         status = "disabled";
 808                 };
 809
 810                 mmc2: mmc@11250000 {
 811                         compatible = "mediatek,mt8173-mmc";
 812                         reg = <0 0x11250000 0 0x1000>;
 813                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 814                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 815                                  <&topckgen CLK_TOP_AXI_SEL>;
 816                         clock-names = "source", "hclk";
 817                         status = "disabled";
 818                 };
 819
 820                 mmc3: mmc@11260000 {
 821                         compatible = "mediatek,mt8173-mmc";
 822                         reg = <0 0x11260000 0 0x1000>;
 823                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 824                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 825                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 826                         clock-names = "source", "hclk";
 827                         status = "disabled";
 828                 };
 829
 830                 ssusb: usb@11271000 {
 831                         compatible = "mediatek,mt8173-mtu3";
 832                         reg = <0 0x11271000 0 0x3000>,
 833                               <0 0x11280700 0 0x0100>;
 834                         reg-names = "mac", "ippc";
 835                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 836                         phys = <&u2port0 PHY_TYPE_USB2>,
 837                                <&u3port0 PHY_TYPE_USB3>,
 838                                <&u2port1 PHY_TYPE_USB2>;
 839                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 840                         clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 841                         clock-names = "sys_ck", "ref_ck";
 842                         mediatek,syscon-wakeup = <&pericfg 0x400 1>;
 843                         #address-cells = <2>;
 844                         #size-cells = <2>;
 845                         ranges;
 846                         status = "disabled";
 847
 848                         usb_host: xhci@11270000 {
 849                                 compatible = "mediatek,mt8173-xhci";
 850                                 reg = <0 0x11270000 0 0x1000>;
 851                                 reg-names = "mac";
 852                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 853                                 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 854                                 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 855                                 clock-names = "sys_ck", "ref_ck";
 856                                 status = "disabled";
 857                         };
 858                 };
 859
 860                 u3phy: usb-phy@11290000 {
 861                         compatible = "mediatek,mt8173-u3phy";
 862                         reg = <0 0x11290000 0 0x800>;
 863                         #address-cells = <2>;
 864                         #size-cells = <2>;
 865                         ranges;
 866                         status = "okay";
 867
 868                         u2port0: usb-phy@11290800 {
 869                                 reg = <0 0x11290800 0 0x100>;
 870                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 871                                 clock-names = "ref";
 872                                 #phy-cells = <1>;
 873                                 status = "okay";
 874                         };
 875
 876                         u3port0: usb-phy@11290900 {
 877                                 reg = <0 0x11290900 0 0x700>;
 878                                 clocks = <&clk26m>;
 879                                 clock-names = "ref";
 880                                 #phy-cells = <1>;
 881                                 status = "okay";
 882                         };
 883
 884                         u2port1: usb-phy@11291000 {
 885                                 reg = <0 0x11291000 0 0x100>;
 886                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 887                                 clock-names = "ref";
 888                                 #phy-cells = <1>;
 889                                 status = "okay";
 890                         };
 891                 };
 892
 893                 mmsys: clock-controller@14000000 {
 894                         compatible = "mediatek,mt8173-mmsys", "syscon";
 895                         reg = <0 0x14000000 0 0x1000>;
 896                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 897                         assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
 898                         assigned-clock-rates = <400000000>;
 899                         #clock-cells = <1>;
 900                 };
 901
 902                 mdp_rdma0: rdma@14001000 {
 903                         compatible = "mediatek,mt8173-mdp-rdma",
 904                                      "mediatek,mt8173-mdp";
 905                         reg = <0 0x14001000 0 0x1000>;
 906                         clocks = <&mmsys CLK_MM_MDP_RDMA0>,
 907                                  <&mmsys CLK_MM_MUTEX_32K>;
 908                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 909                         iommus = <&iommu M4U_PORT_MDP_RDMA0>;
 910                         mediatek,larb = <&larb0>;
 911                         mediatek,vpu = <&vpu>;
 912                 };
 913
 914                 mdp_rdma1: rdma@14002000 {
 915                         compatible = "mediatek,mt8173-mdp-rdma";
 916                         reg = <0 0x14002000 0 0x1000>;
 917                         clocks = <&mmsys CLK_MM_MDP_RDMA1>,
 918                                  <&mmsys CLK_MM_MUTEX_32K>;
 919                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 920                         iommus = <&iommu M4U_PORT_MDP_RDMA1>;
 921                         mediatek,larb = <&larb4>;
 922                 };
 923
 924                 mdp_rsz0: rsz@14003000 {
 925                         compatible = "mediatek,mt8173-mdp-rsz";
 926                         reg = <0 0x14003000 0 0x1000>;
 927                         clocks = <&mmsys CLK_MM_MDP_RSZ0>;
 928                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 929                 };
 930
 931                 mdp_rsz1: rsz@14004000 {
 932                         compatible = "mediatek,mt8173-mdp-rsz";
 933                         reg = <0 0x14004000 0 0x1000>;
 934                         clocks = <&mmsys CLK_MM_MDP_RSZ1>;
 935                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 936                 };
 937
 938                 mdp_rsz2: rsz@14005000 {
 939                         compatible = "mediatek,mt8173-mdp-rsz";
 940                         reg = <0 0x14005000 0 0x1000>;
 941                         clocks = <&mmsys CLK_MM_MDP_RSZ2>;
 942                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 943                 };
 944
 945                 mdp_wdma0: wdma@14006000 {
 946                         compatible = "mediatek,mt8173-mdp-wdma";
 947                         reg = <0 0x14006000 0 0x1000>;
 948                         clocks = <&mmsys CLK_MM_MDP_WDMA>;
 949                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 950                         iommus = <&iommu M4U_PORT_MDP_WDMA>;
 951                         mediatek,larb = <&larb0>;
 952                 };
 953
 954                 mdp_wrot0: wrot@14007000 {
 955                         compatible = "mediatek,mt8173-mdp-wrot";
 956                         reg = <0 0x14007000 0 0x1000>;
 957                         clocks = <&mmsys CLK_MM_MDP_WROT0>;
 958                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 959                         iommus = <&iommu M4U_PORT_MDP_WROT0>;
 960                         mediatek,larb = <&larb0>;
 961                 };
 962
 963                 mdp_wrot1: wrot@14008000 {
 964                         compatible = "mediatek,mt8173-mdp-wrot";
 965                         reg = <0 0x14008000 0 0x1000>;
 966                         clocks = <&mmsys CLK_MM_MDP_WROT1>;
 967                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 968                         iommus = <&iommu M4U_PORT_MDP_WROT1>;
 969                         mediatek,larb = <&larb4>;
 970                 };
 971
 972                 ovl0: ovl@1400c000 {
 973                         compatible = "mediatek,mt8173-disp-ovl";
 974                         reg = <0 0x1400c000 0 0x1000>;
 975                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
 976                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 977                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
 978                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
 979                         mediatek,larb = <&larb0>;
 980                 };
 981
 982                 ovl1: ovl@1400d000 {
 983                         compatible = "mediatek,mt8173-disp-ovl";
 984                         reg = <0 0x1400d000 0 0x1000>;
 985                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
 986                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 987                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
 988                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
 989                         mediatek,larb = <&larb4>;
 990                 };
 991
 992                 rdma0: rdma@1400e000 {
 993                         compatible = "mediatek,mt8173-disp-rdma";
 994                         reg = <0 0x1400e000 0 0x1000>;
 995                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
 996                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 997                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 998                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
 999                         mediatek,larb = <&larb0>;
1000                 };
1001
1002                 rdma1: rdma@1400f000 {
1003                         compatible = "mediatek,mt8173-disp-rdma";
1004                         reg = <0 0x1400f000 0 0x1000>;
1005                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
1006                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1007                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
1008                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
1009                         mediatek,larb = <&larb4>;
1010                 };
1011
1012                 rdma2: rdma@14010000 {
1013                         compatible = "mediatek,mt8173-disp-rdma";
1014                         reg = <0 0x14010000 0 0x1000>;
1015                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1016                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1017                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1018                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1019                         mediatek,larb = <&larb4>;
1020                 };
1021
1022                 wdma0: wdma@14011000 {
1023                         compatible = "mediatek,mt8173-disp-wdma";
1024                         reg = <0 0x14011000 0 0x1000>;
1025                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1026                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1027                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1028                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1029                         mediatek,larb = <&larb0>;
1030                 };
1031
1032                 wdma1: wdma@14012000 {
1033                         compatible = "mediatek,mt8173-disp-wdma";
1034                         reg = <0 0x14012000 0 0x1000>;
1035                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1036                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1037                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1038                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1039                         mediatek,larb = <&larb4>;
1040                 };
1041
1042                 color0: color@14013000 {
1043                         compatible = "mediatek,mt8173-disp-color";
1044                         reg = <0 0x14013000 0 0x1000>;
1045                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1046                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1047                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1048                 };
1049
1050                 color1: color@14014000 {
1051                         compatible = "mediatek,mt8173-disp-color";
1052                         reg = <0 0x14014000 0 0x1000>;
1053                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1054                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1055                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1056                 };
1057
1058                 aal@14015000 {
1059                         compatible = "mediatek,mt8173-disp-aal";
1060                         reg = <0 0x14015000 0 0x1000>;
1061                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1062                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1063                         clocks = <&mmsys CLK_MM_DISP_AAL>;
1064                 };
1065
1066                 gamma@14016000 {
1067                         compatible = "mediatek,mt8173-disp-gamma";
1068                         reg = <0 0x14016000 0 0x1000>;
1069                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1070                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1071                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1072                 };
1073
1074                 merge@14017000 {
1075                         compatible = "mediatek,mt8173-disp-merge";
1076                         reg = <0 0x14017000 0 0x1000>;
1077                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1078                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
1079                 };
1080
1081                 split0: split@14018000 {
1082                         compatible = "mediatek,mt8173-disp-split";
1083                         reg = <0 0x14018000 0 0x1000>;
1084                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1085                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1086                 };
1087
1088                 split1: split@14019000 {
1089                         compatible = "mediatek,mt8173-disp-split";
1090                         reg = <0 0x14019000 0 0x1000>;
1091                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1092                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1093                 };
1094
1095                 ufoe@1401a000 {
1096                         compatible = "mediatek,mt8173-disp-ufoe";
1097                         reg = <0 0x1401a000 0 0x1000>;
1098                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1099                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1100                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
1101                 };
1102
1103                 dsi0: dsi@1401b000 {
1104                         compatible = "mediatek,mt8173-dsi";
1105                         reg = <0 0x1401b000 0 0x1000>;
1106                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1107                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1108                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1109                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
1110                                  <&mipi_tx0>;
1111                         clock-names = "engine", "digital", "hs";
1112                         phys = <&mipi_tx0>;
1113                         phy-names = "dphy";
1114                         status = "disabled";
1115                 };
1116
1117                 dsi1: dsi@1401c000 {
1118                         compatible = "mediatek,mt8173-dsi";
1119                         reg = <0 0x1401c000 0 0x1000>;
1120                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1121                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1122                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1123                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
1124                                  <&mipi_tx1>;
1125                         clock-names = "engine", "digital", "hs";
1126                         phy = <&mipi_tx1>;
1127                         phy-names = "dphy";
1128                         status = "disabled";
1129                 };
1130
1131                 dpi0: dpi@1401d000 {
1132                         compatible = "mediatek,mt8173-dpi";
1133                         reg = <0 0x1401d000 0 0x1000>;
1134                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1135                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1136                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1137                                  <&mmsys CLK_MM_DPI_ENGINE>,
1138                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1139                         clock-names = "pixel", "engine", "pll";
1140                         status = "disabled";
1141
1142                         port {
1143                                 dpi0_out: endpoint {
1144                                         remote-endpoint = <&hdmi0_in>;
1145                                 };
1146                         };
1147                 };
1148
1149                 pwm0: pwm@1401e000 {
1150                         compatible = "mediatek,mt8173-disp-pwm",
1151                                      "mediatek,mt6595-disp-pwm";
1152                         reg = <0 0x1401e000 0 0x1000>;
1153                         #pwm-cells = <2>;
1154                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1155                                  <&mmsys CLK_MM_DISP_PWM0MM>;
1156                         clock-names = "main", "mm";
1157                         status = "disabled";
1158                 };
1159
1160                 pwm1: pwm@1401f000 {
1161                         compatible = "mediatek,mt8173-disp-pwm",
1162                                      "mediatek,mt6595-disp-pwm";
1163                         reg = <0 0x1401f000 0 0x1000>;
1164                         #pwm-cells = <2>;
1165                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1166                                  <&mmsys CLK_MM_DISP_PWM1MM>;
1167                         clock-names = "main", "mm";
1168                         status = "disabled";
1169                 };
1170
1171                 mutex: mutex@14020000 {
1172                         compatible = "mediatek,mt8173-disp-mutex";
1173                         reg = <0 0x14020000 0 0x1000>;
1174                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1175                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1176                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
1177                 };
1178
1179                 larb0: larb@14021000 {
1180                         compatible = "mediatek,mt8173-smi-larb";
1181                         reg = <0 0x14021000 0 0x1000>;
1182                         mediatek,smi = <&smi_common>;
1183                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1184                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1185                                  <&mmsys CLK_MM_SMI_LARB0>;
1186                         clock-names = "apb", "smi";
1187                 };
1188
1189                 smi_common: smi@14022000 {
1190                         compatible = "mediatek,mt8173-smi-common";
1191                         reg = <0 0x14022000 0 0x1000>;
1192                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1193                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1194                                  <&mmsys CLK_MM_SMI_COMMON>;
1195                         clock-names = "apb", "smi";
1196                 };
1197
1198                 od@14023000 {
1199                         compatible = "mediatek,mt8173-disp-od";
1200                         reg = <0 0x14023000 0 0x1000>;
1201                         clocks = <&mmsys CLK_MM_DISP_OD>;
1202                 };
1203
1204                 hdmi0: hdmi@14025000 {
1205                         compatible = "mediatek,mt8173-hdmi";
1206                         reg = <0 0x14025000 0 0x400>;
1207                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1208                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1209                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1210                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1211                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1212                         clock-names = "pixel", "pll", "bclk", "spdif";
1213                         pinctrl-names = "default";
1214                         pinctrl-0 = <&hdmi_pin>;
1215                         phys = <&hdmi_phy>;
1216                         phy-names = "hdmi";
1217                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1218                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1219                         assigned-clock-parents = <&hdmi_phy>;
1220                         status = "disabled";
1221
1222                         ports {
1223                                 #address-cells = <1>;
1224                                 #size-cells = <0>;
1225
1226                                 port@0 {
1227                                         reg = <0>;
1228
1229                                         hdmi0_in: endpoint {
1230                                                 remote-endpoint = <&dpi0_out>;
1231                                         };
1232                                 };
1233                         };
1234                 };
1235
1236                 larb4: larb@14027000 {
1237                         compatible = "mediatek,mt8173-smi-larb";
1238                         reg = <0 0x14027000 0 0x1000>;
1239                         mediatek,smi = <&smi_common>;
1240                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1241                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1242                                  <&mmsys CLK_MM_SMI_LARB4>;
1243                         clock-names = "apb", "smi";
1244                 };
1245
1246                 imgsys: clock-controller@15000000 {
1247                         compatible = "mediatek,mt8173-imgsys", "syscon";
1248                         reg = <0 0x15000000 0 0x1000>;
1249                         #clock-cells = <1>;
1250                 };
1251
1252                 larb2: larb@15001000 {
1253                         compatible = "mediatek,mt8173-smi-larb";
1254                         reg = <0 0x15001000 0 0x1000>;
1255                         mediatek,smi = <&smi_common>;
1256                         power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1257                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1258                                  <&imgsys CLK_IMG_LARB2_SMI>;
1259                         clock-names = "apb", "smi";
1260                 };
1261
1262                 vdecsys: clock-controller@16000000 {
1263                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1264                         reg = <0 0x16000000 0 0x1000>;
1265                         #clock-cells = <1>;
1266                 };
1267
1268                 vcodec_dec: vcodec@16000000 {
1269                         compatible = "mediatek,mt8173-vcodec-dec";
1270                         reg = <0 0x16000000 0 0x100>,   /* VDEC_SYS */
1271                               <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
1272                               <0 0x16021000 0 0x800>,   /* VDEC_LD */
1273                               <0 0x16021800 0 0x800>,   /* VDEC_TOP */
1274                               <0 0x16022000 0 0x1000>,  /* VDEC_CM */
1275                               <0 0x16023000 0 0x1000>,  /* VDEC_AD */
1276                               <0 0x16024000 0 0x1000>,  /* VDEC_AV */
1277                               <0 0x16025000 0 0x1000>,  /* VDEC_PP */
1278                               <0 0x16026800 0 0x800>,   /* VDEC_HWD */
1279                               <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
1280                               <0 0x16027800 0 0x800>,   /* VDEC_HWB */
1281                               <0 0x16028400 0 0x400>;   /* VDEC_HWG */
1282                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1283                         mediatek,larb = <&larb1>;
1284                         iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1285                                  <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1286                                  <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1287                                  <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1288                                  <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1289                                  <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1290                                  <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1291                                  <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1292                         mediatek,vpu = <&vpu>;
1293                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1294                         clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1295                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1296                                  <&topckgen CLK_TOP_CCI400_SEL>,
1297                                  <&topckgen CLK_TOP_VDEC_SEL>,
1298                                  <&topckgen CLK_TOP_VCODECPLL>,
1299                                  <&apmixedsys CLK_APMIXED_VENCPLL>,
1300                                  <&topckgen CLK_TOP_VENC_LT_SEL>,
1301                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1302                         clock-names = "vcodecpll",
1303                                       "univpll_d2",
1304                                       "clk_cci400_sel",
1305                                       "vdec_sel",
1306                                       "vdecpll",
1307                                       "vencpll",
1308                                       "venc_lt_sel",
1309                                       "vdec_bus_clk_src";
1310                 };
1311
1312                 larb1: larb@16010000 {
1313                         compatible = "mediatek,mt8173-smi-larb";
1314                         reg = <0 0x16010000 0 0x1000>;
1315                         mediatek,smi = <&smi_common>;
1316                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1317                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1318                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1319                         clock-names = "apb", "smi";
1320                 };
1321
1322                 vencsys: clock-controller@18000000 {
1323                         compatible = "mediatek,mt8173-vencsys", "syscon";
1324                         reg = <0 0x18000000 0 0x1000>;
1325                         #clock-cells = <1>;
1326                 };
1327
1328                 larb3: larb@18001000 {
1329                         compatible = "mediatek,mt8173-smi-larb";
1330                         reg = <0 0x18001000 0 0x1000>;
1331                         mediatek,smi = <&smi_common>;
1332                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1333                         clocks = <&vencsys CLK_VENC_CKE1>,
1334                                  <&vencsys CLK_VENC_CKE0>;
1335                         clock-names = "apb", "smi";
1336                 };
1337
1338                 vcodec_enc: vcodec@18002000 {
1339                         compatible = "mediatek,mt8173-vcodec-enc";
1340                         reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
1341                               <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
1342                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1343                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1344                         mediatek,larb = <&larb3>,
1345                                         <&larb5>;
1346                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1347                                  <&iommu M4U_PORT_VENC_REC>,
1348                                  <&iommu M4U_PORT_VENC_BSDMA>,
1349                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1350                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1351                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1352                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1353                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1354                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1355                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1356                                  <&iommu M4U_PORT_VENC_NBM_WDMA>,
1357                                  <&iommu M4U_PORT_VENC_RCPU_SET2>,
1358                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1359                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1360                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1361                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1362                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1363                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1364                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1365                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1366                         mediatek,vpu = <&vpu>;
1367                         clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1368                                  <&topckgen CLK_TOP_VENC_SEL>,
1369                                  <&topckgen CLK_TOP_UNIVPLL1_D2>,
1370                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
1371                         clock-names = "venc_sel_src",
1372                                       "venc_sel",
1373                                       "venc_lt_sel_src",
1374                                       "venc_lt_sel";
1375                 };
1376
1377                 vencltsys: clock-controller@19000000 {
1378                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1379                         reg = <0 0x19000000 0 0x1000>;
1380                         #clock-cells = <1>;
1381                 };
1382
1383                 larb5: larb@19001000 {
1384                         compatible = "mediatek,mt8173-smi-larb";
1385                         reg = <0 0x19001000 0 0x1000>;
1386                         mediatek,smi = <&smi_common>;
1387                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1388                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1389                                  <&vencltsys CLK_VENCLT_CKE0>;
1390                         clock-names = "apb", "smi";
1391                 };
1392         };
1393 };
1394