arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include "mt8173-pinfunc.h"
  22
  23 / {
  24         compatible = "mediatek,mt8173";
  25         interrupt-parent = <&sysirq>;
  26         #address-cells = <2>;
  27         #size-cells = <2>;
  28
  29         aliases {
  30                 ovl0 = &ovl0;
  31                 ovl1 = &ovl1;
  32                 rdma0 = &rdma0;
  33                 rdma1 = &rdma1;
  34                 rdma2 = &rdma2;
  35                 wdma0 = &wdma0;
  36                 wdma1 = &wdma1;
  37                 color0 = &color0;
  38                 color1 = &color1;
  39                 split0 = &split0;
  40                 split1 = &split1;
  41                 dpi0 = &dpi0;
  42                 dsi0 = &dsi0;
  43                 dsi1 = &dsi1;
  44                 mdp_rdma0 = &mdp_rdma0;
  45                 mdp_rdma1 = &mdp_rdma1;
  46                 mdp_rsz0 = &mdp_rsz0;
  47                 mdp_rsz1 = &mdp_rsz1;
  48                 mdp_rsz2 = &mdp_rsz2;
  49                 mdp_wdma0 = &mdp_wdma0;
  50                 mdp_wrot0 = &mdp_wrot0;
  51                 mdp_wrot1 = &mdp_wrot1;
  52         };
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu-map {
  59                         cluster0 {
  60                                 core0 {
  61                                         cpu = <&cpu0>;
  62                                 };
  63                                 core1 {
  64                                         cpu = <&cpu1>;
  65                                 };
  66                         };
  67
  68                         cluster1 {
  69                                 core0 {
  70                                         cpu = <&cpu2>;
  71                                 };
  72                                 core1 {
  73                                         cpu = <&cpu3>;
  74                                 };
  75                         };
  76                 };
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53";
  81                         reg = <0x000>;
  82                         enable-method = "psci";
  83                         cpu-idle-states = <&CPU_SLEEP_0>;
  84                 };
  85
  86                 cpu1: cpu@1 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x001>;
  90                         enable-method = "psci";
  91                         cpu-idle-states = <&CPU_SLEEP_0>;
  92                 };
  93
  94                 cpu2: cpu@100 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a57";
  97                         reg = <0x100>;
  98                         enable-method = "psci";
  99                         cpu-idle-states = <&CPU_SLEEP_0>;
 100                 };
 101
 102                 cpu3: cpu@101 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a57";
 105                         reg = <0x101>;
 106                         enable-method = "psci";
 107                         cpu-idle-states = <&CPU_SLEEP_0>;
 108                 };
 109
 110                 idle-states {
 111                         entry-method = "psci";
 112
 113                         CPU_SLEEP_0: cpu-sleep-0 {
 114                                 compatible = "arm,idle-state";
 115                                 local-timer-stop;
 116                                 entry-latency-us = <639>;
 117                                 exit-latency-us = <680>;
 118                                 min-residency-us = <1088>;
 119                                 arm,psci-suspend-param = <0x0010000>;
 120                         };
 121                 };
 122         };
 123
 124         psci {
 125                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 126                 method = "smc";
 127                 cpu_suspend   = <0x84000001>;
 128                 cpu_off       = <0x84000002>;
 129                 cpu_on        = <0x84000003>;
 130         };
 131
 132         clk26m: oscillator@0 {
 133                 compatible = "fixed-clock";
 134                 #clock-cells = <0>;
 135                 clock-frequency = <26000000>;
 136                 clock-output-names = "clk26m";
 137         };
 138
 139         clk32k: oscillator@1 {
 140                 compatible = "fixed-clock";
 141                 #clock-cells = <0>;
 142                 clock-frequency = <32000>;
 143                 clock-output-names = "clk32k";
 144         };
 145
 146         cpum_ck: oscillator@2 {
 147                 compatible = "fixed-clock";
 148                 #clock-cells = <0>;
 149                 clock-frequency = <0>;
 150                 clock-output-names = "cpum_ck";
 151         };
 152
 153         thermal-zones {
 154                 cpu_thermal: cpu_thermal {
 155                         polling-delay-passive = <1000>; /* milliseconds */
 156                         polling-delay = <1000>; /* milliseconds */
 157
 158                         thermal-sensors = <&thermal>;
 159                         sustainable-power = <1500>; /* milliwatts */
 160
 161                         trips {
 162                                 threshold: trip-point@0 {
 163                                         temperature = <68000>;
 164                                         hysteresis = <2000>;
 165                                         type = "passive";
 166                                 };
 167
 168                                 target: trip-point@1 {
 169                                         temperature = <85000>;
 170                                         hysteresis = <2000>;
 171                                         type = "passive";
 172                                 };
 173
 174                                 cpu_crit: cpu_crit@0 {
 175                                         temperature = <115000>;
 176                                         hysteresis = <2000>;
 177                                         type = "critical";
 178                                 };
 179                         };
 180
 181                         cooling-maps {
 182                                 map@0 {
 183                                         trip = <&target>;
 184                                         cooling-device = <&cpu0 0 0>;
 185                                         contribution = <3072>;
 186                                 };
 187                                 map@1 {
 188                                         trip = <&target>;
 189                                         cooling-device = <&cpu2 0 0>;
 190                                         contribution = <1024>;
 191                                 };
 192                         };
 193                 };
 194         };
 195
 196         reserved-memory {
 197                 #address-cells = <2>;
 198                 #size-cells = <2>;
 199                 ranges;
 200                 vpu_dma_reserved: vpu_dma_mem_region {
 201                         compatible = "shared-dma-pool";
 202                         reg = <0 0xb7000000 0 0x500000>;
 203                         alignment = <0x1000>;
 204                         no-map;
 205                 };
 206         };
 207
 208         timer {
 209                 compatible = "arm,armv8-timer";
 210                 interrupt-parent = <&gic>;
 211                 interrupts = <GIC_PPI 13
 212                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 213                              <GIC_PPI 14
 214                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 215                              <GIC_PPI 11
 216                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 217                              <GIC_PPI 10
 218                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 219         };
 220
 221         soc {
 222                 #address-cells = <2>;
 223                 #size-cells = <2>;
 224                 compatible = "simple-bus";
 225                 ranges;
 226
 227                 topckgen: clock-controller@10000000 {
 228                         compatible = "mediatek,mt8173-topckgen";
 229                         reg = <0 0x10000000 0 0x1000>;
 230                         #clock-cells = <1>;
 231                 };
 232
 233                 infracfg: power-controller@10001000 {
 234                         compatible = "mediatek,mt8173-infracfg", "syscon";
 235                         reg = <0 0x10001000 0 0x1000>;
 236                         #clock-cells = <1>;
 237                         #reset-cells = <1>;
 238                 };
 239
 240                 pericfg: power-controller@10003000 {
 241                         compatible = "mediatek,mt8173-pericfg", "syscon";
 242                         reg = <0 0x10003000 0 0x1000>;
 243                         #clock-cells = <1>;
 244                         #reset-cells = <1>;
 245                 };
 246
 247                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 248                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 249                         reg = <0 0x10005000 0 0x1000>;
 250                 };
 251
 252                 pio: pinctrl@0x10005000 {
 253                         compatible = "mediatek,mt8173-pinctrl";
 254                         reg = <0 0x1000b000 0 0x1000>;
 255                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 256                         pins-are-numbered;
 257                         gpio-controller;
 258                         #gpio-cells = <2>;
 259                         interrupt-controller;
 260                         #interrupt-cells = <2>;
 261                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 262                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 263                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 264
 265                         hdmi_pin: xxx {
 266
 267                                 /*hdmi htplg pin*/
 268                                 pins1 {
 269                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 270                                         input-enable;
 271                                         bias-pull-down;
 272                                 };
 273                         };
 274
 275                         i2c0_pins_a: i2c0 {
 276                                 pins1 {
 277                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 278                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 279                                         bias-disable;
 280                                 };
 281                         };
 282
 283                         i2c1_pins_a: i2c1 {
 284                                 pins1 {
 285                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 286                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 287                                         bias-disable;
 288                                 };
 289                         };
 290
 291                         i2c2_pins_a: i2c2 {
 292                                 pins1 {
 293                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 294                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 295                                         bias-disable;
 296                                 };
 297                         };
 298
 299                         i2c3_pins_a: i2c3 {
 300                                 pins1 {
 301                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 302                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 303                                         bias-disable;
 304                                 };
 305                         };
 306
 307                         i2c4_pins_a: i2c4 {
 308                                 pins1 {
 309                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 310                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 311                                         bias-disable;
 312                                 };
 313                         };
 314
 315                         i2c6_pins_a: i2c6 {
 316                                 pins1 {
 317                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 318                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 319                                         bias-disable;
 320                                 };
 321                         };
 322                 };
 323
 324                 scpsys: scpsys@10006000 {
 325                         compatible = "mediatek,mt8173-scpsys";
 326                         #power-domain-cells = <1>;
 327                         reg = <0 0x10006000 0 0x1000>;
 328                         clocks = <&clk26m>,
 329                                  <&topckgen CLK_TOP_MM_SEL>,
 330                                  <&topckgen CLK_TOP_VENC_SEL>,
 331                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 332                         clock-names = "mfg", "mm", "venc", "venc_lt";
 333                         infracfg = <&infracfg>;
 334                 };
 335
 336                 watchdog: watchdog@10007000 {
 337                         compatible = "mediatek,mt8173-wdt",
 338                                      "mediatek,mt6589-wdt";
 339                         reg = <0 0x10007000 0 0x100>;
 340                 };
 341
 342                 timer: timer@10008000 {
 343                         compatible = "mediatek,mt8173-timer",
 344                                      "mediatek,mt6577-timer";
 345                         reg = <0 0x10008000 0 0x1000>;
 346                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 347                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 348                                  <&topckgen CLK_TOP_RTC_SEL>;
 349                 };
 350
 351                 pwrap: pwrap@1000d000 {
 352                         compatible = "mediatek,mt8173-pwrap";
 353                         reg = <0 0x1000d000 0 0x1000>;
 354                         reg-names = "pwrap";
 355                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 356                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 357                         reset-names = "pwrap";
 358                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 359                         clock-names = "spi", "wrap";
 360                 };
 361
 362                 cec: cec@10013000 {
 363                         compatible = "mediatek,mt8173-cec";
 364                         reg = <0 0x10013000 0 0xbc>;
 365                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 366                         clocks = <&infracfg CLK_INFRA_CEC>;
 367                         status = "disabled";
 368                 };
 369
 370                 vpu: vpu@10020000 {
 371                         compatible = "mediatek,mt8173-vpu";
 372                         reg = <0 0x10020000 0 0x30000>,
 373                               <0 0x10050000 0 0x100>;
 374                         reg-names = "tcm", "cfg_reg";
 375                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 376                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 377                         clock-names = "main";
 378                         memory-region = <&vpu_dma_reserved>;
 379                 };
 380
 381                 sysirq: intpol-controller@10200620 {
 382                         compatible = "mediatek,mt8173-sysirq",
 383                                      "mediatek,mt6577-sysirq";
 384                         interrupt-controller;
 385                         #interrupt-cells = <3>;
 386                         interrupt-parent = <&gic>;
 387                         reg = <0 0x10200620 0 0x20>;
 388                 };
 389
 390                 iommu: iommu@10205000 {
 391                         compatible = "mediatek,mt8173-m4u";
 392                         reg = <0 0x10205000 0 0x1000>;
 393                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 394                         clocks = <&infracfg CLK_INFRA_M4U>;
 395                         clock-names = "bclk";
 396                         mediatek,larbs = <&larb0 &larb1 &larb2
 397                                           &larb3 &larb4 &larb5>;
 398                         #iommu-cells = <1>;
 399                 };
 400
 401                 efuse: efuse@10206000 {
 402                         compatible = "mediatek,mt8173-efuse";
 403                         reg = <0 0x10206000 0 0x1000>;
 404                         #address-cells = <1>;
 405                         #size-cells = <1>;
 406                         thermal_calibration: calib@528 {
 407                                 reg = <0x528 0xc>;
 408                         };
 409                 };
 410
 411                 apmixedsys: clock-controller@10209000 {
 412                         compatible = "mediatek,mt8173-apmixedsys";
 413                         reg = <0 0x10209000 0 0x1000>;
 414                         #clock-cells = <1>;
 415                 };
 416
 417                 hdmi_phy: hdmi-phy@10209100 {
 418                         compatible = "mediatek,mt8173-hdmi-phy";
 419                         reg = <0 0x10209100 0 0x24>;
 420                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 421                         clock-names = "pll_ref";
 422                         clock-output-names = "hdmitx_dig_cts";
 423                         mediatek,ibias = <0xa>;
 424                         mediatek,ibias_up = <0x1c>;
 425                         #clock-cells = <0>;
 426                         #phy-cells = <0>;
 427                         status = "disabled";
 428                 };
 429
 430                 mipi_tx0: mipi-dphy@10215000 {
 431                         compatible = "mediatek,mt8173-mipi-tx";
 432                         reg = <0 0x10215000 0 0x1000>;
 433                         clocks = <&clk26m>;
 434                         clock-output-names = "mipi_tx0_pll";
 435                         #clock-cells = <0>;
 436                         #phy-cells = <0>;
 437                         status = "disabled";
 438                 };
 439
 440                 mipi_tx1: mipi-dphy@10216000 {
 441                         compatible = "mediatek,mt8173-mipi-tx";
 442                         reg = <0 0x10216000 0 0x1000>;
 443                         clocks = <&clk26m>;
 444                         clock-output-names = "mipi_tx1_pll";
 445                         #clock-cells = <0>;
 446                         #phy-cells = <0>;
 447                         status = "disabled";
 448                 };
 449
 450                 gic: interrupt-controller@10220000 {
 451                         compatible = "arm,gic-400";
 452                         #interrupt-cells = <3>;
 453                         interrupt-parent = <&gic>;
 454                         interrupt-controller;
 455                         reg = <0 0x10221000 0 0x1000>,
 456                               <0 0x10222000 0 0x2000>,
 457                               <0 0x10224000 0 0x2000>,
 458                               <0 0x10226000 0 0x2000>;
 459                         interrupts = <GIC_PPI 9
 460                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 461                 };
 462
 463                 auxadc: auxadc@11001000 {
 464                         compatible = "mediatek,mt8173-auxadc";
 465                         reg = <0 0x11001000 0 0x1000>;
 466                         clocks = <&pericfg CLK_PERI_AUXADC>;
 467                         clock-names = "main";
 468                         #io-channel-cells = <1>;
 469                 };
 470
 471                 uart0: serial@11002000 {
 472                         compatible = "mediatek,mt8173-uart",
 473                                      "mediatek,mt6577-uart";
 474                         reg = <0 0x11002000 0 0x400>;
 475                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 476                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 477                         clock-names = "baud", "bus";
 478                         status = "disabled";
 479                 };
 480
 481                 uart1: serial@11003000 {
 482                         compatible = "mediatek,mt8173-uart",
 483                                      "mediatek,mt6577-uart";
 484                         reg = <0 0x11003000 0 0x400>;
 485                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 486                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 487                         clock-names = "baud", "bus";
 488                         status = "disabled";
 489                 };
 490
 491                 uart2: serial@11004000 {
 492                         compatible = "mediatek,mt8173-uart",
 493                                      "mediatek,mt6577-uart";
 494                         reg = <0 0x11004000 0 0x400>;
 495                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 496                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 497                         clock-names = "baud", "bus";
 498                         status = "disabled";
 499                 };
 500
 501                 uart3: serial@11005000 {
 502                         compatible = "mediatek,mt8173-uart",
 503                                      "mediatek,mt6577-uart";
 504                         reg = <0 0x11005000 0 0x400>;
 505                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 506                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 507                         clock-names = "baud", "bus";
 508                         status = "disabled";
 509                 };
 510
 511                 i2c0: i2c@11007000 {
 512                         compatible = "mediatek,mt8173-i2c";
 513                         reg = <0 0x11007000 0 0x70>,
 514                               <0 0x11000100 0 0x80>;
 515                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 516                         clock-div = <16>;
 517                         clocks = <&pericfg CLK_PERI_I2C0>,
 518                                  <&pericfg CLK_PERI_AP_DMA>;
 519                         clock-names = "main", "dma";
 520                         pinctrl-names = "default";
 521                         pinctrl-0 = <&i2c0_pins_a>;
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         status = "disabled";
 525                 };
 526
 527                 i2c1: i2c@11008000 {
 528                         compatible = "mediatek,mt8173-i2c";
 529                         reg = <0 0x11008000 0 0x70>,
 530                               <0 0x11000180 0 0x80>;
 531                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 532                         clock-div = <16>;
 533                         clocks = <&pericfg CLK_PERI_I2C1>,
 534                                  <&pericfg CLK_PERI_AP_DMA>;
 535                         clock-names = "main", "dma";
 536                         pinctrl-names = "default";
 537                         pinctrl-0 = <&i2c1_pins_a>;
 538                         #address-cells = <1>;
 539                         #size-cells = <0>;
 540                         status = "disabled";
 541                 };
 542
 543                 i2c2: i2c@11009000 {
 544                         compatible = "mediatek,mt8173-i2c";
 545                         reg = <0 0x11009000 0 0x70>,
 546                               <0 0x11000200 0 0x80>;
 547                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 548                         clock-div = <16>;
 549                         clocks = <&pericfg CLK_PERI_I2C2>,
 550                                  <&pericfg CLK_PERI_AP_DMA>;
 551                         clock-names = "main", "dma";
 552                         pinctrl-names = "default";
 553                         pinctrl-0 = <&i2c2_pins_a>;
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         status = "disabled";
 557                 };
 558
 559                 spi: spi@1100a000 {
 560                         compatible = "mediatek,mt8173-spi";
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                         reg = <0 0x1100a000 0 0x1000>;
 564                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 565                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 566                                  <&topckgen CLK_TOP_SPI_SEL>,
 567                                  <&pericfg CLK_PERI_SPI0>;
 568                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 569                         status = "disabled";
 570                 };
 571
 572                 thermal: thermal@1100b000 {
 573                         #thermal-sensor-cells = <0>;
 574                         compatible = "mediatek,mt8173-thermal";
 575                         reg = <0 0x1100b000 0 0x1000>;
 576                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 577                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 578                         clock-names = "therm", "auxadc";
 579                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 580                         mediatek,auxadc = <&auxadc>;
 581                         mediatek,apmixedsys = <&apmixedsys>;
 582                         nvmem-cells = <&thermal_calibration>;
 583                         nvmem-cell-names = "calibration-data";
 584                 };
 585
 586                 nor_flash: spi@1100d000 {
 587                         compatible = "mediatek,mt8173-nor";
 588                         reg = <0 0x1100d000 0 0xe0>;
 589                         clocks = <&pericfg CLK_PERI_SPI>,
 590                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 591                         clock-names = "spi", "sf";
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                         status = "disabled";
 595                 };
 596
 597                 i2c3: i2c@11010000 {
 598                         compatible = "mediatek,mt8173-i2c";
 599                         reg = <0 0x11010000 0 0x70>,
 600                               <0 0x11000280 0 0x80>;
 601                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 602                         clock-div = <16>;
 603                         clocks = <&pericfg CLK_PERI_I2C3>,
 604                                  <&pericfg CLK_PERI_AP_DMA>;
 605                         clock-names = "main", "dma";
 606                         pinctrl-names = "default";
 607                         pinctrl-0 = <&i2c3_pins_a>;
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         status = "disabled";
 611                 };
 612
 613                 i2c4: i2c@11011000 {
 614                         compatible = "mediatek,mt8173-i2c";
 615                         reg = <0 0x11011000 0 0x70>,
 616                               <0 0x11000300 0 0x80>;
 617                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 618                         clock-div = <16>;
 619                         clocks = <&pericfg CLK_PERI_I2C4>,
 620                                  <&pericfg CLK_PERI_AP_DMA>;
 621                         clock-names = "main", "dma";
 622                         pinctrl-names = "default";
 623                         pinctrl-0 = <&i2c4_pins_a>;
 624                         #address-cells = <1>;
 625                         #size-cells = <0>;
 626                         status = "disabled";
 627                 };
 628
 629                 hdmiddc0: i2c@11012000 {
 630                         compatible = "mediatek,mt8173-hdmi-ddc";
 631                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 632                         reg = <0 0x11012000 0 0x1C>;
 633                         clocks = <&pericfg CLK_PERI_I2C5>;
 634                         clock-names = "ddc-i2c";
 635                 };
 636
 637                 i2c6: i2c@11013000 {
 638                         compatible = "mediatek,mt8173-i2c";
 639                         reg = <0 0x11013000 0 0x70>,
 640                               <0 0x11000080 0 0x80>;
 641                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 642                         clock-div = <16>;
 643                         clocks = <&pericfg CLK_PERI_I2C6>,
 644                                  <&pericfg CLK_PERI_AP_DMA>;
 645                         clock-names = "main", "dma";
 646                         pinctrl-names = "default";
 647                         pinctrl-0 = <&i2c6_pins_a>;
 648                         #address-cells = <1>;
 649                         #size-cells = <0>;
 650                         status = "disabled";
 651                 };
 652
 653                 afe: audio-controller@11220000  {
 654                         compatible = "mediatek,mt8173-afe-pcm";
 655                         reg = <0 0x11220000 0 0x1000>;
 656                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 657                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 658                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 659                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 660                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 661                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 662                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 663                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 664                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 665                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 666                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 667                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 668                         clock-names = "infra_sys_audio_clk",
 669                                       "top_pdn_audio",
 670                                       "top_pdn_aud_intbus",
 671                                       "bck0",
 672                                       "bck1",
 673                                       "i2s0_m",
 674                                       "i2s1_m",
 675                                       "i2s2_m",
 676                                       "i2s3_m",
 677                                       "i2s3_b";
 678                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 679                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 680                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 681                                                  <&topckgen CLK_TOP_APLL2>;
 682                 };
 683
 684                 mmc0: mmc@11230000 {
 685                         compatible = "mediatek,mt8173-mmc",
 686                                      "mediatek,mt8135-mmc";
 687                         reg = <0 0x11230000 0 0x1000>;
 688                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 689                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 690                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 691                         clock-names = "source", "hclk";
 692                         status = "disabled";
 693                 };
 694
 695                 mmc1: mmc@11240000 {
 696                         compatible = "mediatek,mt8173-mmc",
 697                                      "mediatek,mt8135-mmc";
 698                         reg = <0 0x11240000 0 0x1000>;
 699                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 700                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 701                                  <&topckgen CLK_TOP_AXI_SEL>;
 702                         clock-names = "source", "hclk";
 703                         status = "disabled";
 704                 };
 705
 706                 mmc2: mmc@11250000 {
 707                         compatible = "mediatek,mt8173-mmc",
 708                                      "mediatek,mt8135-mmc";
 709                         reg = <0 0x11250000 0 0x1000>;
 710                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 711                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 712                                  <&topckgen CLK_TOP_AXI_SEL>;
 713                         clock-names = "source", "hclk";
 714                         status = "disabled";
 715                 };
 716
 717                 mmc3: mmc@11260000 {
 718                         compatible = "mediatek,mt8173-mmc",
 719                                      "mediatek,mt8135-mmc";
 720                         reg = <0 0x11260000 0 0x1000>;
 721                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 722                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 723                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 724                         clock-names = "source", "hclk";
 725                         status = "disabled";
 726                 };
 727
 728                 ssusb: usb@11271000 {
 729                         compatible = "mediatek,mt8173-mtu3";
 730                         reg = <0 0x11271000 0 0x3000>,
 731                               <0 0x11280700 0 0x0100>;
 732                         reg-names = "mac", "ippc";
 733                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 734                         phys = <&u2port0 PHY_TYPE_USB2>,
 735                                <&u3port0 PHY_TYPE_USB3>,
 736                                <&u2port1 PHY_TYPE_USB2>;
 737                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 738                         clocks = <&topckgen CLK_TOP_USB30_SEL>,
 739                                  <&clk26m>,
 740                                  <&pericfg CLK_PERI_USB0>,
 741                                  <&pericfg CLK_PERI_USB1>;
 742                         clock-names = "sys_ck",
 743                                       "ref_ck",
 744                                       "wakeup_deb_p0",
 745                                       "wakeup_deb_p1";
 746                         mediatek,syscon-wakeup = <&pericfg>;
 747                         #address-cells = <2>;
 748                         #size-cells = <2>;
 749                         ranges;
 750                         status = "disabled";
 751
 752                         usb_host: xhci@11270000 {
 753                                 compatible = "mediatek,mt8173-xhci";
 754                                 reg = <0 0x11270000 0 0x1000>;
 755                                 reg-names = "mac";
 756                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 757                                 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 758                                 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 759                                 clock-names = "sys_ck", "ref_ck";
 760                                 status = "disabled";
 761                         };
 762                 };
 763
 764                 u3phy: usb-phy@11290000 {
 765                         compatible = "mediatek,mt8173-u3phy";
 766                         reg = <0 0x11290000 0 0x800>;
 767                         #address-cells = <2>;
 768                         #size-cells = <2>;
 769                         ranges;
 770                         status = "okay";
 771
 772                         u2port0: usb-phy@11290800 {
 773                                 reg = <0 0x11290800 0 0x100>;
 774                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 775                                 clock-names = "ref";
 776                                 #phy-cells = <1>;
 777                                 status = "okay";
 778                         };
 779
 780                         u3port0: usb-phy@11290900 {
 781                                 reg = <0 0x11290900 0 0x700>;
 782                                 clocks = <&clk26m>;
 783                                 clock-names = "ref";
 784                                 #phy-cells = <1>;
 785                                 status = "okay";
 786                         };
 787
 788                         u2port1: usb-phy@11291000 {
 789                                 reg = <0 0x11291000 0 0x100>;
 790                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 791                                 clock-names = "ref";
 792                                 #phy-cells = <1>;
 793                                 status = "okay";
 794                         };
 795                 };
 796
 797                 mmsys: clock-controller@14000000 {
 798                         compatible = "mediatek,mt8173-mmsys", "syscon";
 799                         reg = <0 0x14000000 0 0x1000>;
 800                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 801                         assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
 802                         assigned-clock-rates = <400000000>;
 803                         #clock-cells = <1>;
 804                 };
 805
 806                 mdp_rdma0: rdma@14001000 {
 807                         compatible = "mediatek,mt8173-mdp-rdma",
 808                                      "mediatek,mt8173-mdp";
 809                         reg = <0 0x14001000 0 0x1000>;
 810                         clocks = <&mmsys CLK_MM_MDP_RDMA0>,
 811                                  <&mmsys CLK_MM_MUTEX_32K>;
 812                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 813                         iommus = <&iommu M4U_PORT_MDP_RDMA0>;
 814                         mediatek,larb = <&larb0>;
 815                         mediatek,vpu = <&vpu>;
 816                 };
 817
 818                 mdp_rdma1: rdma@14002000 {
 819                         compatible = "mediatek,mt8173-mdp-rdma";
 820                         reg = <0 0x14002000 0 0x1000>;
 821                         clocks = <&mmsys CLK_MM_MDP_RDMA1>,
 822                                  <&mmsys CLK_MM_MUTEX_32K>;
 823                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 824                         iommus = <&iommu M4U_PORT_MDP_RDMA1>;
 825                         mediatek,larb = <&larb4>;
 826                 };
 827
 828                 mdp_rsz0: rsz@14003000 {
 829                         compatible = "mediatek,mt8173-mdp-rsz";
 830                         reg = <0 0x14003000 0 0x1000>;
 831                         clocks = <&mmsys CLK_MM_MDP_RSZ0>;
 832                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 833                 };
 834
 835                 mdp_rsz1: rsz@14004000 {
 836                         compatible = "mediatek,mt8173-mdp-rsz";
 837                         reg = <0 0x14004000 0 0x1000>;
 838                         clocks = <&mmsys CLK_MM_MDP_RSZ1>;
 839                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 840                 };
 841
 842                 mdp_rsz2: rsz@14005000 {
 843                         compatible = "mediatek,mt8173-mdp-rsz";
 844                         reg = <0 0x14005000 0 0x1000>;
 845                         clocks = <&mmsys CLK_MM_MDP_RSZ2>;
 846                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 847                 };
 848
 849                 mdp_wdma0: wdma@14006000 {
 850                         compatible = "mediatek,mt8173-mdp-wdma";
 851                         reg = <0 0x14006000 0 0x1000>;
 852                         clocks = <&mmsys CLK_MM_MDP_WDMA>;
 853                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 854                         iommus = <&iommu M4U_PORT_MDP_WDMA>;
 855                         mediatek,larb = <&larb0>;
 856                 };
 857
 858                 mdp_wrot0: wrot@14007000 {
 859                         compatible = "mediatek,mt8173-mdp-wrot";
 860                         reg = <0 0x14007000 0 0x1000>;
 861                         clocks = <&mmsys CLK_MM_MDP_WROT0>;
 862                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 863                         iommus = <&iommu M4U_PORT_MDP_WROT0>;
 864                         mediatek,larb = <&larb0>;
 865                 };
 866
 867                 mdp_wrot1: wrot@14008000 {
 868                         compatible = "mediatek,mt8173-mdp-wrot";
 869                         reg = <0 0x14008000 0 0x1000>;
 870                         clocks = <&mmsys CLK_MM_MDP_WROT1>;
 871                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 872                         iommus = <&iommu M4U_PORT_MDP_WROT1>;
 873                         mediatek,larb = <&larb4>;
 874                 };
 875
 876                 ovl0: ovl@1400c000 {
 877                         compatible = "mediatek,mt8173-disp-ovl";
 878                         reg = <0 0x1400c000 0 0x1000>;
 879                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
 880                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 881                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
 882                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
 883                         mediatek,larb = <&larb0>;
 884                 };
 885
 886                 ovl1: ovl@1400d000 {
 887                         compatible = "mediatek,mt8173-disp-ovl";
 888                         reg = <0 0x1400d000 0 0x1000>;
 889                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
 890                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 891                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
 892                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
 893                         mediatek,larb = <&larb4>;
 894                 };
 895
 896                 rdma0: rdma@1400e000 {
 897                         compatible = "mediatek,mt8173-disp-rdma";
 898                         reg = <0 0x1400e000 0 0x1000>;
 899                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
 900                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 901                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 902                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
 903                         mediatek,larb = <&larb0>;
 904                 };
 905
 906                 rdma1: rdma@1400f000 {
 907                         compatible = "mediatek,mt8173-disp-rdma";
 908                         reg = <0 0x1400f000 0 0x1000>;
 909                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
 910                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 911                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 912                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
 913                         mediatek,larb = <&larb4>;
 914                 };
 915
 916                 rdma2: rdma@14010000 {
 917                         compatible = "mediatek,mt8173-disp-rdma";
 918                         reg = <0 0x14010000 0 0x1000>;
 919                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
 920                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 921                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
 922                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
 923                         mediatek,larb = <&larb4>;
 924                 };
 925
 926                 wdma0: wdma@14011000 {
 927                         compatible = "mediatek,mt8173-disp-wdma";
 928                         reg = <0 0x14011000 0 0x1000>;
 929                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
 930                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 931                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
 932                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
 933                         mediatek,larb = <&larb0>;
 934                 };
 935
 936                 wdma1: wdma@14012000 {
 937                         compatible = "mediatek,mt8173-disp-wdma";
 938                         reg = <0 0x14012000 0 0x1000>;
 939                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
 940                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 941                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
 942                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
 943                         mediatek,larb = <&larb4>;
 944                 };
 945
 946                 color0: color@14013000 {
 947                         compatible = "mediatek,mt8173-disp-color";
 948                         reg = <0 0x14013000 0 0x1000>;
 949                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
 950                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 951                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
 952                 };
 953
 954                 color1: color@14014000 {
 955                         compatible = "mediatek,mt8173-disp-color";
 956                         reg = <0 0x14014000 0 0x1000>;
 957                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
 958                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 959                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
 960                 };
 961
 962                 aal@14015000 {
 963                         compatible = "mediatek,mt8173-disp-aal";
 964                         reg = <0 0x14015000 0 0x1000>;
 965                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
 966                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 967                         clocks = <&mmsys CLK_MM_DISP_AAL>;
 968                 };
 969
 970                 gamma@14016000 {
 971                         compatible = "mediatek,mt8173-disp-gamma";
 972                         reg = <0 0x14016000 0 0x1000>;
 973                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
 974                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 975                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
 976                 };
 977
 978                 merge@14017000 {
 979                         compatible = "mediatek,mt8173-disp-merge";
 980                         reg = <0 0x14017000 0 0x1000>;
 981                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 982                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
 983                 };
 984
 985                 split0: split@14018000 {
 986                         compatible = "mediatek,mt8173-disp-split";
 987                         reg = <0 0x14018000 0 0x1000>;
 988                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 989                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
 990                 };
 991
 992                 split1: split@14019000 {
 993                         compatible = "mediatek,mt8173-disp-split";
 994                         reg = <0 0x14019000 0 0x1000>;
 995                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 996                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
 997                 };
 998
 999                 ufoe@1401a000 {
1000                         compatible = "mediatek,mt8173-disp-ufoe";
1001                         reg = <0 0x1401a000 0 0x1000>;
1002                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1003                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1004                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
1005                 };
1006
1007                 dsi0: dsi@1401b000 {
1008                         compatible = "mediatek,mt8173-dsi";
1009                         reg = <0 0x1401b000 0 0x1000>;
1010                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1011                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1012                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1013                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
1014                                  <&mipi_tx0>;
1015                         clock-names = "engine", "digital", "hs";
1016                         phys = <&mipi_tx0>;
1017                         phy-names = "dphy";
1018                         status = "disabled";
1019                 };
1020
1021                 dsi1: dsi@1401c000 {
1022                         compatible = "mediatek,mt8173-dsi";
1023                         reg = <0 0x1401c000 0 0x1000>;
1024                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1025                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1026                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1027                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
1028                                  <&mipi_tx1>;
1029                         clock-names = "engine", "digital", "hs";
1030                         phy = <&mipi_tx1>;
1031                         phy-names = "dphy";
1032                         status = "disabled";
1033                 };
1034
1035                 dpi0: dpi@1401d000 {
1036                         compatible = "mediatek,mt8173-dpi";
1037                         reg = <0 0x1401d000 0 0x1000>;
1038                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1039                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1040                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1041                                  <&mmsys CLK_MM_DPI_ENGINE>,
1042                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1043                         clock-names = "pixel", "engine", "pll";
1044                         status = "disabled";
1045
1046                         port {
1047                                 dpi0_out: endpoint {
1048                                         remote-endpoint = <&hdmi0_in>;
1049                                 };
1050                         };
1051                 };
1052
1053                 pwm0: pwm@1401e000 {
1054                         compatible = "mediatek,mt8173-disp-pwm",
1055                                      "mediatek,mt6595-disp-pwm";
1056                         reg = <0 0x1401e000 0 0x1000>;
1057                         #pwm-cells = <2>;
1058                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1059                                  <&mmsys CLK_MM_DISP_PWM0MM>;
1060                         clock-names = "main", "mm";
1061                         status = "disabled";
1062                 };
1063
1064                 pwm1: pwm@1401f000 {
1065                         compatible = "mediatek,mt8173-disp-pwm",
1066                                      "mediatek,mt6595-disp-pwm";
1067                         reg = <0 0x1401f000 0 0x1000>;
1068                         #pwm-cells = <2>;
1069                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1070                                  <&mmsys CLK_MM_DISP_PWM1MM>;
1071                         clock-names = "main", "mm";
1072                         status = "disabled";
1073                 };
1074
1075                 mutex: mutex@14020000 {
1076                         compatible = "mediatek,mt8173-disp-mutex";
1077                         reg = <0 0x14020000 0 0x1000>;
1078                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1079                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1080                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
1081                 };
1082
1083                 larb0: larb@14021000 {
1084                         compatible = "mediatek,mt8173-smi-larb";
1085                         reg = <0 0x14021000 0 0x1000>;
1086                         mediatek,smi = <&smi_common>;
1087                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1088                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1089                                  <&mmsys CLK_MM_SMI_LARB0>;
1090                         clock-names = "apb", "smi";
1091                 };
1092
1093                 smi_common: smi@14022000 {
1094                         compatible = "mediatek,mt8173-smi-common";
1095                         reg = <0 0x14022000 0 0x1000>;
1096                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1097                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1098                                  <&mmsys CLK_MM_SMI_COMMON>;
1099                         clock-names = "apb", "smi";
1100                 };
1101
1102                 od@14023000 {
1103                         compatible = "mediatek,mt8173-disp-od";
1104                         reg = <0 0x14023000 0 0x1000>;
1105                         clocks = <&mmsys CLK_MM_DISP_OD>;
1106                 };
1107
1108                 hdmi0: hdmi@14025000 {
1109                         compatible = "mediatek,mt8173-hdmi";
1110                         reg = <0 0x14025000 0 0x400>;
1111                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1112                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1113                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1114                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1115                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1116                         clock-names = "pixel", "pll", "bclk", "spdif";
1117                         pinctrl-names = "default";
1118                         pinctrl-0 = <&hdmi_pin>;
1119                         phys = <&hdmi_phy>;
1120                         phy-names = "hdmi";
1121                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1122                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1123                         assigned-clock-parents = <&hdmi_phy>;
1124                         status = "disabled";
1125
1126                         ports {
1127                                 #address-cells = <1>;
1128                                 #size-cells = <0>;
1129
1130                                 port@0 {
1131                                         reg = <0>;
1132
1133                                         hdmi0_in: endpoint {
1134                                                 remote-endpoint = <&dpi0_out>;
1135                                         };
1136                                 };
1137                         };
1138                 };
1139
1140                 larb4: larb@14027000 {
1141                         compatible = "mediatek,mt8173-smi-larb";
1142                         reg = <0 0x14027000 0 0x1000>;
1143                         mediatek,smi = <&smi_common>;
1144                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1145                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1146                                  <&mmsys CLK_MM_SMI_LARB4>;
1147                         clock-names = "apb", "smi";
1148                 };
1149
1150                 imgsys: clock-controller@15000000 {
1151                         compatible = "mediatek,mt8173-imgsys", "syscon";
1152                         reg = <0 0x15000000 0 0x1000>;
1153                         #clock-cells = <1>;
1154                 };
1155
1156                 larb2: larb@15001000 {
1157                         compatible = "mediatek,mt8173-smi-larb";
1158                         reg = <0 0x15001000 0 0x1000>;
1159                         mediatek,smi = <&smi_common>;
1160                         power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1161                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1162                                  <&imgsys CLK_IMG_LARB2_SMI>;
1163                         clock-names = "apb", "smi";
1164                 };
1165
1166                 vdecsys: clock-controller@16000000 {
1167                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1168                         reg = <0 0x16000000 0 0x1000>;
1169                         #clock-cells = <1>;
1170                 };
1171
1172                 vcodec_dec: vcodec@16000000 {
1173                         compatible = "mediatek,mt8173-vcodec-dec";
1174                         reg = <0 0x16000000 0 0x100>,   /* VDEC_SYS */
1175                               <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
1176                               <0 0x16021000 0 0x800>,   /* VDEC_LD */
1177                               <0 0x16021800 0 0x800>,   /* VDEC_TOP */
1178                               <0 0x16022000 0 0x1000>,  /* VDEC_CM */
1179                               <0 0x16023000 0 0x1000>,  /* VDEC_AD */
1180                               <0 0x16024000 0 0x1000>,  /* VDEC_AV */
1181                               <0 0x16025000 0 0x1000>,  /* VDEC_PP */
1182                               <0 0x16026800 0 0x800>,   /* VDEC_HWD */
1183                               <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
1184                               <0 0x16027800 0 0x800>,   /* VDEC_HWB */
1185                               <0 0x16028400 0 0x400>;   /* VDEC_HWG */
1186                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1187                         mediatek,larb = <&larb1>;
1188                         iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1189                                  <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1190                                  <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1191                                  <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1192                                  <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1193                                  <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1194                                  <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1195                                  <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1196                         mediatek,vpu = <&vpu>;
1197                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1198                         clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1199                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1200                                  <&topckgen CLK_TOP_CCI400_SEL>,
1201                                  <&topckgen CLK_TOP_VDEC_SEL>,
1202                                  <&topckgen CLK_TOP_VCODECPLL>,
1203                                  <&apmixedsys CLK_APMIXED_VENCPLL>,
1204                                  <&topckgen CLK_TOP_VENC_LT_SEL>,
1205                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1206                         clock-names = "vcodecpll",
1207                                       "univpll_d2",
1208                                       "clk_cci400_sel",
1209                                       "vdec_sel",
1210                                       "vdecpll",
1211                                       "vencpll",
1212                                       "venc_lt_sel",
1213                                       "vdec_bus_clk_src";
1214                 };
1215
1216                 larb1: larb@16010000 {
1217                         compatible = "mediatek,mt8173-smi-larb";
1218                         reg = <0 0x16010000 0 0x1000>;
1219                         mediatek,smi = <&smi_common>;
1220                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1221                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1222                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1223                         clock-names = "apb", "smi";
1224                 };
1225
1226                 vencsys: clock-controller@18000000 {
1227                         compatible = "mediatek,mt8173-vencsys", "syscon";
1228                         reg = <0 0x18000000 0 0x1000>;
1229                         #clock-cells = <1>;
1230                 };
1231
1232                 larb3: larb@18001000 {
1233                         compatible = "mediatek,mt8173-smi-larb";
1234                         reg = <0 0x18001000 0 0x1000>;
1235                         mediatek,smi = <&smi_common>;
1236                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1237                         clocks = <&vencsys CLK_VENC_CKE1>,
1238                                  <&vencsys CLK_VENC_CKE0>;
1239                         clock-names = "apb", "smi";
1240                 };
1241
1242                 vcodec_enc: vcodec@18002000 {
1243                         compatible = "mediatek,mt8173-vcodec-enc";
1244                         reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
1245                               <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
1246                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1247                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1248                         mediatek,larb = <&larb3>,
1249                                         <&larb5>;
1250                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1251                                  <&iommu M4U_PORT_VENC_REC>,
1252                                  <&iommu M4U_PORT_VENC_BSDMA>,
1253                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1254                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1255                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1256                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1257                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1258                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1259                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1260                                  <&iommu M4U_PORT_VENC_NBM_WDMA>,
1261                                  <&iommu M4U_PORT_VENC_RCPU_SET2>,
1262                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1263                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1264                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1265                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1266                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1267                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1268                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1269                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1270                         mediatek,vpu = <&vpu>;
1271                         clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1272                                  <&topckgen CLK_TOP_VENC_SEL>,
1273                                  <&topckgen CLK_TOP_UNIVPLL1_D2>,
1274                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
1275                         clock-names = "venc_sel_src",
1276                                       "venc_sel",
1277                                       "venc_lt_sel_src",
1278                                       "venc_lt_sel";
1279                 };
1280
1281                 vencltsys: clock-controller@19000000 {
1282                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1283                         reg = <0 0x19000000 0 0x1000>;
1284                         #clock-cells = <1>;
1285                 };
1286
1287                 larb5: larb@19001000 {
1288                         compatible = "mediatek,mt8173-smi-larb";
1289                         reg = <0 0x19001000 0 0x1000>;
1290                         mediatek,smi = <&smi_common>;
1291                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1292                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1293                                  <&vencltsys CLK_VENCLT_CKE0>;
1294                         clock-names = "apb", "smi";
1295                 };
1296         };
1297 };
1298