arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/memory/mt8173-larb-port.h>
  18 #include <dt-bindings/phy/phy.h>
  19 #include <dt-bindings/power/mt8173-power.h>
  20 #include <dt-bindings/reset/mt8173-resets.h>
  21 #include "mt8173-pinfunc.h"
  22
  23 / {
  24         compatible = "mediatek,mt8173";
  25         interrupt-parent = <&sysirq>;
  26         #address-cells = <2>;
  27         #size-cells = <2>;
  28
  29         aliases {
  30                 ovl0 = &ovl0;
  31                 ovl1 = &ovl1;
  32                 rdma0 = &rdma0;
  33                 rdma1 = &rdma1;
  34                 rdma2 = &rdma2;
  35                 wdma0 = &wdma0;
  36                 wdma1 = &wdma1;
  37                 color0 = &color0;
  38                 color1 = &color1;
  39                 split0 = &split0;
  40                 split1 = &split1;
  41                 dpi0 = &dpi0;
  42                 dsi0 = &dsi0;
  43                 dsi1 = &dsi1;
  44                 mdp_rdma0 = &mdp_rdma0;
  45                 mdp_rdma1 = &mdp_rdma1;
  46                 mdp_rsz0 = &mdp_rsz0;
  47                 mdp_rsz1 = &mdp_rsz1;
  48                 mdp_rsz2 = &mdp_rsz2;
  49                 mdp_wdma0 = &mdp_wdma0;
  50                 mdp_wrot0 = &mdp_wrot0;
  51                 mdp_wrot1 = &mdp_wrot1;
  52         };
  53
  54         cluster0_opp: opp_table0 {
  55                 compatible = "operating-points-v2";
  56                 opp-shared;
  57                 opp-507000000 {
  58                         opp-hz = /bits/ 64 <507000000>;
  59                         opp-microvolt = <859000>;
  60                 };
  61                 opp-702000000 {
  62                         opp-hz = /bits/ 64 <702000000>;
  63                         opp-microvolt = <908000>;
  64                 };
  65                 opp-1001000000 {
  66                         opp-hz = /bits/ 64 <1001000000>;
  67                         opp-microvolt = <983000>;
  68                 };
  69                 opp-1105000000 {
  70                         opp-hz = /bits/ 64 <1105000000>;
  71                         opp-microvolt = <1009000>;
  72                 };
  73                 opp-1209000000 {
  74                         opp-hz = /bits/ 64 <1209000000>;
  75                         opp-microvolt = <1034000>;
  76                 };
  77                 opp-1300000000 {
  78                         opp-hz = /bits/ 64 <1300000000>;
  79                         opp-microvolt = <1057000>;
  80                 };
  81                 opp-1508000000 {
  82                         opp-hz = /bits/ 64 <1508000000>;
  83                         opp-microvolt = <1109000>;
  84                 };
  85                 opp-1703000000 {
  86                         opp-hz = /bits/ 64 <1703000000>;
  87                         opp-microvolt = <1125000>;
  88                 };
  89         };
  90
  91         cluster1_opp: opp_table1 {
  92                 compatible = "operating-points-v2";
  93                 opp-shared;
  94                 opp-507000000 {
  95                         opp-hz = /bits/ 64 <507000000>;
  96                         opp-microvolt = <828000>;
  97                 };
  98                 opp-702000000 {
  99                         opp-hz = /bits/ 64 <702000000>;
 100                         opp-microvolt = <867000>;
 101                 };
 102                 opp-1001000000 {
 103                         opp-hz = /bits/ 64 <1001000000>;
 104                         opp-microvolt = <927000>;
 105                 };
 106                 opp-1209000000 {
 107                         opp-hz = /bits/ 64 <1209000000>;
 108                         opp-microvolt = <968000>;
 109                 };
 110                 opp-1404000000 {
 111                         opp-hz = /bits/ 64 <1404000000>;
 112                         opp-microvolt = <1007000>;
 113                 };
 114                 opp-1612000000 {
 115                         opp-hz = /bits/ 64 <1612000000>;
 116                         opp-microvolt = <1049000>;
 117                 };
 118                 opp-1807000000 {
 119                         opp-hz = /bits/ 64 <1807000000>;
 120                         opp-microvolt = <1089000>;
 121                 };
 122                 opp-2106000000 {
 123                         opp-hz = /bits/ 64 <2106000000>;
 124                         opp-microvolt = <1125000>;
 125                 };
 126         };
 127
 128         cpus {
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131
 132                 cpu-map {
 133                         cluster0 {
 134                                 core0 {
 135                                         cpu = <&cpu0>;
 136                                 };
 137                                 core1 {
 138                                         cpu = <&cpu1>;
 139                                 };
 140                         };
 141
 142                         cluster1 {
 143                                 core0 {
 144                                         cpu = <&cpu2>;
 145                                 };
 146                                 core1 {
 147                                         cpu = <&cpu3>;
 148                                 };
 149                         };
 150                 };
 151
 152                 cpu0: cpu@0 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a53";
 155                         reg = <0x000>;
 156                         enable-method = "psci";
 157                         cpu-idle-states = <&CPU_SLEEP_0>;
 158                         #cooling-cells = <2>;
 159                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 160                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 161                         clock-names = "cpu", "intermediate";
 162                         operating-points-v2 = <&cluster0_opp>;
 163                 };
 164
 165                 cpu1: cpu@1 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a53";
 168                         reg = <0x001>;
 169                         enable-method = "psci";
 170                         cpu-idle-states = <&CPU_SLEEP_0>;
 171                         clocks = <&infracfg CLK_INFRA_CA53SEL>,
 172                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 173                         clock-names = "cpu", "intermediate";
 174                         operating-points-v2 = <&cluster0_opp>;
 175                 };
 176
 177                 cpu2: cpu@100 {
 178                         device_type = "cpu";
 179                         compatible = "arm,cortex-a57";
 180                         reg = <0x100>;
 181                         enable-method = "psci";
 182                         cpu-idle-states = <&CPU_SLEEP_0>;
 183                         #cooling-cells = <2>;
 184                         clocks = <&infracfg CLK_INFRA_CA57SEL>,
 185                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 186                         clock-names = "cpu", "intermediate";
 187                         operating-points-v2 = <&cluster1_opp>;
 188                 };
 189
 190                 cpu3: cpu@101 {
 191                         device_type = "cpu";
 192                         compatible = "arm,cortex-a57";
 193                         reg = <0x101>;
 194                         enable-method = "psci";
 195                         cpu-idle-states = <&CPU_SLEEP_0>;
 196                         clocks = <&infracfg CLK_INFRA_CA57SEL>,
 197                                  <&apmixedsys CLK_APMIXED_MAINPLL>;
 198                         clock-names = "cpu", "intermediate";
 199                         operating-points-v2 = <&cluster1_opp>;
 200                 };
 201
 202                 idle-states {
 203                         entry-method = "psci";
 204
 205                         CPU_SLEEP_0: cpu-sleep-0 {
 206                                 compatible = "arm,idle-state";
 207                                 local-timer-stop;
 208                                 entry-latency-us = <639>;
 209                                 exit-latency-us = <680>;
 210                                 min-residency-us = <1088>;
 211                                 arm,psci-suspend-param = <0x0010000>;
 212                         };
 213                 };
 214         };
 215
 216         psci {
 217                 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
 218                 method = "smc";
 219                 cpu_suspend   = <0x84000001>;
 220                 cpu_off       = <0x84000002>;
 221                 cpu_on        = <0x84000003>;
 222         };
 223
 224         clk26m: oscillator@0 {
 225                 compatible = "fixed-clock";
 226                 #clock-cells = <0>;
 227                 clock-frequency = <26000000>;
 228                 clock-output-names = "clk26m";
 229         };
 230
 231         clk32k: oscillator@1 {
 232                 compatible = "fixed-clock";
 233                 #clock-cells = <0>;
 234                 clock-frequency = <32000>;
 235                 clock-output-names = "clk32k";
 236         };
 237
 238         cpum_ck: oscillator@2 {
 239                 compatible = "fixed-clock";
 240                 #clock-cells = <0>;
 241                 clock-frequency = <0>;
 242                 clock-output-names = "cpum_ck";
 243         };
 244
 245         thermal-zones {
 246                 cpu_thermal: cpu_thermal {
 247                         polling-delay-passive = <1000>; /* milliseconds */
 248                         polling-delay = <1000>; /* milliseconds */
 249
 250                         thermal-sensors = <&thermal>;
 251                         sustainable-power = <1500>; /* milliwatts */
 252
 253                         trips {
 254                                 threshold: trip-point@0 {
 255                                         temperature = <68000>;
 256                                         hysteresis = <2000>;
 257                                         type = "passive";
 258                                 };
 259
 260                                 target: trip-point@1 {
 261                                         temperature = <85000>;
 262                                         hysteresis = <2000>;
 263                                         type = "passive";
 264                                 };
 265
 266                                 cpu_crit: cpu_crit@0 {
 267                                         temperature = <115000>;
 268                                         hysteresis = <2000>;
 269                                         type = "critical";
 270                                 };
 271                         };
 272
 273                         cooling-maps {
 274                                 map@0 {
 275                                         trip = <&target>;
 276                                         cooling-device = <&cpu0 0 0>;
 277                                         contribution = <3072>;
 278                                 };
 279                                 map@1 {
 280                                         trip = <&target>;
 281                                         cooling-device = <&cpu2 0 0>;
 282                                         contribution = <1024>;
 283                                 };
 284                         };
 285                 };
 286         };
 287
 288         reserved-memory {
 289                 #address-cells = <2>;
 290                 #size-cells = <2>;
 291                 ranges;
 292                 vpu_dma_reserved: vpu_dma_mem_region {
 293                         compatible = "shared-dma-pool";
 294                         reg = <0 0xb7000000 0 0x500000>;
 295                         alignment = <0x1000>;
 296                         no-map;
 297                 };
 298         };
 299
 300         timer {
 301                 compatible = "arm,armv8-timer";
 302                 interrupt-parent = <&gic>;
 303                 interrupts = <GIC_PPI 13
 304                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 305                              <GIC_PPI 14
 306                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 307                              <GIC_PPI 11
 308                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 309                              <GIC_PPI 10
 310                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 311         };
 312
 313         soc {
 314                 #address-cells = <2>;
 315                 #size-cells = <2>;
 316                 compatible = "simple-bus";
 317                 ranges;
 318
 319                 topckgen: clock-controller@10000000 {
 320                         compatible = "mediatek,mt8173-topckgen";
 321                         reg = <0 0x10000000 0 0x1000>;
 322                         #clock-cells = <1>;
 323                 };
 324
 325                 infracfg: power-controller@10001000 {
 326                         compatible = "mediatek,mt8173-infracfg", "syscon";
 327                         reg = <0 0x10001000 0 0x1000>;
 328                         #clock-cells = <1>;
 329                         #reset-cells = <1>;
 330                 };
 331
 332                 pericfg: power-controller@10003000 {
 333                         compatible = "mediatek,mt8173-pericfg", "syscon";
 334                         reg = <0 0x10003000 0 0x1000>;
 335                         #clock-cells = <1>;
 336                         #reset-cells = <1>;
 337                 };
 338
 339                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 340                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 341                         reg = <0 0x10005000 0 0x1000>;
 342                 };
 343
 344                 pio: pinctrl@0x10005000 {
 345                         compatible = "mediatek,mt8173-pinctrl";
 346                         reg = <0 0x1000b000 0 0x1000>;
 347                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 348                         pins-are-numbered;
 349                         gpio-controller;
 350                         #gpio-cells = <2>;
 351                         interrupt-controller;
 352                         #interrupt-cells = <2>;
 353                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 354                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 355                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 356
 357                         hdmi_pin: xxx {
 358
 359                                 /*hdmi htplg pin*/
 360                                 pins1 {
 361                                         pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
 362                                         input-enable;
 363                                         bias-pull-down;
 364                                 };
 365                         };
 366
 367                         i2c0_pins_a: i2c0 {
 368                                 pins1 {
 369                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 370                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 371                                         bias-disable;
 372                                 };
 373                         };
 374
 375                         i2c1_pins_a: i2c1 {
 376                                 pins1 {
 377                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 378                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 379                                         bias-disable;
 380                                 };
 381                         };
 382
 383                         i2c2_pins_a: i2c2 {
 384                                 pins1 {
 385                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 386                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 387                                         bias-disable;
 388                                 };
 389                         };
 390
 391                         i2c3_pins_a: i2c3 {
 392                                 pins1 {
 393                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 394                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 395                                         bias-disable;
 396                                 };
 397                         };
 398
 399                         i2c4_pins_a: i2c4 {
 400                                 pins1 {
 401                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 402                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 403                                         bias-disable;
 404                                 };
 405                         };
 406
 407                         i2c6_pins_a: i2c6 {
 408                                 pins1 {
 409                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 410                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 411                                         bias-disable;
 412                                 };
 413                         };
 414                 };
 415
 416                 scpsys: scpsys@10006000 {
 417                         compatible = "mediatek,mt8173-scpsys";
 418                         #power-domain-cells = <1>;
 419                         reg = <0 0x10006000 0 0x1000>;
 420                         clocks = <&clk26m>,
 421                                  <&topckgen CLK_TOP_MM_SEL>,
 422                                  <&topckgen CLK_TOP_VENC_SEL>,
 423                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 424                         clock-names = "mfg", "mm", "venc", "venc_lt";
 425                         infracfg = <&infracfg>;
 426                 };
 427
 428                 watchdog: watchdog@10007000 {
 429                         compatible = "mediatek,mt8173-wdt",
 430                                      "mediatek,mt6589-wdt";
 431                         reg = <0 0x10007000 0 0x100>;
 432                 };
 433
 434                 timer: timer@10008000 {
 435                         compatible = "mediatek,mt8173-timer",
 436                                      "mediatek,mt6577-timer";
 437                         reg = <0 0x10008000 0 0x1000>;
 438                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
 439                         clocks = <&infracfg CLK_INFRA_CLK_13M>,
 440                                  <&topckgen CLK_TOP_RTC_SEL>;
 441                 };
 442
 443                 pwrap: pwrap@1000d000 {
 444                         compatible = "mediatek,mt8173-pwrap";
 445                         reg = <0 0x1000d000 0 0x1000>;
 446                         reg-names = "pwrap";
 447                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 448                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 449                         reset-names = "pwrap";
 450                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 451                         clock-names = "spi", "wrap";
 452                 };
 453
 454                 cec: cec@10013000 {
 455                         compatible = "mediatek,mt8173-cec";
 456                         reg = <0 0x10013000 0 0xbc>;
 457                         interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
 458                         clocks = <&infracfg CLK_INFRA_CEC>;
 459                         status = "disabled";
 460                 };
 461
 462                 vpu: vpu@10020000 {
 463                         compatible = "mediatek,mt8173-vpu";
 464                         reg = <0 0x10020000 0 0x30000>,
 465                               <0 0x10050000 0 0x100>;
 466                         reg-names = "tcm", "cfg_reg";
 467                         interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
 468                         clocks = <&topckgen CLK_TOP_SCP_SEL>;
 469                         clock-names = "main";
 470                         memory-region = <&vpu_dma_reserved>;
 471                 };
 472
 473                 sysirq: intpol-controller@10200620 {
 474                         compatible = "mediatek,mt8173-sysirq",
 475                                      "mediatek,mt6577-sysirq";
 476                         interrupt-controller;
 477                         #interrupt-cells = <3>;
 478                         interrupt-parent = <&gic>;
 479                         reg = <0 0x10200620 0 0x20>;
 480                 };
 481
 482                 iommu: iommu@10205000 {
 483                         compatible = "mediatek,mt8173-m4u";
 484                         reg = <0 0x10205000 0 0x1000>;
 485                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
 486                         clocks = <&infracfg CLK_INFRA_M4U>;
 487                         clock-names = "bclk";
 488                         mediatek,larbs = <&larb0 &larb1 &larb2
 489                                           &larb3 &larb4 &larb5>;
 490                         #iommu-cells = <1>;
 491                 };
 492
 493                 efuse: efuse@10206000 {
 494                         compatible = "mediatek,mt8173-efuse";
 495                         reg = <0 0x10206000 0 0x1000>;
 496                         #address-cells = <1>;
 497                         #size-cells = <1>;
 498                         thermal_calibration: calib@528 {
 499                                 reg = <0x528 0xc>;
 500                         };
 501                 };
 502
 503                 apmixedsys: clock-controller@10209000 {
 504                         compatible = "mediatek,mt8173-apmixedsys";
 505                         reg = <0 0x10209000 0 0x1000>;
 506                         #clock-cells = <1>;
 507                 };
 508
 509                 hdmi_phy: hdmi-phy@10209100 {
 510                         compatible = "mediatek,mt8173-hdmi-phy";
 511                         reg = <0 0x10209100 0 0x24>;
 512                         clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
 513                         clock-names = "pll_ref";
 514                         clock-output-names = "hdmitx_dig_cts";
 515                         mediatek,ibias = <0xa>;
 516                         mediatek,ibias_up = <0x1c>;
 517                         #clock-cells = <0>;
 518                         #phy-cells = <0>;
 519                         status = "disabled";
 520                 };
 521
 522                 mipi_tx0: mipi-dphy@10215000 {
 523                         compatible = "mediatek,mt8173-mipi-tx";
 524                         reg = <0 0x10215000 0 0x1000>;
 525                         clocks = <&clk26m>;
 526                         clock-output-names = "mipi_tx0_pll";
 527                         #clock-cells = <0>;
 528                         #phy-cells = <0>;
 529                         status = "disabled";
 530                 };
 531
 532                 mipi_tx1: mipi-dphy@10216000 {
 533                         compatible = "mediatek,mt8173-mipi-tx";
 534                         reg = <0 0x10216000 0 0x1000>;
 535                         clocks = <&clk26m>;
 536                         clock-output-names = "mipi_tx1_pll";
 537                         #clock-cells = <0>;
 538                         #phy-cells = <0>;
 539                         status = "disabled";
 540                 };
 541
 542                 gic: interrupt-controller@10220000 {
 543                         compatible = "arm,gic-400";
 544                         #interrupt-cells = <3>;
 545                         interrupt-parent = <&gic>;
 546                         interrupt-controller;
 547                         reg = <0 0x10221000 0 0x1000>,
 548                               <0 0x10222000 0 0x2000>,
 549                               <0 0x10224000 0 0x2000>,
 550                               <0 0x10226000 0 0x2000>;
 551                         interrupts = <GIC_PPI 9
 552                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 553                 };
 554
 555                 auxadc: auxadc@11001000 {
 556                         compatible = "mediatek,mt8173-auxadc";
 557                         reg = <0 0x11001000 0 0x1000>;
 558                         clocks = <&pericfg CLK_PERI_AUXADC>;
 559                         clock-names = "main";
 560                         #io-channel-cells = <1>;
 561                 };
 562
 563                 uart0: serial@11002000 {
 564                         compatible = "mediatek,mt8173-uart",
 565                                      "mediatek,mt6577-uart";
 566                         reg = <0 0x11002000 0 0x400>;
 567                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 568                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 569                         clock-names = "baud", "bus";
 570                         status = "disabled";
 571                 };
 572
 573                 uart1: serial@11003000 {
 574                         compatible = "mediatek,mt8173-uart",
 575                                      "mediatek,mt6577-uart";
 576                         reg = <0 0x11003000 0 0x400>;
 577                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 578                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 579                         clock-names = "baud", "bus";
 580                         status = "disabled";
 581                 };
 582
 583                 uart2: serial@11004000 {
 584                         compatible = "mediatek,mt8173-uart",
 585                                      "mediatek,mt6577-uart";
 586                         reg = <0 0x11004000 0 0x400>;
 587                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 588                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 589                         clock-names = "baud", "bus";
 590                         status = "disabled";
 591                 };
 592
 593                 uart3: serial@11005000 {
 594                         compatible = "mediatek,mt8173-uart",
 595                                      "mediatek,mt6577-uart";
 596                         reg = <0 0x11005000 0 0x400>;
 597                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 598                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 599                         clock-names = "baud", "bus";
 600                         status = "disabled";
 601                 };
 602
 603                 i2c0: i2c@11007000 {
 604                         compatible = "mediatek,mt8173-i2c";
 605                         reg = <0 0x11007000 0 0x70>,
 606                               <0 0x11000100 0 0x80>;
 607                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 608                         clock-div = <16>;
 609                         clocks = <&pericfg CLK_PERI_I2C0>,
 610                                  <&pericfg CLK_PERI_AP_DMA>;
 611                         clock-names = "main", "dma";
 612                         pinctrl-names = "default";
 613                         pinctrl-0 = <&i2c0_pins_a>;
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                         status = "disabled";
 617                 };
 618
 619                 i2c1: i2c@11008000 {
 620                         compatible = "mediatek,mt8173-i2c";
 621                         reg = <0 0x11008000 0 0x70>,
 622                               <0 0x11000180 0 0x80>;
 623                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 624                         clock-div = <16>;
 625                         clocks = <&pericfg CLK_PERI_I2C1>,
 626                                  <&pericfg CLK_PERI_AP_DMA>;
 627                         clock-names = "main", "dma";
 628                         pinctrl-names = "default";
 629                         pinctrl-0 = <&i2c1_pins_a>;
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632                         status = "disabled";
 633                 };
 634
 635                 i2c2: i2c@11009000 {
 636                         compatible = "mediatek,mt8173-i2c";
 637                         reg = <0 0x11009000 0 0x70>,
 638                               <0 0x11000200 0 0x80>;
 639                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 640                         clock-div = <16>;
 641                         clocks = <&pericfg CLK_PERI_I2C2>,
 642                                  <&pericfg CLK_PERI_AP_DMA>;
 643                         clock-names = "main", "dma";
 644                         pinctrl-names = "default";
 645                         pinctrl-0 = <&i2c2_pins_a>;
 646                         #address-cells = <1>;
 647                         #size-cells = <0>;
 648                         status = "disabled";
 649                 };
 650
 651                 spi: spi@1100a000 {
 652                         compatible = "mediatek,mt8173-spi";
 653                         #address-cells = <1>;
 654                         #size-cells = <0>;
 655                         reg = <0 0x1100a000 0 0x1000>;
 656                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 657                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 658                                  <&topckgen CLK_TOP_SPI_SEL>,
 659                                  <&pericfg CLK_PERI_SPI0>;
 660                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 661                         status = "disabled";
 662                 };
 663
 664                 thermal: thermal@1100b000 {
 665                         #thermal-sensor-cells = <0>;
 666                         compatible = "mediatek,mt8173-thermal";
 667                         reg = <0 0x1100b000 0 0x1000>;
 668                         interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
 669                         clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
 670                         clock-names = "therm", "auxadc";
 671                         resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
 672                         mediatek,auxadc = <&auxadc>;
 673                         mediatek,apmixedsys = <&apmixedsys>;
 674                         nvmem-cells = <&thermal_calibration>;
 675                         nvmem-cell-names = "calibration-data";
 676                 };
 677
 678                 nor_flash: spi@1100d000 {
 679                         compatible = "mediatek,mt8173-nor";
 680                         reg = <0 0x1100d000 0 0xe0>;
 681                         clocks = <&pericfg CLK_PERI_SPI>,
 682                                  <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
 683                         clock-names = "spi", "sf";
 684                         #address-cells = <1>;
 685                         #size-cells = <0>;
 686                         status = "disabled";
 687                 };
 688
 689                 i2c3: i2c@11010000 {
 690                         compatible = "mediatek,mt8173-i2c";
 691                         reg = <0 0x11010000 0 0x70>,
 692                               <0 0x11000280 0 0x80>;
 693                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 694                         clock-div = <16>;
 695                         clocks = <&pericfg CLK_PERI_I2C3>,
 696                                  <&pericfg CLK_PERI_AP_DMA>;
 697                         clock-names = "main", "dma";
 698                         pinctrl-names = "default";
 699                         pinctrl-0 = <&i2c3_pins_a>;
 700                         #address-cells = <1>;
 701                         #size-cells = <0>;
 702                         status = "disabled";
 703                 };
 704
 705                 i2c4: i2c@11011000 {
 706                         compatible = "mediatek,mt8173-i2c";
 707                         reg = <0 0x11011000 0 0x70>,
 708                               <0 0x11000300 0 0x80>;
 709                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 710                         clock-div = <16>;
 711                         clocks = <&pericfg CLK_PERI_I2C4>,
 712                                  <&pericfg CLK_PERI_AP_DMA>;
 713                         clock-names = "main", "dma";
 714                         pinctrl-names = "default";
 715                         pinctrl-0 = <&i2c4_pins_a>;
 716                         #address-cells = <1>;
 717                         #size-cells = <0>;
 718                         status = "disabled";
 719                 };
 720
 721                 hdmiddc0: i2c@11012000 {
 722                         compatible = "mediatek,mt8173-hdmi-ddc";
 723                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 724                         reg = <0 0x11012000 0 0x1C>;
 725                         clocks = <&pericfg CLK_PERI_I2C5>;
 726                         clock-names = "ddc-i2c";
 727                 };
 728
 729                 i2c6: i2c@11013000 {
 730                         compatible = "mediatek,mt8173-i2c";
 731                         reg = <0 0x11013000 0 0x70>,
 732                               <0 0x11000080 0 0x80>;
 733                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 734                         clock-div = <16>;
 735                         clocks = <&pericfg CLK_PERI_I2C6>,
 736                                  <&pericfg CLK_PERI_AP_DMA>;
 737                         clock-names = "main", "dma";
 738                         pinctrl-names = "default";
 739                         pinctrl-0 = <&i2c6_pins_a>;
 740                         #address-cells = <1>;
 741                         #size-cells = <0>;
 742                         status = "disabled";
 743                 };
 744
 745                 afe: audio-controller@11220000  {
 746                         compatible = "mediatek,mt8173-afe-pcm";
 747                         reg = <0 0x11220000 0 0x1000>;
 748                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 749                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 750                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 751                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 752                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 753                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 754                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 755                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 756                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 757                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 758                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 759                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 760                         clock-names = "infra_sys_audio_clk",
 761                                       "top_pdn_audio",
 762                                       "top_pdn_aud_intbus",
 763                                       "bck0",
 764                                       "bck1",
 765                                       "i2s0_m",
 766                                       "i2s1_m",
 767                                       "i2s2_m",
 768                                       "i2s3_m",
 769                                       "i2s3_b";
 770                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 771                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 772                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 773                                                  <&topckgen CLK_TOP_APLL2>;
 774                 };
 775
 776                 mmc0: mmc@11230000 {
 777                         compatible = "mediatek,mt8173-mmc";
 778                         reg = <0 0x11230000 0 0x1000>;
 779                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 780                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 781                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 782                         clock-names = "source", "hclk";
 783                         status = "disabled";
 784                 };
 785
 786                 mmc1: mmc@11240000 {
 787                         compatible = "mediatek,mt8173-mmc";
 788                         reg = <0 0x11240000 0 0x1000>;
 789                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 790                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 791                                  <&topckgen CLK_TOP_AXI_SEL>;
 792                         clock-names = "source", "hclk";
 793                         status = "disabled";
 794                 };
 795
 796                 mmc2: mmc@11250000 {
 797                         compatible = "mediatek,mt8173-mmc";
 798                         reg = <0 0x11250000 0 0x1000>;
 799                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 800                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 801                                  <&topckgen CLK_TOP_AXI_SEL>;
 802                         clock-names = "source", "hclk";
 803                         status = "disabled";
 804                 };
 805
 806                 mmc3: mmc@11260000 {
 807                         compatible = "mediatek,mt8173-mmc";
 808                         reg = <0 0x11260000 0 0x1000>;
 809                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 810                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 811                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 812                         clock-names = "source", "hclk";
 813                         status = "disabled";
 814                 };
 815
 816                 ssusb: usb@11271000 {
 817                         compatible = "mediatek,mt8173-mtu3";
 818                         reg = <0 0x11271000 0 0x3000>,
 819                               <0 0x11280700 0 0x0100>;
 820                         reg-names = "mac", "ippc";
 821                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
 822                         phys = <&u2port0 PHY_TYPE_USB2>,
 823                                <&u3port0 PHY_TYPE_USB3>,
 824                                <&u2port1 PHY_TYPE_USB2>;
 825                         power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 826                         clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 827                         clock-names = "sys_ck", "ref_ck";
 828                         mediatek,syscon-wakeup = <&pericfg 0x400 1>;
 829                         #address-cells = <2>;
 830                         #size-cells = <2>;
 831                         ranges;
 832                         status = "disabled";
 833
 834                         usb_host: xhci@11270000 {
 835                                 compatible = "mediatek,mt8173-xhci";
 836                                 reg = <0 0x11270000 0 0x1000>;
 837                                 reg-names = "mac";
 838                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
 839                                 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
 840                                 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
 841                                 clock-names = "sys_ck", "ref_ck";
 842                                 status = "disabled";
 843                         };
 844                 };
 845
 846                 u3phy: usb-phy@11290000 {
 847                         compatible = "mediatek,mt8173-u3phy";
 848                         reg = <0 0x11290000 0 0x800>;
 849                         #address-cells = <2>;
 850                         #size-cells = <2>;
 851                         ranges;
 852                         status = "okay";
 853
 854                         u2port0: usb-phy@11290800 {
 855                                 reg = <0 0x11290800 0 0x100>;
 856                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 857                                 clock-names = "ref";
 858                                 #phy-cells = <1>;
 859                                 status = "okay";
 860                         };
 861
 862                         u3port0: usb-phy@11290900 {
 863                                 reg = <0 0x11290900 0 0x700>;
 864                                 clocks = <&clk26m>;
 865                                 clock-names = "ref";
 866                                 #phy-cells = <1>;
 867                                 status = "okay";
 868                         };
 869
 870                         u2port1: usb-phy@11291000 {
 871                                 reg = <0 0x11291000 0 0x100>;
 872                                 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
 873                                 clock-names = "ref";
 874                                 #phy-cells = <1>;
 875                                 status = "okay";
 876                         };
 877                 };
 878
 879                 mmsys: clock-controller@14000000 {
 880                         compatible = "mediatek,mt8173-mmsys", "syscon";
 881                         reg = <0 0x14000000 0 0x1000>;
 882                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 883                         assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
 884                         assigned-clock-rates = <400000000>;
 885                         #clock-cells = <1>;
 886                 };
 887
 888                 mdp_rdma0: rdma@14001000 {
 889                         compatible = "mediatek,mt8173-mdp-rdma",
 890                                      "mediatek,mt8173-mdp";
 891                         reg = <0 0x14001000 0 0x1000>;
 892                         clocks = <&mmsys CLK_MM_MDP_RDMA0>,
 893                                  <&mmsys CLK_MM_MUTEX_32K>;
 894                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 895                         iommus = <&iommu M4U_PORT_MDP_RDMA0>;
 896                         mediatek,larb = <&larb0>;
 897                         mediatek,vpu = <&vpu>;
 898                 };
 899
 900                 mdp_rdma1: rdma@14002000 {
 901                         compatible = "mediatek,mt8173-mdp-rdma";
 902                         reg = <0 0x14002000 0 0x1000>;
 903                         clocks = <&mmsys CLK_MM_MDP_RDMA1>,
 904                                  <&mmsys CLK_MM_MUTEX_32K>;
 905                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 906                         iommus = <&iommu M4U_PORT_MDP_RDMA1>;
 907                         mediatek,larb = <&larb4>;
 908                 };
 909
 910                 mdp_rsz0: rsz@14003000 {
 911                         compatible = "mediatek,mt8173-mdp-rsz";
 912                         reg = <0 0x14003000 0 0x1000>;
 913                         clocks = <&mmsys CLK_MM_MDP_RSZ0>;
 914                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 915                 };
 916
 917                 mdp_rsz1: rsz@14004000 {
 918                         compatible = "mediatek,mt8173-mdp-rsz";
 919                         reg = <0 0x14004000 0 0x1000>;
 920                         clocks = <&mmsys CLK_MM_MDP_RSZ1>;
 921                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 922                 };
 923
 924                 mdp_rsz2: rsz@14005000 {
 925                         compatible = "mediatek,mt8173-mdp-rsz";
 926                         reg = <0 0x14005000 0 0x1000>;
 927                         clocks = <&mmsys CLK_MM_MDP_RSZ2>;
 928                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 929                 };
 930
 931                 mdp_wdma0: wdma@14006000 {
 932                         compatible = "mediatek,mt8173-mdp-wdma";
 933                         reg = <0 0x14006000 0 0x1000>;
 934                         clocks = <&mmsys CLK_MM_MDP_WDMA>;
 935                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 936                         iommus = <&iommu M4U_PORT_MDP_WDMA>;
 937                         mediatek,larb = <&larb0>;
 938                 };
 939
 940                 mdp_wrot0: wrot@14007000 {
 941                         compatible = "mediatek,mt8173-mdp-wrot";
 942                         reg = <0 0x14007000 0 0x1000>;
 943                         clocks = <&mmsys CLK_MM_MDP_WROT0>;
 944                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 945                         iommus = <&iommu M4U_PORT_MDP_WROT0>;
 946                         mediatek,larb = <&larb0>;
 947                 };
 948
 949                 mdp_wrot1: wrot@14008000 {
 950                         compatible = "mediatek,mt8173-mdp-wrot";
 951                         reg = <0 0x14008000 0 0x1000>;
 952                         clocks = <&mmsys CLK_MM_MDP_WROT1>;
 953                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 954                         iommus = <&iommu M4U_PORT_MDP_WROT1>;
 955                         mediatek,larb = <&larb4>;
 956                 };
 957
 958                 ovl0: ovl@1400c000 {
 959                         compatible = "mediatek,mt8173-disp-ovl";
 960                         reg = <0 0x1400c000 0 0x1000>;
 961                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
 962                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 963                         clocks = <&mmsys CLK_MM_DISP_OVL0>;
 964                         iommus = <&iommu M4U_PORT_DISP_OVL0>;
 965                         mediatek,larb = <&larb0>;
 966                 };
 967
 968                 ovl1: ovl@1400d000 {
 969                         compatible = "mediatek,mt8173-disp-ovl";
 970                         reg = <0 0x1400d000 0 0x1000>;
 971                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
 972                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 973                         clocks = <&mmsys CLK_MM_DISP_OVL1>;
 974                         iommus = <&iommu M4U_PORT_DISP_OVL1>;
 975                         mediatek,larb = <&larb4>;
 976                 };
 977
 978                 rdma0: rdma@1400e000 {
 979                         compatible = "mediatek,mt8173-disp-rdma";
 980                         reg = <0 0x1400e000 0 0x1000>;
 981                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
 982                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 983                         clocks = <&mmsys CLK_MM_DISP_RDMA0>;
 984                         iommus = <&iommu M4U_PORT_DISP_RDMA0>;
 985                         mediatek,larb = <&larb0>;
 986                 };
 987
 988                 rdma1: rdma@1400f000 {
 989                         compatible = "mediatek,mt8173-disp-rdma";
 990                         reg = <0 0x1400f000 0 0x1000>;
 991                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
 992                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 993                         clocks = <&mmsys CLK_MM_DISP_RDMA1>;
 994                         iommus = <&iommu M4U_PORT_DISP_RDMA1>;
 995                         mediatek,larb = <&larb4>;
 996                 };
 997
 998                 rdma2: rdma@14010000 {
 999                         compatible = "mediatek,mt8173-disp-rdma";
1000                         reg = <0 0x14010000 0 0x1000>;
1001                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
1002                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1003                         clocks = <&mmsys CLK_MM_DISP_RDMA2>;
1004                         iommus = <&iommu M4U_PORT_DISP_RDMA2>;
1005                         mediatek,larb = <&larb4>;
1006                 };
1007
1008                 wdma0: wdma@14011000 {
1009                         compatible = "mediatek,mt8173-disp-wdma";
1010                         reg = <0 0x14011000 0 0x1000>;
1011                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
1012                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1013                         clocks = <&mmsys CLK_MM_DISP_WDMA0>;
1014                         iommus = <&iommu M4U_PORT_DISP_WDMA0>;
1015                         mediatek,larb = <&larb0>;
1016                 };
1017
1018                 wdma1: wdma@14012000 {
1019                         compatible = "mediatek,mt8173-disp-wdma";
1020                         reg = <0 0x14012000 0 0x1000>;
1021                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
1022                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1023                         clocks = <&mmsys CLK_MM_DISP_WDMA1>;
1024                         iommus = <&iommu M4U_PORT_DISP_WDMA1>;
1025                         mediatek,larb = <&larb4>;
1026                 };
1027
1028                 color0: color@14013000 {
1029                         compatible = "mediatek,mt8173-disp-color";
1030                         reg = <0 0x14013000 0 0x1000>;
1031                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
1032                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1033                         clocks = <&mmsys CLK_MM_DISP_COLOR0>;
1034                 };
1035
1036                 color1: color@14014000 {
1037                         compatible = "mediatek,mt8173-disp-color";
1038                         reg = <0 0x14014000 0 0x1000>;
1039                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
1040                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1041                         clocks = <&mmsys CLK_MM_DISP_COLOR1>;
1042                 };
1043
1044                 aal@14015000 {
1045                         compatible = "mediatek,mt8173-disp-aal";
1046                         reg = <0 0x14015000 0 0x1000>;
1047                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
1048                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1049                         clocks = <&mmsys CLK_MM_DISP_AAL>;
1050                 };
1051
1052                 gamma@14016000 {
1053                         compatible = "mediatek,mt8173-disp-gamma";
1054                         reg = <0 0x14016000 0 0x1000>;
1055                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
1056                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1057                         clocks = <&mmsys CLK_MM_DISP_GAMMA>;
1058                 };
1059
1060                 merge@14017000 {
1061                         compatible = "mediatek,mt8173-disp-merge";
1062                         reg = <0 0x14017000 0 0x1000>;
1063                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1064                         clocks = <&mmsys CLK_MM_DISP_MERGE>;
1065                 };
1066
1067                 split0: split@14018000 {
1068                         compatible = "mediatek,mt8173-disp-split";
1069                         reg = <0 0x14018000 0 0x1000>;
1070                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1071                         clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
1072                 };
1073
1074                 split1: split@14019000 {
1075                         compatible = "mediatek,mt8173-disp-split";
1076                         reg = <0 0x14019000 0 0x1000>;
1077                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1078                         clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
1079                 };
1080
1081                 ufoe@1401a000 {
1082                         compatible = "mediatek,mt8173-disp-ufoe";
1083                         reg = <0 0x1401a000 0 0x1000>;
1084                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
1085                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1086                         clocks = <&mmsys CLK_MM_DISP_UFOE>;
1087                 };
1088
1089                 dsi0: dsi@1401b000 {
1090                         compatible = "mediatek,mt8173-dsi";
1091                         reg = <0 0x1401b000 0 0x1000>;
1092                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1093                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1094                         clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1095                                  <&mmsys CLK_MM_DSI0_DIGITAL>,
1096                                  <&mipi_tx0>;
1097                         clock-names = "engine", "digital", "hs";
1098                         phys = <&mipi_tx0>;
1099                         phy-names = "dphy";
1100                         status = "disabled";
1101                 };
1102
1103                 dsi1: dsi@1401c000 {
1104                         compatible = "mediatek,mt8173-dsi";
1105                         reg = <0 0x1401c000 0 0x1000>;
1106                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1107                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1108                         clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1109                                  <&mmsys CLK_MM_DSI1_DIGITAL>,
1110                                  <&mipi_tx1>;
1111                         clock-names = "engine", "digital", "hs";
1112                         phy = <&mipi_tx1>;
1113                         phy-names = "dphy";
1114                         status = "disabled";
1115                 };
1116
1117                 dpi0: dpi@1401d000 {
1118                         compatible = "mediatek,mt8173-dpi";
1119                         reg = <0 0x1401d000 0 0x1000>;
1120                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1121                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1122                         clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1123                                  <&mmsys CLK_MM_DPI_ENGINE>,
1124                                  <&apmixedsys CLK_APMIXED_TVDPLL>;
1125                         clock-names = "pixel", "engine", "pll";
1126                         status = "disabled";
1127
1128                         port {
1129                                 dpi0_out: endpoint {
1130                                         remote-endpoint = <&hdmi0_in>;
1131                                 };
1132                         };
1133                 };
1134
1135                 pwm0: pwm@1401e000 {
1136                         compatible = "mediatek,mt8173-disp-pwm",
1137                                      "mediatek,mt6595-disp-pwm";
1138                         reg = <0 0x1401e000 0 0x1000>;
1139                         #pwm-cells = <2>;
1140                         clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1141                                  <&mmsys CLK_MM_DISP_PWM0MM>;
1142                         clock-names = "main", "mm";
1143                         status = "disabled";
1144                 };
1145
1146                 pwm1: pwm@1401f000 {
1147                         compatible = "mediatek,mt8173-disp-pwm",
1148                                      "mediatek,mt6595-disp-pwm";
1149                         reg = <0 0x1401f000 0 0x1000>;
1150                         #pwm-cells = <2>;
1151                         clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1152                                  <&mmsys CLK_MM_DISP_PWM1MM>;
1153                         clock-names = "main", "mm";
1154                         status = "disabled";
1155                 };
1156
1157                 mutex: mutex@14020000 {
1158                         compatible = "mediatek,mt8173-disp-mutex";
1159                         reg = <0 0x14020000 0 0x1000>;
1160                         interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1161                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1162                         clocks = <&mmsys CLK_MM_MUTEX_32K>;
1163                 };
1164
1165                 larb0: larb@14021000 {
1166                         compatible = "mediatek,mt8173-smi-larb";
1167                         reg = <0 0x14021000 0 0x1000>;
1168                         mediatek,smi = <&smi_common>;
1169                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1170                         clocks = <&mmsys CLK_MM_SMI_LARB0>,
1171                                  <&mmsys CLK_MM_SMI_LARB0>;
1172                         clock-names = "apb", "smi";
1173                 };
1174
1175                 smi_common: smi@14022000 {
1176                         compatible = "mediatek,mt8173-smi-common";
1177                         reg = <0 0x14022000 0 0x1000>;
1178                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1179                         clocks = <&mmsys CLK_MM_SMI_COMMON>,
1180                                  <&mmsys CLK_MM_SMI_COMMON>;
1181                         clock-names = "apb", "smi";
1182                 };
1183
1184                 od@14023000 {
1185                         compatible = "mediatek,mt8173-disp-od";
1186                         reg = <0 0x14023000 0 0x1000>;
1187                         clocks = <&mmsys CLK_MM_DISP_OD>;
1188                 };
1189
1190                 hdmi0: hdmi@14025000 {
1191                         compatible = "mediatek,mt8173-hdmi";
1192                         reg = <0 0x14025000 0 0x400>;
1193                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1194                         clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1195                                  <&mmsys CLK_MM_HDMI_PLLCK>,
1196                                  <&mmsys CLK_MM_HDMI_AUDIO>,
1197                                  <&mmsys CLK_MM_HDMI_SPDIF>;
1198                         clock-names = "pixel", "pll", "bclk", "spdif";
1199                         pinctrl-names = "default";
1200                         pinctrl-0 = <&hdmi_pin>;
1201                         phys = <&hdmi_phy>;
1202                         phy-names = "hdmi";
1203                         mediatek,syscon-hdmi = <&mmsys 0x900>;
1204                         assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1205                         assigned-clock-parents = <&hdmi_phy>;
1206                         status = "disabled";
1207
1208                         ports {
1209                                 #address-cells = <1>;
1210                                 #size-cells = <0>;
1211
1212                                 port@0 {
1213                                         reg = <0>;
1214
1215                                         hdmi0_in: endpoint {
1216                                                 remote-endpoint = <&dpi0_out>;
1217                                         };
1218                                 };
1219                         };
1220                 };
1221
1222                 larb4: larb@14027000 {
1223                         compatible = "mediatek,mt8173-smi-larb";
1224                         reg = <0 0x14027000 0 0x1000>;
1225                         mediatek,smi = <&smi_common>;
1226                         power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1227                         clocks = <&mmsys CLK_MM_SMI_LARB4>,
1228                                  <&mmsys CLK_MM_SMI_LARB4>;
1229                         clock-names = "apb", "smi";
1230                 };
1231
1232                 imgsys: clock-controller@15000000 {
1233                         compatible = "mediatek,mt8173-imgsys", "syscon";
1234                         reg = <0 0x15000000 0 0x1000>;
1235                         #clock-cells = <1>;
1236                 };
1237
1238                 larb2: larb@15001000 {
1239                         compatible = "mediatek,mt8173-smi-larb";
1240                         reg = <0 0x15001000 0 0x1000>;
1241                         mediatek,smi = <&smi_common>;
1242                         power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1243                         clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1244                                  <&imgsys CLK_IMG_LARB2_SMI>;
1245                         clock-names = "apb", "smi";
1246                 };
1247
1248                 vdecsys: clock-controller@16000000 {
1249                         compatible = "mediatek,mt8173-vdecsys", "syscon";
1250                         reg = <0 0x16000000 0 0x1000>;
1251                         #clock-cells = <1>;
1252                 };
1253
1254                 vcodec_dec: vcodec@16000000 {
1255                         compatible = "mediatek,mt8173-vcodec-dec";
1256                         reg = <0 0x16000000 0 0x100>,   /* VDEC_SYS */
1257                               <0 0x16020000 0 0x1000>,  /* VDEC_MISC */
1258                               <0 0x16021000 0 0x800>,   /* VDEC_LD */
1259                               <0 0x16021800 0 0x800>,   /* VDEC_TOP */
1260                               <0 0x16022000 0 0x1000>,  /* VDEC_CM */
1261                               <0 0x16023000 0 0x1000>,  /* VDEC_AD */
1262                               <0 0x16024000 0 0x1000>,  /* VDEC_AV */
1263                               <0 0x16025000 0 0x1000>,  /* VDEC_PP */
1264                               <0 0x16026800 0 0x800>,   /* VDEC_HWD */
1265                               <0 0x16027000 0 0x800>,   /* VDEC_HWQ */
1266                               <0 0x16027800 0 0x800>,   /* VDEC_HWB */
1267                               <0 0x16028400 0 0x400>;   /* VDEC_HWG */
1268                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1269                         mediatek,larb = <&larb1>;
1270                         iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1271                                  <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1272                                  <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1273                                  <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1274                                  <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1275                                  <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1276                                  <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1277                                  <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1278                         mediatek,vpu = <&vpu>;
1279                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1280                         clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1281                                  <&topckgen CLK_TOP_UNIVPLL_D2>,
1282                                  <&topckgen CLK_TOP_CCI400_SEL>,
1283                                  <&topckgen CLK_TOP_VDEC_SEL>,
1284                                  <&topckgen CLK_TOP_VCODECPLL>,
1285                                  <&apmixedsys CLK_APMIXED_VENCPLL>,
1286                                  <&topckgen CLK_TOP_VENC_LT_SEL>,
1287                                  <&topckgen CLK_TOP_VCODECPLL_370P5>;
1288                         clock-names = "vcodecpll",
1289                                       "univpll_d2",
1290                                       "clk_cci400_sel",
1291                                       "vdec_sel",
1292                                       "vdecpll",
1293                                       "vencpll",
1294                                       "venc_lt_sel",
1295                                       "vdec_bus_clk_src";
1296                 };
1297
1298                 larb1: larb@16010000 {
1299                         compatible = "mediatek,mt8173-smi-larb";
1300                         reg = <0 0x16010000 0 0x1000>;
1301                         mediatek,smi = <&smi_common>;
1302                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1303                         clocks = <&vdecsys CLK_VDEC_CKEN>,
1304                                  <&vdecsys CLK_VDEC_LARB_CKEN>;
1305                         clock-names = "apb", "smi";
1306                 };
1307
1308                 vencsys: clock-controller@18000000 {
1309                         compatible = "mediatek,mt8173-vencsys", "syscon";
1310                         reg = <0 0x18000000 0 0x1000>;
1311                         #clock-cells = <1>;
1312                 };
1313
1314                 larb3: larb@18001000 {
1315                         compatible = "mediatek,mt8173-smi-larb";
1316                         reg = <0 0x18001000 0 0x1000>;
1317                         mediatek,smi = <&smi_common>;
1318                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1319                         clocks = <&vencsys CLK_VENC_CKE1>,
1320                                  <&vencsys CLK_VENC_CKE0>;
1321                         clock-names = "apb", "smi";
1322                 };
1323
1324                 vcodec_enc: vcodec@18002000 {
1325                         compatible = "mediatek,mt8173-vcodec-enc";
1326                         reg = <0 0x18002000 0 0x1000>,  /* VENC_SYS */
1327                               <0 0x19002000 0 0x1000>;  /* VENC_LT_SYS */
1328                         interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1329                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1330                         mediatek,larb = <&larb3>,
1331                                         <&larb5>;
1332                         iommus = <&iommu M4U_PORT_VENC_RCPU>,
1333                                  <&iommu M4U_PORT_VENC_REC>,
1334                                  <&iommu M4U_PORT_VENC_BSDMA>,
1335                                  <&iommu M4U_PORT_VENC_SV_COMV>,
1336                                  <&iommu M4U_PORT_VENC_RD_COMV>,
1337                                  <&iommu M4U_PORT_VENC_CUR_LUMA>,
1338                                  <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1339                                  <&iommu M4U_PORT_VENC_REF_LUMA>,
1340                                  <&iommu M4U_PORT_VENC_REF_CHROMA>,
1341                                  <&iommu M4U_PORT_VENC_NBM_RDMA>,
1342                                  <&iommu M4U_PORT_VENC_NBM_WDMA>,
1343                                  <&iommu M4U_PORT_VENC_RCPU_SET2>,
1344                                  <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1345                                  <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1346                                  <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1347                                  <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1348                                  <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1349                                  <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1350                                  <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1351                                  <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1352                         mediatek,vpu = <&vpu>;
1353                         clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1354                                  <&topckgen CLK_TOP_VENC_SEL>,
1355                                  <&topckgen CLK_TOP_UNIVPLL1_D2>,
1356                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
1357                         clock-names = "venc_sel_src",
1358                                       "venc_sel",
1359                                       "venc_lt_sel_src",
1360                                       "venc_lt_sel";
1361                 };
1362
1363                 vencltsys: clock-controller@19000000 {
1364                         compatible = "mediatek,mt8173-vencltsys", "syscon";
1365                         reg = <0 0x19000000 0 0x1000>;
1366                         #clock-cells = <1>;
1367                 };
1368
1369                 larb5: larb@19001000 {
1370                         compatible = "mediatek,mt8173-smi-larb";
1371                         reg = <0 0x19001000 0 0x1000>;
1372                         mediatek,smi = <&smi_common>;
1373                         power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1374                         clocks = <&vencltsys CLK_VENCLT_CKE1>,
1375                                  <&vencltsys CLK_VENCLT_CKE0>;
1376                         clock-names = "apb", "smi";
1377                 };
1378         };
1379 };
1380