2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Eddie Huang <eddie.huang@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <dt-bindings/clock/mt8173-clk.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/memory/mt8173-larb-port.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/power/mt8173-power.h>
20 #include <dt-bindings/reset/mt8173-resets.h>
21 #include "mt8173-pinfunc.h"
24 compatible = "mediatek,mt8173";
25 interrupt-parent = <&sysirq>;
44 mdp_rdma0 = &mdp_rdma0;
45 mdp_rdma1 = &mdp_rdma1;
49 mdp_wdma0 = &mdp_wdma0;
50 mdp_wrot0 = &mdp_wrot0;
51 mdp_wrot1 = &mdp_wrot1;
80 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
96 compatible = "arm,cortex-a57";
98 enable-method = "psci";
99 cpu-idle-states = <&CPU_SLEEP_0>;
104 compatible = "arm,cortex-a57";
106 enable-method = "psci";
107 cpu-idle-states = <&CPU_SLEEP_0>;
111 entry-method = "psci";
113 CPU_SLEEP_0: cpu-sleep-0 {
114 compatible = "arm,idle-state";
116 entry-latency-us = <639>;
117 exit-latency-us = <680>;
118 min-residency-us = <1088>;
119 arm,psci-suspend-param = <0x0010000>;
125 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
127 cpu_suspend = <0x84000001>;
128 cpu_off = <0x84000002>;
129 cpu_on = <0x84000003>;
132 clk26m: oscillator@0 {
133 compatible = "fixed-clock";
135 clock-frequency = <26000000>;
136 clock-output-names = "clk26m";
139 clk32k: oscillator@1 {
140 compatible = "fixed-clock";
142 clock-frequency = <32000>;
143 clock-output-names = "clk32k";
146 cpum_ck: oscillator@2 {
147 compatible = "fixed-clock";
149 clock-frequency = <0>;
150 clock-output-names = "cpum_ck";
154 cpu_thermal: cpu_thermal {
155 polling-delay-passive = <1000>; /* milliseconds */
156 polling-delay = <1000>; /* milliseconds */
158 thermal-sensors = <&thermal>;
159 sustainable-power = <1500>; /* milliwatts */
162 threshold: trip-point@0 {
163 temperature = <68000>;
168 target: trip-point@1 {
169 temperature = <85000>;
174 cpu_crit: cpu_crit@0 {
175 temperature = <115000>;
184 cooling-device = <&cpu0 0 0>;
185 contribution = <3072>;
189 cooling-device = <&cpu2 0 0>;
190 contribution = <1024>;
197 #address-cells = <2>;
200 vpu_dma_reserved: vpu_dma_mem_region {
201 compatible = "shared-dma-pool";
202 reg = <0 0xb7000000 0 0x500000>;
203 alignment = <0x1000>;
209 compatible = "arm,armv8-timer";
210 interrupt-parent = <&gic>;
211 interrupts = <GIC_PPI 13
212 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
214 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
218 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
222 #address-cells = <2>;
224 compatible = "simple-bus";
227 topckgen: clock-controller@10000000 {
228 compatible = "mediatek,mt8173-topckgen";
229 reg = <0 0x10000000 0 0x1000>;
233 infracfg: power-controller@10001000 {
234 compatible = "mediatek,mt8173-infracfg", "syscon";
235 reg = <0 0x10001000 0 0x1000>;
240 pericfg: power-controller@10003000 {
241 compatible = "mediatek,mt8173-pericfg", "syscon";
242 reg = <0 0x10003000 0 0x1000>;
247 syscfg_pctl_a: syscfg_pctl_a@10005000 {
248 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
249 reg = <0 0x10005000 0 0x1000>;
252 pio: pinctrl@0x10005000 {
253 compatible = "mediatek,mt8173-pinctrl";
254 reg = <0 0x1000b000 0 0x1000>;
255 mediatek,pctl-regmap = <&syscfg_pctl_a>;
259 interrupt-controller;
260 #interrupt-cells = <2>;
261 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
269 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
277 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
278 <MT8173_PIN_46_SCL0__FUNC_SCL0>;
285 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
286 <MT8173_PIN_126_SCL1__FUNC_SCL1>;
293 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
294 <MT8173_PIN_44_SCL2__FUNC_SCL2>;
301 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
302 <MT8173_PIN_107_SCL3__FUNC_SCL3>;
309 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
310 <MT8173_PIN_134_SCL4__FUNC_SCL4>;
317 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
318 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
324 scpsys: scpsys@10006000 {
325 compatible = "mediatek,mt8173-scpsys";
326 #power-domain-cells = <1>;
327 reg = <0 0x10006000 0 0x1000>;
329 <&topckgen CLK_TOP_MM_SEL>,
330 <&topckgen CLK_TOP_VENC_SEL>,
331 <&topckgen CLK_TOP_VENC_LT_SEL>;
332 clock-names = "mfg", "mm", "venc", "venc_lt";
333 infracfg = <&infracfg>;
336 watchdog: watchdog@10007000 {
337 compatible = "mediatek,mt8173-wdt",
338 "mediatek,mt6589-wdt";
339 reg = <0 0x10007000 0 0x100>;
342 timer: timer@10008000 {
343 compatible = "mediatek,mt8173-timer",
344 "mediatek,mt6577-timer";
345 reg = <0 0x10008000 0 0x1000>;
346 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
347 clocks = <&infracfg CLK_INFRA_CLK_13M>,
348 <&topckgen CLK_TOP_RTC_SEL>;
351 pwrap: pwrap@1000d000 {
352 compatible = "mediatek,mt8173-pwrap";
353 reg = <0 0x1000d000 0 0x1000>;
355 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
356 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
357 reset-names = "pwrap";
358 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
359 clock-names = "spi", "wrap";
363 compatible = "mediatek,mt8173-cec";
364 reg = <0 0x10013000 0 0xbc>;
365 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
366 clocks = <&infracfg CLK_INFRA_CEC>;
371 compatible = "mediatek,mt8173-vpu";
372 reg = <0 0x10020000 0 0x30000>,
373 <0 0x10050000 0 0x100>;
374 reg-names = "tcm", "cfg_reg";
375 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&topckgen CLK_TOP_SCP_SEL>;
377 clock-names = "main";
378 memory-region = <&vpu_dma_reserved>;
381 sysirq: intpol-controller@10200620 {
382 compatible = "mediatek,mt8173-sysirq",
383 "mediatek,mt6577-sysirq";
384 interrupt-controller;
385 #interrupt-cells = <3>;
386 interrupt-parent = <&gic>;
387 reg = <0 0x10200620 0 0x20>;
390 iommu: iommu@10205000 {
391 compatible = "mediatek,mt8173-m4u";
392 reg = <0 0x10205000 0 0x1000>;
393 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
394 clocks = <&infracfg CLK_INFRA_M4U>;
395 clock-names = "bclk";
396 mediatek,larbs = <&larb0 &larb1 &larb2
397 &larb3 &larb4 &larb5>;
401 efuse: efuse@10206000 {
402 compatible = "mediatek,mt8173-efuse";
403 reg = <0 0x10206000 0 0x1000>;
404 #address-cells = <1>;
406 thermal_calibration: calib@528 {
411 apmixedsys: clock-controller@10209000 {
412 compatible = "mediatek,mt8173-apmixedsys";
413 reg = <0 0x10209000 0 0x1000>;
417 hdmi_phy: hdmi-phy@10209100 {
418 compatible = "mediatek,mt8173-hdmi-phy";
419 reg = <0 0x10209100 0 0x24>;
420 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
421 clock-names = "pll_ref";
422 clock-output-names = "hdmitx_dig_cts";
423 mediatek,ibias = <0xa>;
424 mediatek,ibias_up = <0x1c>;
430 mipi_tx0: mipi-dphy@10215000 {
431 compatible = "mediatek,mt8173-mipi-tx";
432 reg = <0 0x10215000 0 0x1000>;
434 clock-output-names = "mipi_tx0_pll";
440 mipi_tx1: mipi-dphy@10216000 {
441 compatible = "mediatek,mt8173-mipi-tx";
442 reg = <0 0x10216000 0 0x1000>;
444 clock-output-names = "mipi_tx1_pll";
450 gic: interrupt-controller@10220000 {
451 compatible = "arm,gic-400";
452 #interrupt-cells = <3>;
453 interrupt-parent = <&gic>;
454 interrupt-controller;
455 reg = <0 0x10221000 0 0x1000>,
456 <0 0x10222000 0 0x2000>,
457 <0 0x10224000 0 0x2000>,
458 <0 0x10226000 0 0x2000>;
459 interrupts = <GIC_PPI 9
460 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
463 auxadc: auxadc@11001000 {
464 compatible = "mediatek,mt8173-auxadc";
465 reg = <0 0x11001000 0 0x1000>;
466 clocks = <&pericfg CLK_PERI_AUXADC>;
467 clock-names = "main";
468 #io-channel-cells = <1>;
471 uart0: serial@11002000 {
472 compatible = "mediatek,mt8173-uart",
473 "mediatek,mt6577-uart";
474 reg = <0 0x11002000 0 0x400>;
475 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
476 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
477 clock-names = "baud", "bus";
481 uart1: serial@11003000 {
482 compatible = "mediatek,mt8173-uart",
483 "mediatek,mt6577-uart";
484 reg = <0 0x11003000 0 0x400>;
485 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
486 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
487 clock-names = "baud", "bus";
491 uart2: serial@11004000 {
492 compatible = "mediatek,mt8173-uart",
493 "mediatek,mt6577-uart";
494 reg = <0 0x11004000 0 0x400>;
495 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
496 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
497 clock-names = "baud", "bus";
501 uart3: serial@11005000 {
502 compatible = "mediatek,mt8173-uart",
503 "mediatek,mt6577-uart";
504 reg = <0 0x11005000 0 0x400>;
505 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
506 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
507 clock-names = "baud", "bus";
512 compatible = "mediatek,mt8173-i2c";
513 reg = <0 0x11007000 0 0x70>,
514 <0 0x11000100 0 0x80>;
515 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
517 clocks = <&pericfg CLK_PERI_I2C0>,
518 <&pericfg CLK_PERI_AP_DMA>;
519 clock-names = "main", "dma";
520 pinctrl-names = "default";
521 pinctrl-0 = <&i2c0_pins_a>;
522 #address-cells = <1>;
528 compatible = "mediatek,mt8173-i2c";
529 reg = <0 0x11008000 0 0x70>,
530 <0 0x11000180 0 0x80>;
531 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
533 clocks = <&pericfg CLK_PERI_I2C1>,
534 <&pericfg CLK_PERI_AP_DMA>;
535 clock-names = "main", "dma";
536 pinctrl-names = "default";
537 pinctrl-0 = <&i2c1_pins_a>;
538 #address-cells = <1>;
544 compatible = "mediatek,mt8173-i2c";
545 reg = <0 0x11009000 0 0x70>,
546 <0 0x11000200 0 0x80>;
547 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
549 clocks = <&pericfg CLK_PERI_I2C2>,
550 <&pericfg CLK_PERI_AP_DMA>;
551 clock-names = "main", "dma";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c2_pins_a>;
554 #address-cells = <1>;
560 compatible = "mediatek,mt8173-spi";
561 #address-cells = <1>;
563 reg = <0 0x1100a000 0 0x1000>;
564 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
565 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
566 <&topckgen CLK_TOP_SPI_SEL>,
567 <&pericfg CLK_PERI_SPI0>;
568 clock-names = "parent-clk", "sel-clk", "spi-clk";
572 thermal: thermal@1100b000 {
573 #thermal-sensor-cells = <0>;
574 compatible = "mediatek,mt8173-thermal";
575 reg = <0 0x1100b000 0 0x1000>;
576 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
577 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
578 clock-names = "therm", "auxadc";
579 resets = <&pericfg MT8173_PERI_THERM_SW_RST>;
580 mediatek,auxadc = <&auxadc>;
581 mediatek,apmixedsys = <&apmixedsys>;
582 nvmem-cells = <&thermal_calibration>;
583 nvmem-cell-names = "calibration-data";
586 nor_flash: spi@1100d000 {
587 compatible = "mediatek,mt8173-nor";
588 reg = <0 0x1100d000 0 0xe0>;
589 clocks = <&pericfg CLK_PERI_SPI>,
590 <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
591 clock-names = "spi", "sf";
592 #address-cells = <1>;
598 compatible = "mediatek,mt8173-i2c";
599 reg = <0 0x11010000 0 0x70>,
600 <0 0x11000280 0 0x80>;
601 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
603 clocks = <&pericfg CLK_PERI_I2C3>,
604 <&pericfg CLK_PERI_AP_DMA>;
605 clock-names = "main", "dma";
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c3_pins_a>;
608 #address-cells = <1>;
614 compatible = "mediatek,mt8173-i2c";
615 reg = <0 0x11011000 0 0x70>,
616 <0 0x11000300 0 0x80>;
617 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
619 clocks = <&pericfg CLK_PERI_I2C4>,
620 <&pericfg CLK_PERI_AP_DMA>;
621 clock-names = "main", "dma";
622 pinctrl-names = "default";
623 pinctrl-0 = <&i2c4_pins_a>;
624 #address-cells = <1>;
629 hdmiddc0: i2c@11012000 {
630 compatible = "mediatek,mt8173-hdmi-ddc";
631 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
632 reg = <0 0x11012000 0 0x1C>;
633 clocks = <&pericfg CLK_PERI_I2C5>;
634 clock-names = "ddc-i2c";
638 compatible = "mediatek,mt8173-i2c";
639 reg = <0 0x11013000 0 0x70>,
640 <0 0x11000080 0 0x80>;
641 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
643 clocks = <&pericfg CLK_PERI_I2C6>,
644 <&pericfg CLK_PERI_AP_DMA>;
645 clock-names = "main", "dma";
646 pinctrl-names = "default";
647 pinctrl-0 = <&i2c6_pins_a>;
648 #address-cells = <1>;
653 afe: audio-controller@11220000 {
654 compatible = "mediatek,mt8173-afe-pcm";
655 reg = <0 0x11220000 0 0x1000>;
656 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
657 power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
658 clocks = <&infracfg CLK_INFRA_AUDIO>,
659 <&topckgen CLK_TOP_AUDIO_SEL>,
660 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
661 <&topckgen CLK_TOP_APLL1_DIV0>,
662 <&topckgen CLK_TOP_APLL2_DIV0>,
663 <&topckgen CLK_TOP_I2S0_M_SEL>,
664 <&topckgen CLK_TOP_I2S1_M_SEL>,
665 <&topckgen CLK_TOP_I2S2_M_SEL>,
666 <&topckgen CLK_TOP_I2S3_M_SEL>,
667 <&topckgen CLK_TOP_I2S3_B_SEL>;
668 clock-names = "infra_sys_audio_clk",
670 "top_pdn_aud_intbus",
678 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
679 <&topckgen CLK_TOP_AUD_2_SEL>;
680 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
681 <&topckgen CLK_TOP_APLL2>;
685 compatible = "mediatek,mt8173-mmc";
686 reg = <0 0x11230000 0 0x1000>;
687 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
688 clocks = <&pericfg CLK_PERI_MSDC30_0>,
689 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
690 clock-names = "source", "hclk";
695 compatible = "mediatek,mt8173-mmc";
696 reg = <0 0x11240000 0 0x1000>;
697 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
698 clocks = <&pericfg CLK_PERI_MSDC30_1>,
699 <&topckgen CLK_TOP_AXI_SEL>;
700 clock-names = "source", "hclk";
705 compatible = "mediatek,mt8173-mmc";
706 reg = <0 0x11250000 0 0x1000>;
707 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
708 clocks = <&pericfg CLK_PERI_MSDC30_2>,
709 <&topckgen CLK_TOP_AXI_SEL>;
710 clock-names = "source", "hclk";
715 compatible = "mediatek,mt8173-mmc";
716 reg = <0 0x11260000 0 0x1000>;
717 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
718 clocks = <&pericfg CLK_PERI_MSDC30_3>,
719 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
720 clock-names = "source", "hclk";
724 ssusb: usb@11271000 {
725 compatible = "mediatek,mt8173-mtu3";
726 reg = <0 0x11271000 0 0x3000>,
727 <0 0x11280700 0 0x0100>;
728 reg-names = "mac", "ippc";
729 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>;
730 phys = <&u2port0 PHY_TYPE_USB2>,
731 <&u3port0 PHY_TYPE_USB3>,
732 <&u2port1 PHY_TYPE_USB2>;
733 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
734 clocks = <&topckgen CLK_TOP_USB30_SEL>,
736 <&pericfg CLK_PERI_USB0>,
737 <&pericfg CLK_PERI_USB1>;
738 clock-names = "sys_ck",
742 mediatek,syscon-wakeup = <&pericfg>;
743 #address-cells = <2>;
748 usb_host: xhci@11270000 {
749 compatible = "mediatek,mt8173-xhci";
750 reg = <0 0x11270000 0 0x1000>;
752 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
753 power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
754 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>;
755 clock-names = "sys_ck", "ref_ck";
760 u3phy: usb-phy@11290000 {
761 compatible = "mediatek,mt8173-u3phy";
762 reg = <0 0x11290000 0 0x800>;
763 #address-cells = <2>;
768 u2port0: usb-phy@11290800 {
769 reg = <0 0x11290800 0 0x100>;
770 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
776 u3port0: usb-phy@11290900 {
777 reg = <0 0x11290900 0 0x700>;
784 u2port1: usb-phy@11291000 {
785 reg = <0 0x11291000 0 0x100>;
786 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
793 mmsys: clock-controller@14000000 {
794 compatible = "mediatek,mt8173-mmsys", "syscon";
795 reg = <0 0x14000000 0 0x1000>;
796 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
797 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
798 assigned-clock-rates = <400000000>;
802 mdp_rdma0: rdma@14001000 {
803 compatible = "mediatek,mt8173-mdp-rdma",
804 "mediatek,mt8173-mdp";
805 reg = <0 0x14001000 0 0x1000>;
806 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
807 <&mmsys CLK_MM_MUTEX_32K>;
808 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
809 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
810 mediatek,larb = <&larb0>;
811 mediatek,vpu = <&vpu>;
814 mdp_rdma1: rdma@14002000 {
815 compatible = "mediatek,mt8173-mdp-rdma";
816 reg = <0 0x14002000 0 0x1000>;
817 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
818 <&mmsys CLK_MM_MUTEX_32K>;
819 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
820 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
821 mediatek,larb = <&larb4>;
824 mdp_rsz0: rsz@14003000 {
825 compatible = "mediatek,mt8173-mdp-rsz";
826 reg = <0 0x14003000 0 0x1000>;
827 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
828 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
831 mdp_rsz1: rsz@14004000 {
832 compatible = "mediatek,mt8173-mdp-rsz";
833 reg = <0 0x14004000 0 0x1000>;
834 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
835 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
838 mdp_rsz2: rsz@14005000 {
839 compatible = "mediatek,mt8173-mdp-rsz";
840 reg = <0 0x14005000 0 0x1000>;
841 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
842 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
845 mdp_wdma0: wdma@14006000 {
846 compatible = "mediatek,mt8173-mdp-wdma";
847 reg = <0 0x14006000 0 0x1000>;
848 clocks = <&mmsys CLK_MM_MDP_WDMA>;
849 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
850 iommus = <&iommu M4U_PORT_MDP_WDMA>;
851 mediatek,larb = <&larb0>;
854 mdp_wrot0: wrot@14007000 {
855 compatible = "mediatek,mt8173-mdp-wrot";
856 reg = <0 0x14007000 0 0x1000>;
857 clocks = <&mmsys CLK_MM_MDP_WROT0>;
858 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
859 iommus = <&iommu M4U_PORT_MDP_WROT0>;
860 mediatek,larb = <&larb0>;
863 mdp_wrot1: wrot@14008000 {
864 compatible = "mediatek,mt8173-mdp-wrot";
865 reg = <0 0x14008000 0 0x1000>;
866 clocks = <&mmsys CLK_MM_MDP_WROT1>;
867 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
868 iommus = <&iommu M4U_PORT_MDP_WROT1>;
869 mediatek,larb = <&larb4>;
873 compatible = "mediatek,mt8173-disp-ovl";
874 reg = <0 0x1400c000 0 0x1000>;
875 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
876 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
877 clocks = <&mmsys CLK_MM_DISP_OVL0>;
878 iommus = <&iommu M4U_PORT_DISP_OVL0>;
879 mediatek,larb = <&larb0>;
883 compatible = "mediatek,mt8173-disp-ovl";
884 reg = <0 0x1400d000 0 0x1000>;
885 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
886 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
887 clocks = <&mmsys CLK_MM_DISP_OVL1>;
888 iommus = <&iommu M4U_PORT_DISP_OVL1>;
889 mediatek,larb = <&larb4>;
892 rdma0: rdma@1400e000 {
893 compatible = "mediatek,mt8173-disp-rdma";
894 reg = <0 0x1400e000 0 0x1000>;
895 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
896 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
897 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
898 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
899 mediatek,larb = <&larb0>;
902 rdma1: rdma@1400f000 {
903 compatible = "mediatek,mt8173-disp-rdma";
904 reg = <0 0x1400f000 0 0x1000>;
905 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
906 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
907 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
908 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
909 mediatek,larb = <&larb4>;
912 rdma2: rdma@14010000 {
913 compatible = "mediatek,mt8173-disp-rdma";
914 reg = <0 0x14010000 0 0x1000>;
915 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
916 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
917 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
918 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
919 mediatek,larb = <&larb4>;
922 wdma0: wdma@14011000 {
923 compatible = "mediatek,mt8173-disp-wdma";
924 reg = <0 0x14011000 0 0x1000>;
925 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
926 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
927 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
928 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
929 mediatek,larb = <&larb0>;
932 wdma1: wdma@14012000 {
933 compatible = "mediatek,mt8173-disp-wdma";
934 reg = <0 0x14012000 0 0x1000>;
935 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
936 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
937 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
938 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
939 mediatek,larb = <&larb4>;
942 color0: color@14013000 {
943 compatible = "mediatek,mt8173-disp-color";
944 reg = <0 0x14013000 0 0x1000>;
945 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
946 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
947 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
950 color1: color@14014000 {
951 compatible = "mediatek,mt8173-disp-color";
952 reg = <0 0x14014000 0 0x1000>;
953 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
954 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
955 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
959 compatible = "mediatek,mt8173-disp-aal";
960 reg = <0 0x14015000 0 0x1000>;
961 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
962 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
963 clocks = <&mmsys CLK_MM_DISP_AAL>;
967 compatible = "mediatek,mt8173-disp-gamma";
968 reg = <0 0x14016000 0 0x1000>;
969 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
970 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
971 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
975 compatible = "mediatek,mt8173-disp-merge";
976 reg = <0 0x14017000 0 0x1000>;
977 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
978 clocks = <&mmsys CLK_MM_DISP_MERGE>;
981 split0: split@14018000 {
982 compatible = "mediatek,mt8173-disp-split";
983 reg = <0 0x14018000 0 0x1000>;
984 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
985 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
988 split1: split@14019000 {
989 compatible = "mediatek,mt8173-disp-split";
990 reg = <0 0x14019000 0 0x1000>;
991 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
992 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
996 compatible = "mediatek,mt8173-disp-ufoe";
997 reg = <0 0x1401a000 0 0x1000>;
998 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
999 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1000 clocks = <&mmsys CLK_MM_DISP_UFOE>;
1003 dsi0: dsi@1401b000 {
1004 compatible = "mediatek,mt8173-dsi";
1005 reg = <0 0x1401b000 0 0x1000>;
1006 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
1007 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1008 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
1009 <&mmsys CLK_MM_DSI0_DIGITAL>,
1011 clock-names = "engine", "digital", "hs";
1014 status = "disabled";
1017 dsi1: dsi@1401c000 {
1018 compatible = "mediatek,mt8173-dsi";
1019 reg = <0 0x1401c000 0 0x1000>;
1020 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
1021 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1022 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
1023 <&mmsys CLK_MM_DSI1_DIGITAL>,
1025 clock-names = "engine", "digital", "hs";
1028 status = "disabled";
1031 dpi0: dpi@1401d000 {
1032 compatible = "mediatek,mt8173-dpi";
1033 reg = <0 0x1401d000 0 0x1000>;
1034 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
1035 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1036 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
1037 <&mmsys CLK_MM_DPI_ENGINE>,
1038 <&apmixedsys CLK_APMIXED_TVDPLL>;
1039 clock-names = "pixel", "engine", "pll";
1040 status = "disabled";
1043 dpi0_out: endpoint {
1044 remote-endpoint = <&hdmi0_in>;
1049 pwm0: pwm@1401e000 {
1050 compatible = "mediatek,mt8173-disp-pwm",
1051 "mediatek,mt6595-disp-pwm";
1052 reg = <0 0x1401e000 0 0x1000>;
1054 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
1055 <&mmsys CLK_MM_DISP_PWM0MM>;
1056 clock-names = "main", "mm";
1057 status = "disabled";
1060 pwm1: pwm@1401f000 {
1061 compatible = "mediatek,mt8173-disp-pwm",
1062 "mediatek,mt6595-disp-pwm";
1063 reg = <0 0x1401f000 0 0x1000>;
1065 clocks = <&mmsys CLK_MM_DISP_PWM126M>,
1066 <&mmsys CLK_MM_DISP_PWM1MM>;
1067 clock-names = "main", "mm";
1068 status = "disabled";
1071 mutex: mutex@14020000 {
1072 compatible = "mediatek,mt8173-disp-mutex";
1073 reg = <0 0x14020000 0 0x1000>;
1074 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
1075 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1076 clocks = <&mmsys CLK_MM_MUTEX_32K>;
1079 larb0: larb@14021000 {
1080 compatible = "mediatek,mt8173-smi-larb";
1081 reg = <0 0x14021000 0 0x1000>;
1082 mediatek,smi = <&smi_common>;
1083 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1084 clocks = <&mmsys CLK_MM_SMI_LARB0>,
1085 <&mmsys CLK_MM_SMI_LARB0>;
1086 clock-names = "apb", "smi";
1089 smi_common: smi@14022000 {
1090 compatible = "mediatek,mt8173-smi-common";
1091 reg = <0 0x14022000 0 0x1000>;
1092 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1093 clocks = <&mmsys CLK_MM_SMI_COMMON>,
1094 <&mmsys CLK_MM_SMI_COMMON>;
1095 clock-names = "apb", "smi";
1099 compatible = "mediatek,mt8173-disp-od";
1100 reg = <0 0x14023000 0 0x1000>;
1101 clocks = <&mmsys CLK_MM_DISP_OD>;
1104 hdmi0: hdmi@14025000 {
1105 compatible = "mediatek,mt8173-hdmi";
1106 reg = <0 0x14025000 0 0x400>;
1107 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
1108 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
1109 <&mmsys CLK_MM_HDMI_PLLCK>,
1110 <&mmsys CLK_MM_HDMI_AUDIO>,
1111 <&mmsys CLK_MM_HDMI_SPDIF>;
1112 clock-names = "pixel", "pll", "bclk", "spdif";
1113 pinctrl-names = "default";
1114 pinctrl-0 = <&hdmi_pin>;
1117 mediatek,syscon-hdmi = <&mmsys 0x900>;
1118 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
1119 assigned-clock-parents = <&hdmi_phy>;
1120 status = "disabled";
1123 #address-cells = <1>;
1129 hdmi0_in: endpoint {
1130 remote-endpoint = <&dpi0_out>;
1136 larb4: larb@14027000 {
1137 compatible = "mediatek,mt8173-smi-larb";
1138 reg = <0 0x14027000 0 0x1000>;
1139 mediatek,smi = <&smi_common>;
1140 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
1141 clocks = <&mmsys CLK_MM_SMI_LARB4>,
1142 <&mmsys CLK_MM_SMI_LARB4>;
1143 clock-names = "apb", "smi";
1146 imgsys: clock-controller@15000000 {
1147 compatible = "mediatek,mt8173-imgsys", "syscon";
1148 reg = <0 0x15000000 0 0x1000>;
1152 larb2: larb@15001000 {
1153 compatible = "mediatek,mt8173-smi-larb";
1154 reg = <0 0x15001000 0 0x1000>;
1155 mediatek,smi = <&smi_common>;
1156 power-domains = <&scpsys MT8173_POWER_DOMAIN_ISP>;
1157 clocks = <&imgsys CLK_IMG_LARB2_SMI>,
1158 <&imgsys CLK_IMG_LARB2_SMI>;
1159 clock-names = "apb", "smi";
1162 vdecsys: clock-controller@16000000 {
1163 compatible = "mediatek,mt8173-vdecsys", "syscon";
1164 reg = <0 0x16000000 0 0x1000>;
1168 vcodec_dec: vcodec@16000000 {
1169 compatible = "mediatek,mt8173-vcodec-dec";
1170 reg = <0 0x16000000 0 0x100>, /* VDEC_SYS */
1171 <0 0x16020000 0 0x1000>, /* VDEC_MISC */
1172 <0 0x16021000 0 0x800>, /* VDEC_LD */
1173 <0 0x16021800 0 0x800>, /* VDEC_TOP */
1174 <0 0x16022000 0 0x1000>, /* VDEC_CM */
1175 <0 0x16023000 0 0x1000>, /* VDEC_AD */
1176 <0 0x16024000 0 0x1000>, /* VDEC_AV */
1177 <0 0x16025000 0 0x1000>, /* VDEC_PP */
1178 <0 0x16026800 0 0x800>, /* VDEC_HWD */
1179 <0 0x16027000 0 0x800>, /* VDEC_HWQ */
1180 <0 0x16027800 0 0x800>, /* VDEC_HWB */
1181 <0 0x16028400 0 0x400>; /* VDEC_HWG */
1182 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
1183 mediatek,larb = <&larb1>;
1184 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
1185 <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
1186 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
1187 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
1188 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
1189 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
1190 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
1191 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
1192 mediatek,vpu = <&vpu>;
1193 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1194 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
1195 <&topckgen CLK_TOP_UNIVPLL_D2>,
1196 <&topckgen CLK_TOP_CCI400_SEL>,
1197 <&topckgen CLK_TOP_VDEC_SEL>,
1198 <&topckgen CLK_TOP_VCODECPLL>,
1199 <&apmixedsys CLK_APMIXED_VENCPLL>,
1200 <&topckgen CLK_TOP_VENC_LT_SEL>,
1201 <&topckgen CLK_TOP_VCODECPLL_370P5>;
1202 clock-names = "vcodecpll",
1212 larb1: larb@16010000 {
1213 compatible = "mediatek,mt8173-smi-larb";
1214 reg = <0 0x16010000 0 0x1000>;
1215 mediatek,smi = <&smi_common>;
1216 power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
1217 clocks = <&vdecsys CLK_VDEC_CKEN>,
1218 <&vdecsys CLK_VDEC_LARB_CKEN>;
1219 clock-names = "apb", "smi";
1222 vencsys: clock-controller@18000000 {
1223 compatible = "mediatek,mt8173-vencsys", "syscon";
1224 reg = <0 0x18000000 0 0x1000>;
1228 larb3: larb@18001000 {
1229 compatible = "mediatek,mt8173-smi-larb";
1230 reg = <0 0x18001000 0 0x1000>;
1231 mediatek,smi = <&smi_common>;
1232 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>;
1233 clocks = <&vencsys CLK_VENC_CKE1>,
1234 <&vencsys CLK_VENC_CKE0>;
1235 clock-names = "apb", "smi";
1238 vcodec_enc: vcodec@18002000 {
1239 compatible = "mediatek,mt8173-vcodec-enc";
1240 reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
1241 <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
1242 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
1243 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
1244 mediatek,larb = <&larb3>,
1246 iommus = <&iommu M4U_PORT_VENC_RCPU>,
1247 <&iommu M4U_PORT_VENC_REC>,
1248 <&iommu M4U_PORT_VENC_BSDMA>,
1249 <&iommu M4U_PORT_VENC_SV_COMV>,
1250 <&iommu M4U_PORT_VENC_RD_COMV>,
1251 <&iommu M4U_PORT_VENC_CUR_LUMA>,
1252 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
1253 <&iommu M4U_PORT_VENC_REF_LUMA>,
1254 <&iommu M4U_PORT_VENC_REF_CHROMA>,
1255 <&iommu M4U_PORT_VENC_NBM_RDMA>,
1256 <&iommu M4U_PORT_VENC_NBM_WDMA>,
1257 <&iommu M4U_PORT_VENC_RCPU_SET2>,
1258 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
1259 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
1260 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
1261 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
1262 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
1263 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
1264 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
1265 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
1266 mediatek,vpu = <&vpu>;
1267 clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
1268 <&topckgen CLK_TOP_VENC_SEL>,
1269 <&topckgen CLK_TOP_UNIVPLL1_D2>,
1270 <&topckgen CLK_TOP_VENC_LT_SEL>;
1271 clock-names = "venc_sel_src",
1277 vencltsys: clock-controller@19000000 {
1278 compatible = "mediatek,mt8173-vencltsys", "syscon";
1279 reg = <0 0x19000000 0 0x1000>;
1283 larb5: larb@19001000 {
1284 compatible = "mediatek,mt8173-smi-larb";
1285 reg = <0 0x19001000 0 0x1000>;
1286 mediatek,smi = <&smi_common>;
1287 power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>;
1288 clocks = <&vencltsys CLK_VENCLT_CKE1>,
1289 <&vencltsys CLK_VENCLT_CKE0>;
1290 clock-names = "apb", "smi";