2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
73 compatible = "arm,cortex-a53", "arm,armv8";
75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
82 cci-control-port = <&cci_control2>;
87 compatible = "arm,cortex-a53", "arm,armv8";
89 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
91 clock-names = "cpu", "intermediate";
92 operating-points-v2 = <&cpu_opp_table>;
94 enable-method = "psci";
95 clock-frequency = <1300000000>;
96 cci-control-port = <&cci_control2>;
100 pwrap_clk: dummy40m {
101 compatible = "fixed-clock";
102 clock-frequency = <40000000>;
107 compatible = "fixed-clock";
109 clock-frequency = <25000000>;
110 clock-output-names = "clkxtal";
114 compatible = "arm,psci-0.2";
119 compatible = "arm,cortex-a53-pmu";
120 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
121 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
122 interrupt-affinity = <&cpu0>, <&cpu1>;
126 #address-cells = <2>;
130 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
131 secmon_reserved: secmon@43000000 {
132 reg = <0 0x43000000 0 0x30000>;
138 cpu_thermal: cpu-thermal {
139 polling-delay-passive = <1000>;
140 polling-delay = <1000>;
142 thermal-sensors = <&thermal 0>;
145 cpu_passive: cpu-passive {
146 temperature = <47000>;
151 cpu_active: cpu-active {
152 temperature = <67000>;
158 temperature = <87000>;
164 temperature = <107000>;
172 trip = <&cpu_passive>;
173 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
177 trip = <&cpu_active>;
178 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
183 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
190 compatible = "arm,armv8-timer";
191 interrupt-parent = <&gic>;
192 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
193 IRQ_TYPE_LEVEL_HIGH)>,
194 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
195 IRQ_TYPE_LEVEL_HIGH)>,
196 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
197 IRQ_TYPE_LEVEL_HIGH)>,
198 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
199 IRQ_TYPE_LEVEL_HIGH)>;
202 infracfg: infracfg@10000000 {
203 compatible = "mediatek,mt7622-infracfg",
205 reg = <0 0x10000000 0 0x1000>;
210 pwrap: pwrap@10001000 {
211 compatible = "mediatek,mt7622-pwrap";
212 reg = <0 0x10001000 0 0x250>;
214 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
215 clock-names = "spi", "wrap";
216 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
217 reset-names = "pwrap";
218 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
222 pericfg: pericfg@10002000 {
223 compatible = "mediatek,mt7622-pericfg",
225 reg = <0 0x10002000 0 0x1000>;
230 scpsys: scpsys@10006000 {
231 compatible = "mediatek,mt7622-scpsys",
233 #power-domain-cells = <1>;
234 reg = <0 0x10006000 0 0x1000>;
235 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
236 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
237 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
238 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
239 infracfg = <&infracfg>;
240 clocks = <&topckgen CLK_TOP_HIF_SEL>;
241 clock-names = "hif_sel";
245 compatible = "mediatek,mt7622-cir";
246 reg = <0 0x10009000 0 0x1000>;
247 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
248 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
249 <&topckgen CLK_TOP_AXI_SEL>;
250 clock-names = "clk", "bus";
254 sysirq: interrupt-controller@10200620 {
255 compatible = "mediatek,mt7622-sysirq",
256 "mediatek,mt6577-sysirq";
257 interrupt-controller;
258 #interrupt-cells = <3>;
259 interrupt-parent = <&gic>;
260 reg = <0 0x10200620 0 0x20>;
263 efuse: efuse@10206000 {
264 compatible = "mediatek,mt7622-efuse",
266 reg = <0 0x10206000 0 0x1000>;
267 #address-cells = <1>;
270 thermal_calibration: calib@198 {
275 apmixedsys: apmixedsys@10209000 {
276 compatible = "mediatek,mt7622-apmixedsys",
278 reg = <0 0x10209000 0 0x1000>;
282 topckgen: topckgen@10210000 {
283 compatible = "mediatek,mt7622-topckgen",
285 reg = <0 0x10210000 0 0x1000>;
290 compatible = "mediatek,mt7622-rng",
291 "mediatek,mt7623-rng";
292 reg = <0 0x1020f000 0 0x1000>;
293 clocks = <&infracfg CLK_INFRA_TRNG>;
297 pio: pinctrl@10211000 {
298 compatible = "mediatek,mt7622-pinctrl";
299 reg = <0 0x10211000 0 0x1000>,
300 <0 0x10005000 0 0x1000>;
301 reg-names = "base", "eint";
304 gpio-ranges = <&pio 0 0 103>;
305 interrupt-controller;
306 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
307 interrupt-parent = <&gic>;
308 #interrupt-cells = <2>;
311 watchdog: watchdog@10212000 {
312 compatible = "mediatek,mt7622-wdt",
313 "mediatek,mt6589-wdt";
314 reg = <0 0x10212000 0 0x800>;
318 compatible = "mediatek,mt7622-rtc",
320 reg = <0 0x10212800 0 0x200>;
321 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
322 clocks = <&topckgen CLK_TOP_RTC>;
326 gic: interrupt-controller@10300000 {
327 compatible = "arm,gic-400";
328 interrupt-controller;
329 #interrupt-cells = <3>;
330 interrupt-parent = <&gic>;
331 reg = <0 0x10310000 0 0x1000>,
332 <0 0x10320000 0 0x1000>,
333 <0 0x10340000 0 0x2000>,
334 <0 0x10360000 0 0x2000>;
338 compatible = "arm,cci-400";
339 #address-cells = <1>;
341 reg = <0 0x10390000 0 0x1000>;
342 ranges = <0 0 0x10390000 0x10000>;
344 cci_control0: slave-if@1000 {
345 compatible = "arm,cci-400-ctrl-if";
346 interface-type = "ace-lite";
347 reg = <0x1000 0x1000>;
350 cci_control1: slave-if@4000 {
351 compatible = "arm,cci-400-ctrl-if";
352 interface-type = "ace";
353 reg = <0x4000 0x1000>;
356 cci_control2: slave-if@5000 {
357 compatible = "arm,cci-400-ctrl-if";
358 interface-type = "ace";
359 reg = <0x5000 0x1000>;
363 compatible = "arm,cci-400-pmu,r1";
364 reg = <0x9000 0x5000>;
365 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
373 auxadc: adc@11001000 {
374 compatible = "mediatek,mt7622-auxadc";
375 reg = <0 0x11001000 0 0x1000>;
376 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
377 clock-names = "main";
378 #io-channel-cells = <1>;
381 uart0: serial@11002000 {
382 compatible = "mediatek,mt7622-uart",
383 "mediatek,mt6577-uart";
384 reg = <0 0x11002000 0 0x400>;
385 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
386 clocks = <&topckgen CLK_TOP_UART_SEL>,
387 <&pericfg CLK_PERI_UART0_PD>;
388 clock-names = "baud", "bus";
392 uart1: serial@11003000 {
393 compatible = "mediatek,mt7622-uart",
394 "mediatek,mt6577-uart";
395 reg = <0 0x11003000 0 0x400>;
396 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
397 clocks = <&topckgen CLK_TOP_UART_SEL>,
398 <&pericfg CLK_PERI_UART1_PD>;
399 clock-names = "baud", "bus";
403 uart2: serial@11004000 {
404 compatible = "mediatek,mt7622-uart",
405 "mediatek,mt6577-uart";
406 reg = <0 0x11004000 0 0x400>;
407 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
408 clocks = <&topckgen CLK_TOP_UART_SEL>,
409 <&pericfg CLK_PERI_UART2_PD>;
410 clock-names = "baud", "bus";
414 uart3: serial@11005000 {
415 compatible = "mediatek,mt7622-uart",
416 "mediatek,mt6577-uart";
417 reg = <0 0x11005000 0 0x400>;
418 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
419 clocks = <&topckgen CLK_TOP_UART_SEL>,
420 <&pericfg CLK_PERI_UART3_PD>;
421 clock-names = "baud", "bus";
426 compatible = "mediatek,mt7622-pwm";
427 reg = <0 0x11006000 0 0x1000>;
428 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
429 clocks = <&topckgen CLK_TOP_PWM_SEL>,
430 <&pericfg CLK_PERI_PWM_PD>,
431 <&pericfg CLK_PERI_PWM1_PD>,
432 <&pericfg CLK_PERI_PWM2_PD>,
433 <&pericfg CLK_PERI_PWM3_PD>,
434 <&pericfg CLK_PERI_PWM4_PD>,
435 <&pericfg CLK_PERI_PWM5_PD>,
436 <&pericfg CLK_PERI_PWM6_PD>;
437 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
443 compatible = "mediatek,mt7622-i2c";
444 reg = <0 0x11007000 0 0x90>,
445 <0 0x11000100 0 0x80>;
446 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
448 clocks = <&pericfg CLK_PERI_I2C0_PD>,
449 <&pericfg CLK_PERI_AP_DMA_PD>;
450 clock-names = "main", "dma";
451 #address-cells = <1>;
457 compatible = "mediatek,mt7622-i2c";
458 reg = <0 0x11008000 0 0x90>,
459 <0 0x11000180 0 0x80>;
460 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
462 clocks = <&pericfg CLK_PERI_I2C1_PD>,
463 <&pericfg CLK_PERI_AP_DMA_PD>;
464 clock-names = "main", "dma";
465 #address-cells = <1>;
471 compatible = "mediatek,mt7622-i2c";
472 reg = <0 0x11009000 0 0x90>,
473 <0 0x11000200 0 0x80>;
474 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
476 clocks = <&pericfg CLK_PERI_I2C2_PD>,
477 <&pericfg CLK_PERI_AP_DMA_PD>;
478 clock-names = "main", "dma";
479 #address-cells = <1>;
485 compatible = "mediatek,mt7622-spi";
486 reg = <0 0x1100a000 0 0x100>;
487 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
488 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489 <&topckgen CLK_TOP_SPI0_SEL>,
490 <&pericfg CLK_PERI_SPI0_PD>;
491 clock-names = "parent-clk", "sel-clk", "spi-clk";
492 #address-cells = <1>;
497 thermal: thermal@1100b000 {
498 #thermal-sensor-cells = <1>;
499 compatible = "mediatek,mt7622-thermal";
500 reg = <0 0x1100b000 0 0x1000>;
501 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
502 clocks = <&pericfg CLK_PERI_THERM_PD>,
503 <&pericfg CLK_PERI_AUXADC_PD>;
504 clock-names = "therm", "auxadc";
505 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
506 reset-names = "therm";
507 mediatek,auxadc = <&auxadc>;
508 mediatek,apmixedsys = <&apmixedsys>;
509 nvmem-cells = <&thermal_calibration>;
510 nvmem-cell-names = "calibration-data";
513 btif: serial@1100c000 {
514 compatible = "mediatek,mt7622-btif",
516 reg = <0 0x1100c000 0 0x1000>;
517 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
518 clocks = <&pericfg CLK_PERI_BTIF_PD>;
519 clock-names = "main";
525 compatible = "mediatek,mt7622-bluetooth";
526 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
532 nandc: nfi@1100d000 {
533 compatible = "mediatek,mt7622-nfc";
534 reg = <0 0x1100D000 0 0x1000>;
535 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
536 clocks = <&pericfg CLK_PERI_NFI_PD>,
537 <&pericfg CLK_PERI_SNFI_PD>;
538 clock-names = "nfi_clk", "pad_clk";
540 #address-cells = <1>;
546 compatible = "mediatek,mt7622-ecc";
547 reg = <0 0x1100e000 0 0x1000>;
548 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
549 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
550 clock-names = "nfiecc_clk";
554 nor_flash: spi@11014000 {
555 compatible = "mediatek,mt7622-nor",
556 "mediatek,mt8173-nor";
557 reg = <0 0x11014000 0 0xe0>;
558 clocks = <&pericfg CLK_PERI_FLASH_PD>,
559 <&topckgen CLK_TOP_FLASH_SEL>;
560 clock-names = "spi", "sf";
561 #address-cells = <1>;
567 compatible = "mediatek,mt7622-spi";
568 reg = <0 0x11016000 0 0x100>;
569 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
570 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
571 <&topckgen CLK_TOP_SPI1_SEL>,
572 <&pericfg CLK_PERI_SPI1_PD>;
573 clock-names = "parent-clk", "sel-clk", "spi-clk";
574 #address-cells = <1>;
579 uart4: serial@11019000 {
580 compatible = "mediatek,mt7622-uart",
581 "mediatek,mt6577-uart";
582 reg = <0 0x11019000 0 0x400>;
583 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
584 clocks = <&topckgen CLK_TOP_UART_SEL>,
585 <&pericfg CLK_PERI_UART4_PD>;
586 clock-names = "baud", "bus";
590 audsys: clock-controller@11220000 {
591 compatible = "mediatek,mt7622-audsys", "syscon";
592 reg = <0 0x11220000 0 0x2000>;
595 afe: audio-controller {
596 compatible = "mediatek,mt7622-audio";
597 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
598 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
599 interrupt-names = "afe", "asys";
601 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
602 <&topckgen CLK_TOP_AUD1_SEL>,
603 <&topckgen CLK_TOP_AUD2_SEL>,
604 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
605 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
606 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
607 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
608 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
609 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
610 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
611 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
612 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
613 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
614 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
615 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
616 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
617 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
618 <&audsys CLK_AUDIO_I2SO1>,
619 <&audsys CLK_AUDIO_I2SO2>,
620 <&audsys CLK_AUDIO_I2SO3>,
621 <&audsys CLK_AUDIO_I2SO4>,
622 <&audsys CLK_AUDIO_I2SIN1>,
623 <&audsys CLK_AUDIO_I2SIN2>,
624 <&audsys CLK_AUDIO_I2SIN3>,
625 <&audsys CLK_AUDIO_I2SIN4>,
626 <&audsys CLK_AUDIO_ASRCO1>,
627 <&audsys CLK_AUDIO_ASRCO2>,
628 <&audsys CLK_AUDIO_ASRCO3>,
629 <&audsys CLK_AUDIO_ASRCO4>,
630 <&audsys CLK_AUDIO_AFE>,
631 <&audsys CLK_AUDIO_AFE_CONN>,
632 <&audsys CLK_AUDIO_A1SYS>,
633 <&audsys CLK_AUDIO_A2SYS>;
635 clock-names = "infra_sys_audio_clk",
636 "top_audio_mux1_sel",
637 "top_audio_mux2_sel",
638 "top_audio_a1sys_hp",
639 "top_audio_a2sys_hp",
669 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
670 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
671 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
672 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
673 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
674 <&topckgen CLK_TOP_AUD2PLL>;
675 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
680 compatible = "mediatek,mt7622-mmc";
681 reg = <0 0x11230000 0 0x1000>;
682 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
683 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
684 <&topckgen CLK_TOP_MSDC50_0_SEL>;
685 clock-names = "source", "hclk";
690 compatible = "mediatek,mt7622-mmc";
691 reg = <0 0x11240000 0 0x1000>;
692 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
693 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
694 <&topckgen CLK_TOP_AXI_SEL>;
695 clock-names = "source", "hclk";
699 ssusbsys: ssusbsys@1a000000 {
700 compatible = "mediatek,mt7622-ssusbsys",
702 reg = <0 0x1a000000 0 0x1000>;
707 ssusb: usb@1a0c0000 {
708 compatible = "mediatek,mt7622-xhci",
710 reg = <0 0x1a0c0000 0 0x01000>,
711 <0 0x1a0c4700 0 0x0100>;
712 reg-names = "mac", "ippc";
713 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
714 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
715 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
716 <&ssusbsys CLK_SSUSB_REF_EN>,
717 <&ssusbsys CLK_SSUSB_MCU_EN>,
718 <&ssusbsys CLK_SSUSB_DMA_EN>;
719 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
720 phys = <&u2port0 PHY_TYPE_USB2>,
721 <&u3port0 PHY_TYPE_USB3>,
722 <&u2port1 PHY_TYPE_USB2>;
727 u3phy: usb-phy@1a0c4000 {
728 compatible = "mediatek,mt7622-u3phy",
729 "mediatek,generic-tphy-v1";
730 reg = <0 0x1a0c4000 0 0x700>;
731 #address-cells = <2>;
736 u2port0: usb-phy@1a0c4800 {
737 reg = <0 0x1a0c4800 0 0x0100>;
739 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
743 u3port0: usb-phy@1a0c4900 {
744 reg = <0 0x1a0c4900 0 0x0700>;
750 u2port1: usb-phy@1a0c5000 {
751 reg = <0 0x1a0c5000 0 0x0100>;
753 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
758 pciesys: pciesys@1a100800 {
759 compatible = "mediatek,mt7622-pciesys",
761 reg = <0 0x1a100800 0 0x1000>;
766 pcie: pcie@1a140000 {
767 compatible = "mediatek,mt7622-pcie";
769 reg = <0 0x1a140000 0 0x1000>,
770 <0 0x1a143000 0 0x1000>,
771 <0 0x1a145000 0 0x1000>;
772 reg-names = "subsys", "port0", "port1";
773 #address-cells = <3>;
775 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
776 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
777 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
778 <&pciesys CLK_PCIE_P1_MAC_EN>,
779 <&pciesys CLK_PCIE_P0_AHB_EN>,
780 <&pciesys CLK_PCIE_P0_AHB_EN>,
781 <&pciesys CLK_PCIE_P0_AUX_EN>,
782 <&pciesys CLK_PCIE_P1_AUX_EN>,
783 <&pciesys CLK_PCIE_P0_AXI_EN>,
784 <&pciesys CLK_PCIE_P1_AXI_EN>,
785 <&pciesys CLK_PCIE_P0_OBFF_EN>,
786 <&pciesys CLK_PCIE_P1_OBFF_EN>,
787 <&pciesys CLK_PCIE_P0_PIPE_EN>,
788 <&pciesys CLK_PCIE_P1_PIPE_EN>;
789 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
790 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
791 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
792 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
793 bus-range = <0x00 0xff>;
794 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
798 reg = <0x0000 0 0 0 0>;
799 #address-cells = <3>;
801 #interrupt-cells = <1>;
806 interrupt-map-mask = <0 0 0 7>;
807 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
808 <0 0 0 2 &pcie_intc0 1>,
809 <0 0 0 3 &pcie_intc0 2>,
810 <0 0 0 4 &pcie_intc0 3>;
811 pcie_intc0: interrupt-controller {
812 interrupt-controller;
813 #address-cells = <0>;
814 #interrupt-cells = <1>;
819 reg = <0x0800 0 0 0 0>;
820 #address-cells = <3>;
822 #interrupt-cells = <1>;
827 interrupt-map-mask = <0 0 0 7>;
828 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
829 <0 0 0 2 &pcie_intc1 1>,
830 <0 0 0 3 &pcie_intc1 2>,
831 <0 0 0 4 &pcie_intc1 3>;
832 pcie_intc1: interrupt-controller {
833 interrupt-controller;
834 #address-cells = <0>;
835 #interrupt-cells = <1>;
840 sata: sata@1a200000 {
841 compatible = "mediatek,mt7622-ahci",
843 reg = <0 0x1a200000 0 0x1100>;
844 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
845 interrupt-names = "hostc";
846 clocks = <&pciesys CLK_SATA_AHB_EN>,
847 <&pciesys CLK_SATA_AXI_EN>,
848 <&pciesys CLK_SATA_ASIC_EN>,
849 <&pciesys CLK_SATA_RBC_EN>,
850 <&pciesys CLK_SATA_PM_EN>;
851 clock-names = "ahb", "axi", "asic", "rbc", "pm";
852 phys = <&sata_port PHY_TYPE_SATA>;
853 phy-names = "sata-phy";
854 ports-implemented = <0x1>;
855 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
856 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
857 <&pciesys MT7622_SATA_PHY_SW_RST>,
858 <&pciesys MT7622_SATA_PHY_REG_RST>;
859 reset-names = "axi", "sw", "reg";
860 mediatek,phy-mode = <&pciesys>;
864 sata_phy: sata-phy@1a243000 {
865 compatible = "mediatek,generic-tphy-v1";
866 #address-cells = <2>;
871 sata_port: sata-phy@1a243000 {
872 reg = <0 0x1a243000 0 0x0100>;
873 clocks = <&topckgen CLK_TOP_ETH_500M>;
879 ethsys: syscon@1b000000 {
880 compatible = "mediatek,mt7622-ethsys",
882 reg = <0 0x1b000000 0 0x1000>;
887 hsdma: dma-controller@1b007000 {
888 compatible = "mediatek,mt7622-hsdma";
889 reg = <0 0x1b007000 0 0x1000>;
890 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
891 clocks = <ðsys CLK_ETH_HSDMA_EN>;
892 clock-names = "hsdma";
893 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
897 eth: ethernet@1b100000 {
898 compatible = "mediatek,mt7622-eth",
899 "mediatek,mt2701-eth",
901 reg = <0 0x1b100000 0 0x20000>;
902 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
903 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
904 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
905 clocks = <&topckgen CLK_TOP_ETH_SEL>,
906 <ðsys CLK_ETH_ESW_EN>,
907 <ðsys CLK_ETH_GP0_EN>,
908 <ðsys CLK_ETH_GP1_EN>,
909 <ðsys CLK_ETH_GP2_EN>,
910 <&sgmiisys CLK_SGMII_TX250M_EN>,
911 <&sgmiisys CLK_SGMII_RX250M_EN>,
912 <&sgmiisys CLK_SGMII_CDR_REF>,
913 <&sgmiisys CLK_SGMII_CDR_FB>,
914 <&topckgen CLK_TOP_SGMIIPLL>,
915 <&apmixedsys CLK_APMIXED_ETH2PLL>;
916 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
917 "sgmii_tx250m", "sgmii_rx250m",
918 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
920 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
921 mediatek,ethsys = <ðsys>;
922 mediatek,sgmiisys = <&sgmiisys>;
923 #address-cells = <1>;
928 sgmiisys: sgmiisys@1b128000 {
929 compatible = "mediatek,mt7622-sgmiisys",
931 reg = <0 0x1b128000 0 0x1000>;