arch/arm64/boot/dts/mediatek/mt7622.dtsi

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/clock/mt7622-clk.h>
  12 #include <dt-bindings/phy/phy.h>
  13 #include <dt-bindings/power/mt7622-power.h>
  14 #include <dt-bindings/reset/mt7622-reset.h>
  15 #include <dt-bindings/thermal/thermal.h>
  16
  17 / {
  18         compatible = "mediatek,mt7622";
  19         interrupt-parent = <&sysirq>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         cpu_opp_table: opp-table {
  24                 compatible = "operating-points-v2";
  25                 opp-shared;
  26                 opp-300000000 {
  27                         opp-hz = /bits/ 64 <30000000>;
  28                         opp-microvolt = <950000>;
  29                 };
  30
  31                 opp-437500000 {
  32                         opp-hz = /bits/ 64 <437500000>;
  33                         opp-microvolt = <1000000>;
  34                 };
  35
  36                 opp-600000000 {
  37                         opp-hz = /bits/ 64 <600000000>;
  38                         opp-microvolt = <1050000>;
  39                 };
  40
  41                 opp-812500000 {
  42                         opp-hz = /bits/ 64 <812500000>;
  43                         opp-microvolt = <1100000>;
  44                 };
  45
  46                 opp-1025000000 {
  47                         opp-hz = /bits/ 64 <1025000000>;
  48                         opp-microvolt = <1150000>;
  49                 };
  50
  51                 opp-1137500000 {
  52                         opp-hz = /bits/ 64 <1137500000>;
  53                         opp-microvolt = <1200000>;
  54                 };
  55
  56                 opp-1262500000 {
  57                         opp-hz = /bits/ 64 <1262500000>;
  58                         opp-microvolt = <1250000>;
  59                 };
  60
  61                 opp-1350000000 {
  62                         opp-hz = /bits/ 64 <1350000000>;
  63                         opp-microvolt = <1310000>;
  64                 };
  65         };
  66
  67         cpus {
  68                 #address-cells = <2>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x0>;
  75                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  76                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  77                         clock-names = "cpu", "intermediate";
  78                         operating-points-v2 = <&cpu_opp_table>;
  79                         #cooling-cells = <2>;
  80                         enable-method = "psci";
  81                         clock-frequency = <1300000000>;
  82                         cci-control-port = <&cci_control2>;
  83                 };
  84
  85                 cpu1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53", "arm,armv8";
  88                         reg = <0x0 0x1>;
  89                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
  90                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
  91                         clock-names = "cpu", "intermediate";
  92                         operating-points-v2 = <&cpu_opp_table>;
  93                         #cooling-cells = <2>;
  94                         enable-method = "psci";
  95                         clock-frequency = <1300000000>;
  96                         cci-control-port = <&cci_control2>;
  97                 };
  98         };
  99
 100         pwrap_clk: dummy40m {
 101                 compatible = "fixed-clock";
 102                 clock-frequency = <40000000>;
 103                 #clock-cells = <0>;
 104         };
 105
 106         clk25m: oscillator {
 107                 compatible = "fixed-clock";
 108                 #clock-cells = <0>;
 109                 clock-frequency = <25000000>;
 110                 clock-output-names = "clkxtal";
 111         };
 112
 113         psci {
 114                 compatible  = "arm,psci-0.2";
 115                 method      = "smc";
 116         };
 117
 118         pmu {
 119                 compatible = "arm,cortex-a53-pmu";
 120                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
 121                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
 122                 interrupt-affinity = <&cpu0>, <&cpu1>;
 123         };
 124
 125         reserved-memory {
 126                 #address-cells = <2>;
 127                 #size-cells = <2>;
 128                 ranges;
 129
 130                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 131                 secmon_reserved: secmon@43000000 {
 132                         reg = <0 0x43000000 0 0x30000>;
 133                         no-map;
 134                 };
 135         };
 136
 137         thermal-zones {
 138                 cpu_thermal: cpu-thermal {
 139                         polling-delay-passive = <1000>;
 140                         polling-delay = <1000>;
 141
 142                         thermal-sensors = <&thermal 0>;
 143
 144                         trips {
 145                                 cpu_passive: cpu-passive {
 146                                         temperature = <47000>;
 147                                         hysteresis = <2000>;
 148                                         type = "passive";
 149                                 };
 150
 151                                 cpu_active: cpu-active {
 152                                         temperature = <67000>;
 153                                         hysteresis = <2000>;
 154                                         type = "active";
 155                                 };
 156
 157                                 cpu_hot: cpu-hot {
 158                                         temperature = <87000>;
 159                                         hysteresis = <2000>;
 160                                         type = "hot";
 161                                 };
 162
 163                                 cpu-crit {
 164                                         temperature = <107000>;
 165                                         hysteresis = <2000>;
 166                                         type = "critical";
 167                                 };
 168                         };
 169
 170                         cooling-maps {
 171                                 map0 {
 172                                         trip = <&cpu_passive>;
 173                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 174                                 };
 175
 176                                 map1 {
 177                                         trip = <&cpu_active>;
 178                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 179                                 };
 180
 181                                 map2 {
 182                                         trip = <&cpu_hot>;
 183                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 184                                 };
 185                         };
 186                 };
 187         };
 188
 189         timer {
 190                 compatible = "arm,armv8-timer";
 191                 interrupt-parent = <&gic>;
 192                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 193                               IRQ_TYPE_LEVEL_HIGH)>,
 194                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 195                               IRQ_TYPE_LEVEL_HIGH)>,
 196                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 197                               IRQ_TYPE_LEVEL_HIGH)>,
 198                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 199                               IRQ_TYPE_LEVEL_HIGH)>;
 200         };
 201
 202         infracfg: infracfg@10000000 {
 203                 compatible = "mediatek,mt7622-infracfg",
 204                              "syscon";
 205                 reg = <0 0x10000000 0 0x1000>;
 206                 #clock-cells = <1>;
 207                 #reset-cells = <1>;
 208         };
 209
 210         pwrap: pwrap@10001000 {
 211                 compatible = "mediatek,mt7622-pwrap";
 212                 reg = <0 0x10001000 0 0x250>;
 213                 reg-names = "pwrap";
 214                 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
 215                 clock-names = "spi", "wrap";
 216                 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
 217                 reset-names = "pwrap";
 218                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 219                 status = "disabled";
 220         };
 221
 222         pericfg: pericfg@10002000 {
 223                 compatible = "mediatek,mt7622-pericfg",
 224                              "syscon";
 225                 reg = <0 0x10002000 0 0x1000>;
 226                 #clock-cells = <1>;
 227                 #reset-cells = <1>;
 228         };
 229
 230         timer: timer@10004000 {
 231                 compatible = "mediatek,mt7622-timer",
 232                              "mediatek,mt6577-timer";
 233                 reg = <0 0x10004000 0 0x80>;
 234                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
 235                 clocks = <&infracfg CLK_INFRA_APXGPT_PD>,
 236                          <&topckgen CLK_TOP_RTC>;
 237                 clock-names = "system-clk", "rtc-clk";
 238         };
 239
 240         scpsys: scpsys@10006000 {
 241                 compatible = "mediatek,mt7622-scpsys",
 242                              "syscon";
 243                 #power-domain-cells = <1>;
 244                 reg = <0 0x10006000 0 0x1000>;
 245                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 249                 infracfg = <&infracfg>;
 250                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 251                 clock-names = "hif_sel";
 252         };
 253
 254         cir: cir@10009000 {
 255                 compatible = "mediatek,mt7622-cir";
 256                 reg = <0 0x10009000 0 0x1000>;
 257                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
 258                 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
 259                          <&topckgen CLK_TOP_AXI_SEL>;
 260                 clock-names = "clk", "bus";
 261                 status = "disabled";
 262         };
 263
 264         sysirq: interrupt-controller@10200620 {
 265                 compatible = "mediatek,mt7622-sysirq",
 266                              "mediatek,mt6577-sysirq";
 267                 interrupt-controller;
 268                 #interrupt-cells = <3>;
 269                 interrupt-parent = <&gic>;
 270                 reg = <0 0x10200620 0 0x20>;
 271         };
 272
 273         efuse: efuse@10206000 {
 274                 compatible = "mediatek,mt7622-efuse",
 275                              "mediatek,efuse";
 276                 reg = <0 0x10206000 0 0x1000>;
 277                 #address-cells = <1>;
 278                 #size-cells = <1>;
 279
 280                 thermal_calibration: calib@198 {
 281                         reg = <0x198 0xc>;
 282                 };
 283         };
 284
 285         apmixedsys: apmixedsys@10209000 {
 286                 compatible = "mediatek,mt7622-apmixedsys",
 287                              "syscon";
 288                 reg = <0 0x10209000 0 0x1000>;
 289                 #clock-cells = <1>;
 290         };
 291
 292         topckgen: topckgen@10210000 {
 293                 compatible = "mediatek,mt7622-topckgen",
 294                              "syscon";
 295                 reg = <0 0x10210000 0 0x1000>;
 296                 #clock-cells = <1>;
 297         };
 298
 299         rng: rng@1020f000 {
 300                 compatible = "mediatek,mt7622-rng",
 301                              "mediatek,mt7623-rng";
 302                 reg = <0 0x1020f000 0 0x1000>;
 303                 clocks = <&infracfg CLK_INFRA_TRNG>;
 304                 clock-names = "rng";
 305         };
 306
 307         pio: pinctrl@10211000 {
 308                 compatible = "mediatek,mt7622-pinctrl";
 309                 reg = <0 0x10211000 0 0x1000>,
 310                       <0 0x10005000 0 0x1000>;
 311                 reg-names = "base", "eint";
 312                 gpio-controller;
 313                 #gpio-cells = <2>;
 314                 gpio-ranges = <&pio 0 0 103>;
 315                 interrupt-controller;
 316                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 317                 interrupt-parent = <&gic>;
 318                 #interrupt-cells = <2>;
 319         };
 320
 321         watchdog: watchdog@10212000 {
 322                 compatible = "mediatek,mt7622-wdt",
 323                              "mediatek,mt6589-wdt";
 324                 reg = <0 0x10212000 0 0x800>;
 325         };
 326
 327         rtc: rtc@10212800 {
 328                 compatible = "mediatek,mt7622-rtc",
 329                              "mediatek,soc-rtc";
 330                 reg = <0 0x10212800 0 0x200>;
 331                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 332                 clocks = <&topckgen CLK_TOP_RTC>;
 333                 clock-names = "rtc";
 334         };
 335
 336         gic: interrupt-controller@10300000 {
 337                 compatible = "arm,gic-400";
 338                 interrupt-controller;
 339                 #interrupt-cells = <3>;
 340                 interrupt-parent = <&gic>;
 341                 reg = <0 0x10310000 0 0x1000>,
 342                       <0 0x10320000 0 0x1000>,
 343                       <0 0x10340000 0 0x2000>,
 344                       <0 0x10360000 0 0x2000>;
 345         };
 346
 347         cci: cci@10390000 {
 348                 compatible = "arm,cci-400";
 349                 #address-cells = <1>;
 350                 #size-cells = <1>;
 351                 reg = <0 0x10390000 0 0x1000>;
 352                 ranges = <0 0 0x10390000 0x10000>;
 353
 354                 cci_control0: slave-if@1000 {
 355                         compatible = "arm,cci-400-ctrl-if";
 356                         interface-type = "ace-lite";
 357                         reg = <0x1000 0x1000>;
 358                 };
 359
 360                 cci_control1: slave-if@4000 {
 361                         compatible = "arm,cci-400-ctrl-if";
 362                         interface-type = "ace";
 363                         reg = <0x4000 0x1000>;
 364                 };
 365
 366                 cci_control2: slave-if@5000 {
 367                         compatible = "arm,cci-400-ctrl-if";
 368                         interface-type = "ace";
 369                         reg = <0x5000 0x1000>;
 370                 };
 371
 372                 pmu@9000 {
 373                         compatible = "arm,cci-400-pmu,r1";
 374                         reg = <0x9000 0x5000>;
 375                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 376                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 377                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 378                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 379                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 380                 };
 381         };
 382
 383         auxadc: adc@11001000 {
 384                 compatible = "mediatek,mt7622-auxadc";
 385                 reg = <0 0x11001000 0 0x1000>;
 386                 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
 387                 clock-names = "main";
 388                 #io-channel-cells = <1>;
 389         };
 390
 391         uart0: serial@11002000 {
 392                 compatible = "mediatek,mt7622-uart",
 393                              "mediatek,mt6577-uart";
 394                 reg = <0 0x11002000 0 0x400>;
 395                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 396                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 397                          <&pericfg CLK_PERI_UART0_PD>;
 398                 clock-names = "baud", "bus";
 399                 status = "disabled";
 400         };
 401
 402         uart1: serial@11003000 {
 403                 compatible = "mediatek,mt7622-uart",
 404                              "mediatek,mt6577-uart";
 405                 reg = <0 0x11003000 0 0x400>;
 406                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 407                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 408                          <&pericfg CLK_PERI_UART1_PD>;
 409                 clock-names = "baud", "bus";
 410                 status = "disabled";
 411         };
 412
 413         uart2: serial@11004000 {
 414                 compatible = "mediatek,mt7622-uart",
 415                              "mediatek,mt6577-uart";
 416                 reg = <0 0x11004000 0 0x400>;
 417                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 418                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 419                          <&pericfg CLK_PERI_UART2_PD>;
 420                 clock-names = "baud", "bus";
 421                 status = "disabled";
 422         };
 423
 424         uart3: serial@11005000 {
 425                 compatible = "mediatek,mt7622-uart",
 426                              "mediatek,mt6577-uart";
 427                 reg = <0 0x11005000 0 0x400>;
 428                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
 429                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 430                          <&pericfg CLK_PERI_UART3_PD>;
 431                 clock-names = "baud", "bus";
 432                 status = "disabled";
 433         };
 434
 435         pwm: pwm@11006000 {
 436                 compatible = "mediatek,mt7622-pwm";
 437                 reg = <0 0x11006000 0 0x1000>;
 438                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 439                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 440                          <&pericfg CLK_PERI_PWM_PD>,
 441                          <&pericfg CLK_PERI_PWM1_PD>,
 442                          <&pericfg CLK_PERI_PWM2_PD>,
 443                          <&pericfg CLK_PERI_PWM3_PD>,
 444                          <&pericfg CLK_PERI_PWM4_PD>,
 445                          <&pericfg CLK_PERI_PWM5_PD>,
 446                          <&pericfg CLK_PERI_PWM6_PD>;
 447                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 448                               "pwm5", "pwm6";
 449                 status = "disabled";
 450         };
 451
 452         i2c0: i2c@11007000 {
 453                 compatible = "mediatek,mt7622-i2c";
 454                 reg = <0 0x11007000 0 0x90>,
 455                       <0 0x11000100 0 0x80>;
 456                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 457                 clock-div = <16>;
 458                 clocks = <&pericfg CLK_PERI_I2C0_PD>,
 459                          <&pericfg CLK_PERI_AP_DMA_PD>;
 460                 clock-names = "main", "dma";
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 status = "disabled";
 464         };
 465
 466         i2c1: i2c@11008000 {
 467                 compatible = "mediatek,mt7622-i2c";
 468                 reg = <0 0x11008000 0 0x90>,
 469                       <0 0x11000180 0 0x80>;
 470                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 471                 clock-div = <16>;
 472                 clocks = <&pericfg CLK_PERI_I2C1_PD>,
 473                          <&pericfg CLK_PERI_AP_DMA_PD>;
 474                 clock-names = "main", "dma";
 475                 #address-cells = <1>;
 476                 #size-cells = <0>;
 477                 status = "disabled";
 478         };
 479
 480         i2c2: i2c@11009000 {
 481                 compatible = "mediatek,mt7622-i2c";
 482                 reg = <0 0x11009000 0 0x90>,
 483                       <0 0x11000200 0 0x80>;
 484                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 485                 clock-div = <16>;
 486                 clocks = <&pericfg CLK_PERI_I2C2_PD>,
 487                          <&pericfg CLK_PERI_AP_DMA_PD>;
 488                 clock-names = "main", "dma";
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491                 status = "disabled";
 492         };
 493
 494         spi0: spi@1100a000 {
 495                 compatible = "mediatek,mt7622-spi";
 496                 reg = <0 0x1100a000 0 0x100>;
 497                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
 498                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 499                          <&topckgen CLK_TOP_SPI0_SEL>,
 500                          <&pericfg CLK_PERI_SPI0_PD>;
 501                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 502                 #address-cells = <1>;
 503                 #size-cells = <0>;
 504                 status = "disabled";
 505         };
 506
 507         thermal: thermal@1100b000 {
 508                 #thermal-sensor-cells = <1>;
 509                 compatible = "mediatek,mt7622-thermal";
 510                 reg = <0 0x1100b000 0 0x1000>;
 511                 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
 512                 clocks = <&pericfg CLK_PERI_THERM_PD>,
 513                          <&pericfg CLK_PERI_AUXADC_PD>;
 514                 clock-names = "therm", "auxadc";
 515                 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
 516                 reset-names = "therm";
 517                 mediatek,auxadc = <&auxadc>;
 518                 mediatek,apmixedsys = <&apmixedsys>;
 519                 nvmem-cells = <&thermal_calibration>;
 520                 nvmem-cell-names = "calibration-data";
 521         };
 522
 523         btif: serial@1100c000 {
 524                 compatible = "mediatek,mt7622-btif",
 525                              "mediatek,mtk-btif";
 526                 reg = <0 0x1100c000 0 0x1000>;
 527                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
 528                 clocks = <&pericfg CLK_PERI_BTIF_PD>;
 529                 clock-names = "main";
 530                 reg-shift = <2>;
 531                 reg-io-width = <4>;
 532                 status = "disabled";
 533
 534                 bluetooth {
 535                         compatible = "mediatek,mt7622-bluetooth";
 536                         power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
 537                         clocks = <&clk25m>;
 538                         clock-names = "ref";
 539                 };
 540         };
 541
 542         nandc: nfi@1100d000 {
 543                 compatible = "mediatek,mt7622-nfc";
 544                 reg = <0 0x1100D000 0 0x1000>;
 545                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
 546                 clocks = <&pericfg CLK_PERI_NFI_PD>,
 547                          <&pericfg CLK_PERI_SNFI_PD>;
 548                 clock-names = "nfi_clk", "pad_clk";
 549                 ecc-engine = <&bch>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         bch: ecc@1100e000 {
 556                 compatible = "mediatek,mt7622-ecc";
 557                 reg = <0 0x1100e000 0 0x1000>;
 558                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
 559                 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
 560                 clock-names = "nfiecc_clk";
 561                 status = "disabled";
 562         };
 563
 564         nor_flash: spi@11014000 {
 565                 compatible = "mediatek,mt7622-nor",
 566                              "mediatek,mt8173-nor";
 567                 reg = <0 0x11014000 0 0xe0>;
 568                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
 569                          <&topckgen CLK_TOP_FLASH_SEL>;
 570                 clock-names = "spi", "sf";
 571                 #address-cells = <1>;
 572                 #size-cells = <0>;
 573                 status = "disabled";
 574         };
 575
 576         spi1: spi@11016000 {
 577                 compatible = "mediatek,mt7622-spi";
 578                 reg = <0 0x11016000 0 0x100>;
 579                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
 580                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 581                          <&topckgen CLK_TOP_SPI1_SEL>,
 582                          <&pericfg CLK_PERI_SPI1_PD>;
 583                 clock-names = "parent-clk", "sel-clk", "spi-clk";
 584                 #address-cells = <1>;
 585                 #size-cells = <0>;
 586                 status = "disabled";
 587         };
 588
 589         uart4: serial@11019000 {
 590                 compatible = "mediatek,mt7622-uart",
 591                              "mediatek,mt6577-uart";
 592                 reg = <0 0x11019000 0 0x400>;
 593                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 594                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 595                          <&pericfg CLK_PERI_UART4_PD>;
 596                 clock-names = "baud", "bus";
 597                 status = "disabled";
 598         };
 599
 600         audsys: clock-controller@11220000 {
 601                 compatible = "mediatek,mt7622-audsys", "syscon";
 602                 reg = <0 0x11220000 0 0x2000>;
 603                 #clock-cells = <1>;
 604
 605                 afe: audio-controller {
 606                         compatible = "mediatek,mt7622-audio";
 607                         interrupts =  <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
 608                                       <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
 609                         interrupt-names = "afe", "asys";
 610
 611                         clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
 612                                  <&topckgen CLK_TOP_AUD1_SEL>,
 613                                  <&topckgen CLK_TOP_AUD2_SEL>,
 614                                  <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
 615                                  <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
 616                                  <&topckgen CLK_TOP_I2S0_MCK_SEL>,
 617                                  <&topckgen CLK_TOP_I2S1_MCK_SEL>,
 618                                  <&topckgen CLK_TOP_I2S2_MCK_SEL>,
 619                                  <&topckgen CLK_TOP_I2S3_MCK_SEL>,
 620                                  <&topckgen CLK_TOP_I2S0_MCK_DIV>,
 621                                  <&topckgen CLK_TOP_I2S1_MCK_DIV>,
 622                                  <&topckgen CLK_TOP_I2S2_MCK_DIV>,
 623                                  <&topckgen CLK_TOP_I2S3_MCK_DIV>,
 624                                  <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
 625                                  <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
 626                                  <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
 627                                  <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
 628                                  <&audsys CLK_AUDIO_I2SO1>,
 629                                  <&audsys CLK_AUDIO_I2SO2>,
 630                                  <&audsys CLK_AUDIO_I2SO3>,
 631                                  <&audsys CLK_AUDIO_I2SO4>,
 632                                  <&audsys CLK_AUDIO_I2SIN1>,
 633                                  <&audsys CLK_AUDIO_I2SIN2>,
 634                                  <&audsys CLK_AUDIO_I2SIN3>,
 635                                  <&audsys CLK_AUDIO_I2SIN4>,
 636                                  <&audsys CLK_AUDIO_ASRCO1>,
 637                                  <&audsys CLK_AUDIO_ASRCO2>,
 638                                  <&audsys CLK_AUDIO_ASRCO3>,
 639                                  <&audsys CLK_AUDIO_ASRCO4>,
 640                                  <&audsys CLK_AUDIO_AFE>,
 641                                  <&audsys CLK_AUDIO_AFE_CONN>,
 642                                  <&audsys CLK_AUDIO_A1SYS>,
 643                                  <&audsys CLK_AUDIO_A2SYS>;
 644
 645                         clock-names = "infra_sys_audio_clk",
 646                                       "top_audio_mux1_sel",
 647                                       "top_audio_mux2_sel",
 648                                       "top_audio_a1sys_hp",
 649                                       "top_audio_a2sys_hp",
 650                                       "i2s0_src_sel",
 651                                       "i2s1_src_sel",
 652                                       "i2s2_src_sel",
 653                                       "i2s3_src_sel",
 654                                       "i2s0_src_div",
 655                                       "i2s1_src_div",
 656                                       "i2s2_src_div",
 657                                       "i2s3_src_div",
 658                                       "i2s0_mclk_en",
 659                                       "i2s1_mclk_en",
 660                                       "i2s2_mclk_en",
 661                                       "i2s3_mclk_en",
 662                                       "i2so0_hop_ck",
 663                                       "i2so1_hop_ck",
 664                                       "i2so2_hop_ck",
 665                                       "i2so3_hop_ck",
 666                                       "i2si0_hop_ck",
 667                                       "i2si1_hop_ck",
 668                                       "i2si2_hop_ck",
 669                                       "i2si3_hop_ck",
 670                                       "asrc0_out_ck",
 671                                       "asrc1_out_ck",
 672                                       "asrc2_out_ck",
 673                                       "asrc3_out_ck",
 674                                       "audio_afe_pd",
 675                                       "audio_afe_conn_pd",
 676                                       "audio_a1sys_pd",
 677                                       "audio_a2sys_pd";
 678
 679                         assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
 680                                           <&topckgen CLK_TOP_A2SYS_HP_SEL>,
 681                                           <&topckgen CLK_TOP_A1SYS_HP_DIV>,
 682                                           <&topckgen CLK_TOP_A2SYS_HP_DIV>;
 683                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
 684                                                  <&topckgen CLK_TOP_AUD2PLL>;
 685                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
 686                 };
 687         };
 688
 689         mmc0: mmc@11230000 {
 690                 compatible = "mediatek,mt7622-mmc";
 691                 reg = <0 0x11230000 0 0x1000>;
 692                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 693                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 694                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 695                 clock-names = "source", "hclk";
 696                 status = "disabled";
 697         };
 698
 699         mmc1: mmc@11240000 {
 700                 compatible = "mediatek,mt7622-mmc";
 701                 reg = <0 0x11240000 0 0x1000>;
 702                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 703                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 704                          <&topckgen CLK_TOP_AXI_SEL>;
 705                 clock-names = "source", "hclk";
 706                 status = "disabled";
 707         };
 708
 709         ssusbsys: ssusbsys@1a000000 {
 710                 compatible = "mediatek,mt7622-ssusbsys",
 711                              "syscon";
 712                 reg = <0 0x1a000000 0 0x1000>;
 713                 #clock-cells = <1>;
 714                 #reset-cells = <1>;
 715         };
 716
 717         ssusb: usb@1a0c0000 {
 718                 compatible = "mediatek,mt7622-xhci",
 719                              "mediatek,mtk-xhci";
 720                 reg = <0 0x1a0c0000 0 0x01000>,
 721                       <0 0x1a0c4700 0 0x0100>;
 722                 reg-names = "mac", "ippc";
 723                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 724                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
 725                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 726                          <&ssusbsys CLK_SSUSB_REF_EN>,
 727                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 728                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 729                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 730                 phys = <&u2port0 PHY_TYPE_USB2>,
 731                        <&u3port0 PHY_TYPE_USB3>,
 732                        <&u2port1 PHY_TYPE_USB2>;
 733
 734                 status = "disabled";
 735         };
 736
 737         u3phy: usb-phy@1a0c4000 {
 738                 compatible = "mediatek,mt7622-u3phy",
 739                              "mediatek,generic-tphy-v1";
 740                 reg = <0 0x1a0c4000 0 0x700>;
 741                 #address-cells = <2>;
 742                 #size-cells = <2>;
 743                 ranges;
 744                 status = "disabled";
 745
 746                 u2port0: usb-phy@1a0c4800 {
 747                         reg = <0 0x1a0c4800 0 0x0100>;
 748                         #phy-cells = <1>;
 749                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 750                         clock-names = "ref";
 751                 };
 752
 753                 u3port0: usb-phy@1a0c4900 {
 754                         reg = <0 0x1a0c4900 0 0x0700>;
 755                         #phy-cells = <1>;
 756                         clocks = <&clk25m>;
 757                         clock-names = "ref";
 758                 };
 759
 760                 u2port1: usb-phy@1a0c5000 {
 761                         reg = <0 0x1a0c5000 0 0x0100>;
 762                         #phy-cells = <1>;
 763                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 764                         clock-names = "ref";
 765                 };
 766         };
 767
 768         pciesys: pciesys@1a100800 {
 769                 compatible = "mediatek,mt7622-pciesys",
 770                              "syscon";
 771                 reg = <0 0x1a100800 0 0x1000>;
 772                 #clock-cells = <1>;
 773                 #reset-cells = <1>;
 774         };
 775
 776         pcie: pcie@1a140000 {
 777                 compatible = "mediatek,mt7622-pcie";
 778                 device_type = "pci";
 779                 reg = <0 0x1a140000 0 0x1000>,
 780                       <0 0x1a143000 0 0x1000>,
 781                       <0 0x1a145000 0 0x1000>;
 782                 reg-names = "subsys", "port0", "port1";
 783                 #address-cells = <3>;
 784                 #size-cells = <2>;
 785                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 786                              <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 787                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 788                          <&pciesys CLK_PCIE_P1_MAC_EN>,
 789                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 790                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 791                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 792                          <&pciesys CLK_PCIE_P1_AUX_EN>,
 793                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 794                          <&pciesys CLK_PCIE_P1_AXI_EN>,
 795                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 796                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
 797                          <&pciesys CLK_PCIE_P0_PIPE_EN>,
 798                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
 799                 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 800                               "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 801                               "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 802                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 803                 bus-range = <0x00 0xff>;
 804                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
 805                 status = "disabled";
 806
 807                 pcie0: pcie@0,0 {
 808                         reg = <0x0000 0 0 0 0>;
 809                         #address-cells = <3>;
 810                         #size-cells = <2>;
 811                         #interrupt-cells = <1>;
 812                         ranges;
 813                         status = "disabled";
 814
 815                         num-lanes = <1>;
 816                         interrupt-map-mask = <0 0 0 7>;
 817                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 818                                         <0 0 0 2 &pcie_intc0 1>,
 819                                         <0 0 0 3 &pcie_intc0 2>,
 820                                         <0 0 0 4 &pcie_intc0 3>;
 821                         pcie_intc0: interrupt-controller {
 822                                 interrupt-controller;
 823                                 #address-cells = <0>;
 824                                 #interrupt-cells = <1>;
 825                         };
 826                 };
 827
 828                 pcie1: pcie@1,0 {
 829                         reg = <0x0800 0 0 0 0>;
 830                         #address-cells = <3>;
 831                         #size-cells = <2>;
 832                         #interrupt-cells = <1>;
 833                         ranges;
 834                         status = "disabled";
 835
 836                         num-lanes = <1>;
 837                         interrupt-map-mask = <0 0 0 7>;
 838                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 839                                         <0 0 0 2 &pcie_intc1 1>,
 840                                         <0 0 0 3 &pcie_intc1 2>,
 841                                         <0 0 0 4 &pcie_intc1 3>;
 842                         pcie_intc1: interrupt-controller {
 843                                 interrupt-controller;
 844                                 #address-cells = <0>;
 845                                 #interrupt-cells = <1>;
 846                         };
 847                 };
 848         };
 849
 850         sata: sata@1a200000 {
 851                 compatible = "mediatek,mt7622-ahci",
 852                              "mediatek,mtk-ahci";
 853                 reg = <0 0x1a200000 0 0x1100>;
 854                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 855                 interrupt-names = "hostc";
 856                 clocks = <&pciesys CLK_SATA_AHB_EN>,
 857                          <&pciesys CLK_SATA_AXI_EN>,
 858                          <&pciesys CLK_SATA_ASIC_EN>,
 859                          <&pciesys CLK_SATA_RBC_EN>,
 860                          <&pciesys CLK_SATA_PM_EN>;
 861                 clock-names = "ahb", "axi", "asic", "rbc", "pm";
 862                 phys = <&sata_port PHY_TYPE_SATA>;
 863                 phy-names = "sata-phy";
 864                 ports-implemented = <0x1>;
 865                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
 866                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
 867                          <&pciesys MT7622_SATA_PHY_SW_RST>,
 868                          <&pciesys MT7622_SATA_PHY_REG_RST>;
 869                 reset-names = "axi", "sw", "reg";
 870                 mediatek,phy-mode = <&pciesys>;
 871                 status = "disabled";
 872         };
 873
 874         sata_phy: sata-phy@1a243000 {
 875                 compatible = "mediatek,generic-tphy-v1";
 876                 #address-cells = <2>;
 877                 #size-cells = <2>;
 878                 ranges;
 879                 status = "disabled";
 880
 881                 sata_port: sata-phy@1a243000 {
 882                         reg = <0 0x1a243000 0 0x0100>;
 883                         clocks = <&topckgen CLK_TOP_ETH_500M>;
 884                         clock-names = "ref";
 885                         #phy-cells = <1>;
 886                 };
 887         };
 888
 889         ethsys: syscon@1b000000 {
 890                 compatible = "mediatek,mt7622-ethsys",
 891                              "syscon";
 892                 reg = <0 0x1b000000 0 0x1000>;
 893                 #clock-cells = <1>;
 894                 #reset-cells = <1>;
 895         };
 896
 897         hsdma: dma-controller@1b007000 {
 898                 compatible = "mediatek,mt7622-hsdma";
 899                 reg = <0 0x1b007000 0 0x1000>;
 900                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
 901                 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
 902                 clock-names = "hsdma";
 903                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 904                 #dma-cells = <1>;
 905         };
 906
 907         eth: ethernet@1b100000 {
 908                 compatible = "mediatek,mt7622-eth",
 909                              "mediatek,mt2701-eth",
 910                              "syscon";
 911                 reg = <0 0x1b100000 0 0x20000>;
 912                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
 913                              <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
 914                              <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
 915                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 916                          <&ethsys CLK_ETH_ESW_EN>,
 917                          <&ethsys CLK_ETH_GP0_EN>,
 918                          <&ethsys CLK_ETH_GP1_EN>,
 919                          <&ethsys CLK_ETH_GP2_EN>,
 920                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 921                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 922                          <&sgmiisys CLK_SGMII_CDR_REF>,
 923                          <&sgmiisys CLK_SGMII_CDR_FB>,
 924                          <&topckgen CLK_TOP_SGMIIPLL>,
 925                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 926                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 927                               "sgmii_tx250m", "sgmii_rx250m",
 928                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 929                               "eth2pll";
 930                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
 931                 mediatek,ethsys = <&ethsys>;
 932                 mediatek,sgmiisys = <&sgmiisys>;
 933                 #address-cells = <1>;
 934                 #size-cells = <0>;
 935                 status = "disabled";
 936         };
 937
 938         sgmiisys: sgmiisys@1b128000 {
 939                 compatible = "mediatek,mt7622-sgmiisys",
 940                              "syscon";
 941                 reg = <0 0x1b128000 0 0x1000>;
 942                 #clock-cells = <1>;
 943         };
 944 };