Merge tag 'pci-v4.21-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / mediatek / mt7622.dtsi
1 /*
2  * Copyright (c) 2017 MediaTek Inc.
3  * Author: Ming Huang <ming.huang@mediatek.com>
4  *         Sean Wang <sean.wang@mediatek.com>
5  *
6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7  */
8
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
16
17 / {
18         compatible = "mediatek,mt7622";
19         interrupt-parent = <&sysirq>;
20         #address-cells = <2>;
21         #size-cells = <2>;
22
23         cpu_opp_table: opp-table {
24                 compatible = "operating-points-v2";
25                 opp-shared;
26                 opp-300000000 {
27                         opp-hz = /bits/ 64 <30000000>;
28                         opp-microvolt = <950000>;
29                 };
30
31                 opp-437500000 {
32                         opp-hz = /bits/ 64 <437500000>;
33                         opp-microvolt = <1000000>;
34                 };
35
36                 opp-600000000 {
37                         opp-hz = /bits/ 64 <600000000>;
38                         opp-microvolt = <1050000>;
39                 };
40
41                 opp-812500000 {
42                         opp-hz = /bits/ 64 <812500000>;
43                         opp-microvolt = <1100000>;
44                 };
45
46                 opp-1025000000 {
47                         opp-hz = /bits/ 64 <1025000000>;
48                         opp-microvolt = <1150000>;
49                 };
50
51                 opp-1137500000 {
52                         opp-hz = /bits/ 64 <1137500000>;
53                         opp-microvolt = <1200000>;
54                 };
55
56                 opp-1262500000 {
57                         opp-hz = /bits/ 64 <1262500000>;
58                         opp-microvolt = <1250000>;
59                 };
60
61                 opp-1350000000 {
62                         opp-hz = /bits/ 64 <1350000000>;
63                         opp-microvolt = <1310000>;
64                 };
65         };
66
67         cpus {
68                 #address-cells = <2>;
69                 #size-cells = <0>;
70
71                 cpu0: cpu@0 {
72                         device_type = "cpu";
73                         compatible = "arm,cortex-a53", "arm,armv8";
74                         reg = <0x0 0x0>;
75                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77                         clock-names = "cpu", "intermediate";
78                         operating-points-v2 = <&cpu_opp_table>;
79                         #cooling-cells = <2>;
80                         enable-method = "psci";
81                         clock-frequency = <1300000000>;
82                         cci-control-port = <&cci_control2>;
83                 };
84
85                 cpu1: cpu@1 {
86                         device_type = "cpu";
87                         compatible = "arm,cortex-a53", "arm,armv8";
88                         reg = <0x0 0x1>;
89                         clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90                                  <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
91                         clock-names = "cpu", "intermediate";
92                         operating-points-v2 = <&cpu_opp_table>;
93                         #cooling-cells = <2>;
94                         enable-method = "psci";
95                         clock-frequency = <1300000000>;
96                         cci-control-port = <&cci_control2>;
97                 };
98         };
99
100         pwrap_clk: dummy40m {
101                 compatible = "fixed-clock";
102                 clock-frequency = <40000000>;
103                 #clock-cells = <0>;
104         };
105
106         clk25m: oscillator {
107                 compatible = "fixed-clock";
108                 #clock-cells = <0>;
109                 clock-frequency = <25000000>;
110                 clock-output-names = "clkxtal";
111         };
112
113         psci {
114                 compatible  = "arm,psci-0.2";
115                 method      = "smc";
116         };
117
118         pmu {
119                 compatible = "arm,cortex-a53-pmu";
120                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
121                              <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
122                 interrupt-affinity = <&cpu0>, <&cpu1>;
123         };
124
125         reserved-memory {
126                 #address-cells = <2>;
127                 #size-cells = <2>;
128                 ranges;
129
130                 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
131                 secmon_reserved: secmon@43000000 {
132                         reg = <0 0x43000000 0 0x30000>;
133                         no-map;
134                 };
135         };
136
137         thermal-zones {
138                 cpu_thermal: cpu-thermal {
139                         polling-delay-passive = <1000>;
140                         polling-delay = <1000>;
141
142                         thermal-sensors = <&thermal 0>;
143
144                         trips {
145                                 cpu_passive: cpu-passive {
146                                         temperature = <47000>;
147                                         hysteresis = <2000>;
148                                         type = "passive";
149                                 };
150
151                                 cpu_active: cpu-active {
152                                         temperature = <67000>;
153                                         hysteresis = <2000>;
154                                         type = "active";
155                                 };
156
157                                 cpu_hot: cpu-hot {
158                                         temperature = <87000>;
159                                         hysteresis = <2000>;
160                                         type = "hot";
161                                 };
162
163                                 cpu-crit {
164                                         temperature = <107000>;
165                                         hysteresis = <2000>;
166                                         type = "critical";
167                                 };
168                         };
169
170                         cooling-maps {
171                                 map0 {
172                                         trip = <&cpu_passive>;
173                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
174                                 };
175
176                                 map1 {
177                                         trip = <&cpu_active>;
178                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
179                                 };
180
181                                 map2 {
182                                         trip = <&cpu_hot>;
183                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
184                                 };
185                         };
186                 };
187         };
188
189         timer {
190                 compatible = "arm,armv8-timer";
191                 interrupt-parent = <&gic>;
192                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
193                               IRQ_TYPE_LEVEL_HIGH)>,
194                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
195                               IRQ_TYPE_LEVEL_HIGH)>,
196                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
197                               IRQ_TYPE_LEVEL_HIGH)>,
198                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
199                               IRQ_TYPE_LEVEL_HIGH)>;
200         };
201
202         infracfg: infracfg@10000000 {
203                 compatible = "mediatek,mt7622-infracfg",
204                              "syscon";
205                 reg = <0 0x10000000 0 0x1000>;
206                 #clock-cells = <1>;
207                 #reset-cells = <1>;
208         };
209
210         pwrap: pwrap@10001000 {
211                 compatible = "mediatek,mt7622-pwrap";
212                 reg = <0 0x10001000 0 0x250>;
213                 reg-names = "pwrap";
214                 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
215                 clock-names = "spi", "wrap";
216                 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
217                 reset-names = "pwrap";
218                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
219                 status = "disabled";
220         };
221
222         pericfg: pericfg@10002000 {
223                 compatible = "mediatek,mt7622-pericfg",
224                              "syscon";
225                 reg = <0 0x10002000 0 0x1000>;
226                 #clock-cells = <1>;
227                 #reset-cells = <1>;
228         };
229
230         scpsys: scpsys@10006000 {
231                 compatible = "mediatek,mt7622-scpsys",
232                              "syscon";
233                 #power-domain-cells = <1>;
234                 reg = <0 0x10006000 0 0x1000>;
235                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
236                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
237                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
238                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
239                 infracfg = <&infracfg>;
240                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
241                 clock-names = "hif_sel";
242         };
243
244         cir: cir@10009000 {
245                 compatible = "mediatek,mt7622-cir";
246                 reg = <0 0x10009000 0 0x1000>;
247                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
248                 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
249                          <&topckgen CLK_TOP_AXI_SEL>;
250                 clock-names = "clk", "bus";
251                 status = "disabled";
252         };
253
254         sysirq: interrupt-controller@10200620 {
255                 compatible = "mediatek,mt7622-sysirq",
256                              "mediatek,mt6577-sysirq";
257                 interrupt-controller;
258                 #interrupt-cells = <3>;
259                 interrupt-parent = <&gic>;
260                 reg = <0 0x10200620 0 0x20>;
261         };
262
263         efuse: efuse@10206000 {
264                 compatible = "mediatek,mt7622-efuse",
265                              "mediatek,efuse";
266                 reg = <0 0x10206000 0 0x1000>;
267                 #address-cells = <1>;
268                 #size-cells = <1>;
269
270                 thermal_calibration: calib@198 {
271                         reg = <0x198 0xc>;
272                 };
273         };
274
275         apmixedsys: apmixedsys@10209000 {
276                 compatible = "mediatek,mt7622-apmixedsys",
277                              "syscon";
278                 reg = <0 0x10209000 0 0x1000>;
279                 #clock-cells = <1>;
280         };
281
282         topckgen: topckgen@10210000 {
283                 compatible = "mediatek,mt7622-topckgen",
284                              "syscon";
285                 reg = <0 0x10210000 0 0x1000>;
286                 #clock-cells = <1>;
287         };
288
289         rng: rng@1020f000 {
290                 compatible = "mediatek,mt7622-rng",
291                              "mediatek,mt7623-rng";
292                 reg = <0 0x1020f000 0 0x1000>;
293                 clocks = <&infracfg CLK_INFRA_TRNG>;
294                 clock-names = "rng";
295         };
296
297         pio: pinctrl@10211000 {
298                 compatible = "mediatek,mt7622-pinctrl";
299                 reg = <0 0x10211000 0 0x1000>,
300                       <0 0x10005000 0 0x1000>;
301                 reg-names = "base", "eint";
302                 gpio-controller;
303                 #gpio-cells = <2>;
304                 gpio-ranges = <&pio 0 0 103>;
305                 interrupt-controller;
306                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
307                 interrupt-parent = <&gic>;
308                 #interrupt-cells = <2>;
309         };
310
311         watchdog: watchdog@10212000 {
312                 compatible = "mediatek,mt7622-wdt",
313                              "mediatek,mt6589-wdt";
314                 reg = <0 0x10212000 0 0x800>;
315         };
316
317         rtc: rtc@10212800 {
318                 compatible = "mediatek,mt7622-rtc",
319                              "mediatek,soc-rtc";
320                 reg = <0 0x10212800 0 0x200>;
321                 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
322                 clocks = <&topckgen CLK_TOP_RTC>;
323                 clock-names = "rtc";
324         };
325
326         gic: interrupt-controller@10300000 {
327                 compatible = "arm,gic-400";
328                 interrupt-controller;
329                 #interrupt-cells = <3>;
330                 interrupt-parent = <&gic>;
331                 reg = <0 0x10310000 0 0x1000>,
332                       <0 0x10320000 0 0x1000>,
333                       <0 0x10340000 0 0x2000>,
334                       <0 0x10360000 0 0x2000>;
335         };
336
337         cci: cci@10390000 {
338                 compatible = "arm,cci-400";
339                 #address-cells = <1>;
340                 #size-cells = <1>;
341                 reg = <0 0x10390000 0 0x1000>;
342                 ranges = <0 0 0x10390000 0x10000>;
343
344                 cci_control0: slave-if@1000 {
345                         compatible = "arm,cci-400-ctrl-if";
346                         interface-type = "ace-lite";
347                         reg = <0x1000 0x1000>;
348                 };
349
350                 cci_control1: slave-if@4000 {
351                         compatible = "arm,cci-400-ctrl-if";
352                         interface-type = "ace";
353                         reg = <0x4000 0x1000>;
354                 };
355
356                 cci_control2: slave-if@5000 {
357                         compatible = "arm,cci-400-ctrl-if";
358                         interface-type = "ace";
359                         reg = <0x5000 0x1000>;
360                 };
361
362                 pmu@9000 {
363                         compatible = "arm,cci-400-pmu,r1";
364                         reg = <0x9000 0x5000>;
365                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
366                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
367                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
368                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
369                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
370                 };
371         };
372
373         auxadc: adc@11001000 {
374                 compatible = "mediatek,mt7622-auxadc";
375                 reg = <0 0x11001000 0 0x1000>;
376                 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
377                 clock-names = "main";
378                 #io-channel-cells = <1>;
379         };
380
381         uart0: serial@11002000 {
382                 compatible = "mediatek,mt7622-uart",
383                              "mediatek,mt6577-uart";
384                 reg = <0 0x11002000 0 0x400>;
385                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
386                 clocks = <&topckgen CLK_TOP_UART_SEL>,
387                          <&pericfg CLK_PERI_UART0_PD>;
388                 clock-names = "baud", "bus";
389                 status = "disabled";
390         };
391
392         uart1: serial@11003000 {
393                 compatible = "mediatek,mt7622-uart",
394                              "mediatek,mt6577-uart";
395                 reg = <0 0x11003000 0 0x400>;
396                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
397                 clocks = <&topckgen CLK_TOP_UART_SEL>,
398                          <&pericfg CLK_PERI_UART1_PD>;
399                 clock-names = "baud", "bus";
400                 status = "disabled";
401         };
402
403         uart2: serial@11004000 {
404                 compatible = "mediatek,mt7622-uart",
405                              "mediatek,mt6577-uart";
406                 reg = <0 0x11004000 0 0x400>;
407                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
408                 clocks = <&topckgen CLK_TOP_UART_SEL>,
409                          <&pericfg CLK_PERI_UART2_PD>;
410                 clock-names = "baud", "bus";
411                 status = "disabled";
412         };
413
414         uart3: serial@11005000 {
415                 compatible = "mediatek,mt7622-uart",
416                              "mediatek,mt6577-uart";
417                 reg = <0 0x11005000 0 0x400>;
418                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
419                 clocks = <&topckgen CLK_TOP_UART_SEL>,
420                          <&pericfg CLK_PERI_UART3_PD>;
421                 clock-names = "baud", "bus";
422                 status = "disabled";
423         };
424
425         pwm: pwm@11006000 {
426                 compatible = "mediatek,mt7622-pwm";
427                 reg = <0 0x11006000 0 0x1000>;
428                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
429                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
430                          <&pericfg CLK_PERI_PWM_PD>,
431                          <&pericfg CLK_PERI_PWM1_PD>,
432                          <&pericfg CLK_PERI_PWM2_PD>,
433                          <&pericfg CLK_PERI_PWM3_PD>,
434                          <&pericfg CLK_PERI_PWM4_PD>,
435                          <&pericfg CLK_PERI_PWM5_PD>,
436                          <&pericfg CLK_PERI_PWM6_PD>;
437                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
438                               "pwm5", "pwm6";
439                 status = "disabled";
440         };
441
442         i2c0: i2c@11007000 {
443                 compatible = "mediatek,mt7622-i2c";
444                 reg = <0 0x11007000 0 0x90>,
445                       <0 0x11000100 0 0x80>;
446                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
447                 clock-div = <16>;
448                 clocks = <&pericfg CLK_PERI_I2C0_PD>,
449                          <&pericfg CLK_PERI_AP_DMA_PD>;
450                 clock-names = "main", "dma";
451                 #address-cells = <1>;
452                 #size-cells = <0>;
453                 status = "disabled";
454         };
455
456         i2c1: i2c@11008000 {
457                 compatible = "mediatek,mt7622-i2c";
458                 reg = <0 0x11008000 0 0x90>,
459                       <0 0x11000180 0 0x80>;
460                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
461                 clock-div = <16>;
462                 clocks = <&pericfg CLK_PERI_I2C1_PD>,
463                          <&pericfg CLK_PERI_AP_DMA_PD>;
464                 clock-names = "main", "dma";
465                 #address-cells = <1>;
466                 #size-cells = <0>;
467                 status = "disabled";
468         };
469
470         i2c2: i2c@11009000 {
471                 compatible = "mediatek,mt7622-i2c";
472                 reg = <0 0x11009000 0 0x90>,
473                       <0 0x11000200 0 0x80>;
474                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
475                 clock-div = <16>;
476                 clocks = <&pericfg CLK_PERI_I2C2_PD>,
477                          <&pericfg CLK_PERI_AP_DMA_PD>;
478                 clock-names = "main", "dma";
479                 #address-cells = <1>;
480                 #size-cells = <0>;
481                 status = "disabled";
482         };
483
484         spi0: spi@1100a000 {
485                 compatible = "mediatek,mt7622-spi";
486                 reg = <0 0x1100a000 0 0x100>;
487                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
488                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
489                          <&topckgen CLK_TOP_SPI0_SEL>,
490                          <&pericfg CLK_PERI_SPI0_PD>;
491                 clock-names = "parent-clk", "sel-clk", "spi-clk";
492                 #address-cells = <1>;
493                 #size-cells = <0>;
494                 status = "disabled";
495         };
496
497         thermal: thermal@1100b000 {
498                 #thermal-sensor-cells = <1>;
499                 compatible = "mediatek,mt7622-thermal";
500                 reg = <0 0x1100b000 0 0x1000>;
501                 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
502                 clocks = <&pericfg CLK_PERI_THERM_PD>,
503                          <&pericfg CLK_PERI_AUXADC_PD>;
504                 clock-names = "therm", "auxadc";
505                 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
506                 reset-names = "therm";
507                 mediatek,auxadc = <&auxadc>;
508                 mediatek,apmixedsys = <&apmixedsys>;
509                 nvmem-cells = <&thermal_calibration>;
510                 nvmem-cell-names = "calibration-data";
511         };
512
513         btif: serial@1100c000 {
514                 compatible = "mediatek,mt7622-btif",
515                              "mediatek,mtk-btif";
516                 reg = <0 0x1100c000 0 0x1000>;
517                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
518                 clocks = <&pericfg CLK_PERI_BTIF_PD>;
519                 clock-names = "main";
520                 reg-shift = <2>;
521                 reg-io-width = <4>;
522                 status = "disabled";
523
524                 bluetooth {
525                         compatible = "mediatek,mt7622-bluetooth";
526                         power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
527                         clocks = <&clk25m>;
528                         clock-names = "ref";
529                 };
530         };
531
532         nandc: nfi@1100d000 {
533                 compatible = "mediatek,mt7622-nfc";
534                 reg = <0 0x1100D000 0 0x1000>;
535                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
536                 clocks = <&pericfg CLK_PERI_NFI_PD>,
537                          <&pericfg CLK_PERI_SNFI_PD>;
538                 clock-names = "nfi_clk", "pad_clk";
539                 ecc-engine = <&bch>;
540                 #address-cells = <1>;
541                 #size-cells = <0>;
542                 status = "disabled";
543         };
544
545         bch: ecc@1100e000 {
546                 compatible = "mediatek,mt7622-ecc";
547                 reg = <0 0x1100e000 0 0x1000>;
548                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
549                 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
550                 clock-names = "nfiecc_clk";
551                 status = "disabled";
552         };
553
554         nor_flash: spi@11014000 {
555                 compatible = "mediatek,mt7622-nor",
556                              "mediatek,mt8173-nor";
557                 reg = <0 0x11014000 0 0xe0>;
558                 clocks = <&pericfg CLK_PERI_FLASH_PD>,
559                          <&topckgen CLK_TOP_FLASH_SEL>;
560                 clock-names = "spi", "sf";
561                 #address-cells = <1>;
562                 #size-cells = <0>;
563                 status = "disabled";
564         };
565
566         spi1: spi@11016000 {
567                 compatible = "mediatek,mt7622-spi";
568                 reg = <0 0x11016000 0 0x100>;
569                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
570                 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
571                          <&topckgen CLK_TOP_SPI1_SEL>,
572                          <&pericfg CLK_PERI_SPI1_PD>;
573                 clock-names = "parent-clk", "sel-clk", "spi-clk";
574                 #address-cells = <1>;
575                 #size-cells = <0>;
576                 status = "disabled";
577         };
578
579         uart4: serial@11019000 {
580                 compatible = "mediatek,mt7622-uart",
581                              "mediatek,mt6577-uart";
582                 reg = <0 0x11019000 0 0x400>;
583                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
584                 clocks = <&topckgen CLK_TOP_UART_SEL>,
585                          <&pericfg CLK_PERI_UART4_PD>;
586                 clock-names = "baud", "bus";
587                 status = "disabled";
588         };
589
590         audsys: clock-controller@11220000 {
591                 compatible = "mediatek,mt7622-audsys", "syscon";
592                 reg = <0 0x11220000 0 0x2000>;
593                 #clock-cells = <1>;
594
595                 afe: audio-controller {
596                         compatible = "mediatek,mt7622-audio";
597                         interrupts =  <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
598                                       <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
599                         interrupt-names = "afe", "asys";
600
601                         clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
602                                  <&topckgen CLK_TOP_AUD1_SEL>,
603                                  <&topckgen CLK_TOP_AUD2_SEL>,
604                                  <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
605                                  <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
606                                  <&topckgen CLK_TOP_I2S0_MCK_SEL>,
607                                  <&topckgen CLK_TOP_I2S1_MCK_SEL>,
608                                  <&topckgen CLK_TOP_I2S2_MCK_SEL>,
609                                  <&topckgen CLK_TOP_I2S3_MCK_SEL>,
610                                  <&topckgen CLK_TOP_I2S0_MCK_DIV>,
611                                  <&topckgen CLK_TOP_I2S1_MCK_DIV>,
612                                  <&topckgen CLK_TOP_I2S2_MCK_DIV>,
613                                  <&topckgen CLK_TOP_I2S3_MCK_DIV>,
614                                  <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
615                                  <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
616                                  <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
617                                  <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
618                                  <&audsys CLK_AUDIO_I2SO1>,
619                                  <&audsys CLK_AUDIO_I2SO2>,
620                                  <&audsys CLK_AUDIO_I2SO3>,
621                                  <&audsys CLK_AUDIO_I2SO4>,
622                                  <&audsys CLK_AUDIO_I2SIN1>,
623                                  <&audsys CLK_AUDIO_I2SIN2>,
624                                  <&audsys CLK_AUDIO_I2SIN3>,
625                                  <&audsys CLK_AUDIO_I2SIN4>,
626                                  <&audsys CLK_AUDIO_ASRCO1>,
627                                  <&audsys CLK_AUDIO_ASRCO2>,
628                                  <&audsys CLK_AUDIO_ASRCO3>,
629                                  <&audsys CLK_AUDIO_ASRCO4>,
630                                  <&audsys CLK_AUDIO_AFE>,
631                                  <&audsys CLK_AUDIO_AFE_CONN>,
632                                  <&audsys CLK_AUDIO_A1SYS>,
633                                  <&audsys CLK_AUDIO_A2SYS>;
634
635                         clock-names = "infra_sys_audio_clk",
636                                       "top_audio_mux1_sel",
637                                       "top_audio_mux2_sel",
638                                       "top_audio_a1sys_hp",
639                                       "top_audio_a2sys_hp",
640                                       "i2s0_src_sel",
641                                       "i2s1_src_sel",
642                                       "i2s2_src_sel",
643                                       "i2s3_src_sel",
644                                       "i2s0_src_div",
645                                       "i2s1_src_div",
646                                       "i2s2_src_div",
647                                       "i2s3_src_div",
648                                       "i2s0_mclk_en",
649                                       "i2s1_mclk_en",
650                                       "i2s2_mclk_en",
651                                       "i2s3_mclk_en",
652                                       "i2so0_hop_ck",
653                                       "i2so1_hop_ck",
654                                       "i2so2_hop_ck",
655                                       "i2so3_hop_ck",
656                                       "i2si0_hop_ck",
657                                       "i2si1_hop_ck",
658                                       "i2si2_hop_ck",
659                                       "i2si3_hop_ck",
660                                       "asrc0_out_ck",
661                                       "asrc1_out_ck",
662                                       "asrc2_out_ck",
663                                       "asrc3_out_ck",
664                                       "audio_afe_pd",
665                                       "audio_afe_conn_pd",
666                                       "audio_a1sys_pd",
667                                       "audio_a2sys_pd";
668
669                         assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
670                                           <&topckgen CLK_TOP_A2SYS_HP_SEL>,
671                                           <&topckgen CLK_TOP_A1SYS_HP_DIV>,
672                                           <&topckgen CLK_TOP_A2SYS_HP_DIV>;
673                         assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
674                                                  <&topckgen CLK_TOP_AUD2PLL>;
675                         assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
676                 };
677         };
678
679         mmc0: mmc@11230000 {
680                 compatible = "mediatek,mt7622-mmc";
681                 reg = <0 0x11230000 0 0x1000>;
682                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
683                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
684                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
685                 clock-names = "source", "hclk";
686                 status = "disabled";
687         };
688
689         mmc1: mmc@11240000 {
690                 compatible = "mediatek,mt7622-mmc";
691                 reg = <0 0x11240000 0 0x1000>;
692                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
693                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
694                          <&topckgen CLK_TOP_AXI_SEL>;
695                 clock-names = "source", "hclk";
696                 status = "disabled";
697         };
698
699         ssusbsys: ssusbsys@1a000000 {
700                 compatible = "mediatek,mt7622-ssusbsys",
701                              "syscon";
702                 reg = <0 0x1a000000 0 0x1000>;
703                 #clock-cells = <1>;
704                 #reset-cells = <1>;
705         };
706
707         ssusb: usb@1a0c0000 {
708                 compatible = "mediatek,mt7622-xhci",
709                              "mediatek,mtk-xhci";
710                 reg = <0 0x1a0c0000 0 0x01000>,
711                       <0 0x1a0c4700 0 0x0100>;
712                 reg-names = "mac", "ippc";
713                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
714                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
715                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
716                          <&ssusbsys CLK_SSUSB_REF_EN>,
717                          <&ssusbsys CLK_SSUSB_MCU_EN>,
718                          <&ssusbsys CLK_SSUSB_DMA_EN>;
719                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
720                 phys = <&u2port0 PHY_TYPE_USB2>,
721                        <&u3port0 PHY_TYPE_USB3>,
722                        <&u2port1 PHY_TYPE_USB2>;
723
724                 status = "disabled";
725         };
726
727         u3phy: usb-phy@1a0c4000 {
728                 compatible = "mediatek,mt7622-u3phy",
729                              "mediatek,generic-tphy-v1";
730                 reg = <0 0x1a0c4000 0 0x700>;
731                 #address-cells = <2>;
732                 #size-cells = <2>;
733                 ranges;
734                 status = "disabled";
735
736                 u2port0: usb-phy@1a0c4800 {
737                         reg = <0 0x1a0c4800 0 0x0100>;
738                         #phy-cells = <1>;
739                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
740                         clock-names = "ref";
741                 };
742
743                 u3port0: usb-phy@1a0c4900 {
744                         reg = <0 0x1a0c4900 0 0x0700>;
745                         #phy-cells = <1>;
746                         clocks = <&clk25m>;
747                         clock-names = "ref";
748                 };
749
750                 u2port1: usb-phy@1a0c5000 {
751                         reg = <0 0x1a0c5000 0 0x0100>;
752                         #phy-cells = <1>;
753                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
754                         clock-names = "ref";
755                 };
756         };
757
758         pciesys: pciesys@1a100800 {
759                 compatible = "mediatek,mt7622-pciesys",
760                              "syscon";
761                 reg = <0 0x1a100800 0 0x1000>;
762                 #clock-cells = <1>;
763                 #reset-cells = <1>;
764         };
765
766         pcie: pcie@1a140000 {
767                 compatible = "mediatek,mt7622-pcie";
768                 device_type = "pci";
769                 reg = <0 0x1a140000 0 0x1000>,
770                       <0 0x1a143000 0 0x1000>,
771                       <0 0x1a145000 0 0x1000>;
772                 reg-names = "subsys", "port0", "port1";
773                 #address-cells = <3>;
774                 #size-cells = <2>;
775                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
776                              <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
777                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
778                          <&pciesys CLK_PCIE_P1_MAC_EN>,
779                          <&pciesys CLK_PCIE_P0_AHB_EN>,
780                          <&pciesys CLK_PCIE_P0_AHB_EN>,
781                          <&pciesys CLK_PCIE_P0_AUX_EN>,
782                          <&pciesys CLK_PCIE_P1_AUX_EN>,
783                          <&pciesys CLK_PCIE_P0_AXI_EN>,
784                          <&pciesys CLK_PCIE_P1_AXI_EN>,
785                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
786                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
787                          <&pciesys CLK_PCIE_P0_PIPE_EN>,
788                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
789                 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
790                               "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
791                               "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
792                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
793                 bus-range = <0x00 0xff>;
794                 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
795                 status = "disabled";
796
797                 pcie0: pcie@0,0 {
798                         reg = <0x0000 0 0 0 0>;
799                         #address-cells = <3>;
800                         #size-cells = <2>;
801                         #interrupt-cells = <1>;
802                         ranges;
803                         status = "disabled";
804
805                         interrupt-map-mask = <0 0 0 7>;
806                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
807                                         <0 0 0 2 &pcie_intc0 1>,
808                                         <0 0 0 3 &pcie_intc0 2>,
809                                         <0 0 0 4 &pcie_intc0 3>;
810                         pcie_intc0: interrupt-controller {
811                                 interrupt-controller;
812                                 #address-cells = <0>;
813                                 #interrupt-cells = <1>;
814                         };
815                 };
816
817                 pcie1: pcie@1,0 {
818                         reg = <0x0800 0 0 0 0>;
819                         #address-cells = <3>;
820                         #size-cells = <2>;
821                         #interrupt-cells = <1>;
822                         ranges;
823                         status = "disabled";
824
825                         interrupt-map-mask = <0 0 0 7>;
826                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
827                                         <0 0 0 2 &pcie_intc1 1>,
828                                         <0 0 0 3 &pcie_intc1 2>,
829                                         <0 0 0 4 &pcie_intc1 3>;
830                         pcie_intc1: interrupt-controller {
831                                 interrupt-controller;
832                                 #address-cells = <0>;
833                                 #interrupt-cells = <1>;
834                         };
835                 };
836         };
837
838         sata: sata@1a200000 {
839                 compatible = "mediatek,mt7622-ahci",
840                              "mediatek,mtk-ahci";
841                 reg = <0 0x1a200000 0 0x1100>;
842                 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
843                 interrupt-names = "hostc";
844                 clocks = <&pciesys CLK_SATA_AHB_EN>,
845                          <&pciesys CLK_SATA_AXI_EN>,
846                          <&pciesys CLK_SATA_ASIC_EN>,
847                          <&pciesys CLK_SATA_RBC_EN>,
848                          <&pciesys CLK_SATA_PM_EN>;
849                 clock-names = "ahb", "axi", "asic", "rbc", "pm";
850                 phys = <&sata_port PHY_TYPE_SATA>;
851                 phy-names = "sata-phy";
852                 ports-implemented = <0x1>;
853                 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
854                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
855                          <&pciesys MT7622_SATA_PHY_SW_RST>,
856                          <&pciesys MT7622_SATA_PHY_REG_RST>;
857                 reset-names = "axi", "sw", "reg";
858                 mediatek,phy-mode = <&pciesys>;
859                 status = "disabled";
860         };
861
862         sata_phy: sata-phy@1a243000 {
863                 compatible = "mediatek,generic-tphy-v1";
864                 #address-cells = <2>;
865                 #size-cells = <2>;
866                 ranges;
867                 status = "disabled";
868
869                 sata_port: sata-phy@1a243000 {
870                         reg = <0 0x1a243000 0 0x0100>;
871                         clocks = <&topckgen CLK_TOP_ETH_500M>;
872                         clock-names = "ref";
873                         #phy-cells = <1>;
874                 };
875         };
876
877         ethsys: syscon@1b000000 {
878                 compatible = "mediatek,mt7622-ethsys",
879                              "syscon";
880                 reg = <0 0x1b000000 0 0x1000>;
881                 #clock-cells = <1>;
882                 #reset-cells = <1>;
883         };
884
885         hsdma: dma-controller@1b007000 {
886                 compatible = "mediatek,mt7622-hsdma";
887                 reg = <0 0x1b007000 0 0x1000>;
888                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
889                 clocks = <&ethsys CLK_ETH_HSDMA_EN>;
890                 clock-names = "hsdma";
891                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
892                 #dma-cells = <1>;
893         };
894
895         eth: ethernet@1b100000 {
896                 compatible = "mediatek,mt7622-eth",
897                              "mediatek,mt2701-eth",
898                              "syscon";
899                 reg = <0 0x1b100000 0 0x20000>;
900                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
901                              <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
902                              <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
903                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
904                          <&ethsys CLK_ETH_ESW_EN>,
905                          <&ethsys CLK_ETH_GP0_EN>,
906                          <&ethsys CLK_ETH_GP1_EN>,
907                          <&ethsys CLK_ETH_GP2_EN>,
908                          <&sgmiisys CLK_SGMII_TX250M_EN>,
909                          <&sgmiisys CLK_SGMII_RX250M_EN>,
910                          <&sgmiisys CLK_SGMII_CDR_REF>,
911                          <&sgmiisys CLK_SGMII_CDR_FB>,
912                          <&topckgen CLK_TOP_SGMIIPLL>,
913                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
914                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
915                               "sgmii_tx250m", "sgmii_rx250m",
916                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
917                               "eth2pll";
918                 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
919                 mediatek,ethsys = <&ethsys>;
920                 mediatek,sgmiisys = <&sgmiisys>;
921                 #address-cells = <1>;
922                 #size-cells = <0>;
923                 status = "disabled";
924         };
925
926         sgmiisys: sgmiisys@1b128000 {
927                 compatible = "mediatek,mt7622-sgmiisys",
928                              "syscon";
929                 reg = <0 0x1b128000 0 0x1000>;
930                 #clock-cells = <1>;
931         };
932 };