arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "MediaTek MT7622 RFB1 board";
  18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  19
  20         chosen {
  21                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  22         };
  23
  24         cpus {
  25                 cpu@0 {
  26                         proc-supply = <&mt6380_vcpu_reg>;
  27                         sram-supply = <&mt6380_vm_reg>;
  28                 };
  29
  30                 cpu@1 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34         };
  35
  36         gpio-keys {
  37                 compatible = "gpio-keys";
  38                 poll-interval = <100>;
  39
  40                 factory {
  41                         label = "factory";
  42                         linux,code = <BTN_0>;
  43                         gpios = <&pio 0 0>;
  44                 };
  45
  46                 wps {
  47                         label = "wps";
  48                         linux,code = <KEY_WPS_BUTTON>;
  49                         gpios = <&pio 102 0>;
  50                 };
  51         };
  52
  53         memory {
  54                 reg = <0 0x40000000 0 0x20000000>;
  55         };
  56
  57         reg_1p8v: regulator-1p8v {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "fixed-1.8V";
  60                 regulator-min-microvolt = <1800000>;
  61                 regulator-max-microvolt = <1800000>;
  62                 regulator-always-on;
  63         };
  64
  65         reg_3p3v: regulator-3p3v {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "fixed-3.3V";
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-max-microvolt = <3300000>;
  70                 regulator-boot-on;
  71                 regulator-always-on;
  72         };
  73
  74         reg_5v: regulator-5v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "fixed-5V";
  77                 regulator-min-microvolt = <5000000>;
  78                 regulator-max-microvolt = <5000000>;
  79                 regulator-boot-on;
  80                 regulator-always-on;
  81         };
  82 };
  83
  84 &bch {
  85         status = "disabled";
  86 };
  87
  88 &btif {
  89         status = "okay";
  90 };
  91
  92 &cir {
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&irrx_pins>;
  95         status = "okay";
  96 };
  97
  98 &eth {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&eth_pins>;
 101         status = "okay";
 102
 103         gmac1: mac@1 {
 104                 compatible = "mediatek,eth-mac";
 105                 reg = <1>;
 106                 phy-handle = <&phy5>;
 107         };
 108
 109         mdio-bus {
 110                 #address-cells = <1>;
 111                 #size-cells = <0>;
 112
 113                 phy5: ethernet-phy@5 {
 114                         reg = <5>;
 115                         phy-mode = "sgmii";
 116                 };
 117         };
 118 };
 119
 120 &i2c1 {
 121         pinctrl-names = "default";
 122         pinctrl-0 = <&i2c1_pins>;
 123         status = "okay";
 124 };
 125
 126 &i2c2 {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&i2c2_pins>;
 129         status = "okay";
 130 };
 131
 132 &mmc0 {
 133         pinctrl-names = "default", "state_uhs";
 134         pinctrl-0 = <&emmc_pins_default>;
 135         pinctrl-1 = <&emmc_pins_uhs>;
 136         status = "okay";
 137         bus-width = <8>;
 138         max-frequency = <50000000>;
 139         cap-mmc-highspeed;
 140         mmc-hs200-1_8v;
 141         vmmc-supply = <&reg_3p3v>;
 142         vqmmc-supply = <&reg_1p8v>;
 143         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 144         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 145         non-removable;
 146 };
 147
 148 &mmc1 {
 149         pinctrl-names = "default", "state_uhs";
 150         pinctrl-0 = <&sd0_pins_default>;
 151         pinctrl-1 = <&sd0_pins_uhs>;
 152         status = "okay";
 153         bus-width = <4>;
 154         max-frequency = <50000000>;
 155         cap-sd-highspeed;
 156         r_smpl = <1>;
 157         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 158         vmmc-supply = <&reg_3p3v>;
 159         vqmmc-supply = <&reg_3p3v>;
 160         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 161         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 162 };
 163
 164 &nandc {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&parallel_nand_pins>;
 167         status = "disabled";
 168 };
 169
 170 &nor_flash {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&spi_nor_pins>;
 173         status = "disabled";
 174
 175         flash@0 {
 176                 compatible = "jedec,spi-nor";
 177                 reg = <0>;
 178         };
 179 };
 180
 181 &pcie {
 182         pinctrl-names = "default";
 183         pinctrl-0 = <&pcie0_pins>;
 184         status = "okay";
 185
 186         pcie@0,0 {
 187                 status = "okay";
 188         };
 189 };
 190
 191 &pio {
 192         /* eMMC is shared pin with parallel NAND */
 193         emmc_pins_default: emmc-pins-default {
 194                 mux {
 195                         function = "emmc", "emmc_rst";
 196                         groups = "emmc";
 197                 };
 198
 199                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 200                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 201                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 202                  */
 203                 conf-cmd-dat {
 204                         pins = "NDL0", "NDL1", "NDL2",
 205                                "NDL3", "NDL4", "NDL5",
 206                                "NDL6", "NDL7", "NRB";
 207                         input-enable;
 208                         bias-pull-up;
 209                 };
 210
 211                 conf-clk {
 212                         pins = "NCLE";
 213                         bias-pull-down;
 214                 };
 215         };
 216
 217         emmc_pins_uhs: emmc-pins-uhs {
 218                 mux {
 219                         function = "emmc";
 220                         groups = "emmc";
 221                 };
 222
 223                 conf-cmd-dat {
 224                         pins = "NDL0", "NDL1", "NDL2",
 225                                "NDL3", "NDL4", "NDL5",
 226                                "NDL6", "NDL7", "NRB";
 227                         input-enable;
 228                         drive-strength = <4>;
 229                         bias-pull-up;
 230                 };
 231
 232                 conf-clk {
 233                         pins = "NCLE";
 234                         drive-strength = <4>;
 235                         bias-pull-down;
 236                 };
 237         };
 238
 239         eth_pins: eth-pins {
 240                 mux {
 241                         function = "eth";
 242                         groups = "mdc_mdio", "rgmii_via_gmac2";
 243                 };
 244         };
 245
 246         i2c1_pins: i2c1-pins {
 247                 mux {
 248                         function = "i2c";
 249                         groups =  "i2c1_0";
 250                 };
 251         };
 252
 253         i2c2_pins: i2c2-pins {
 254                 mux {
 255                         function = "i2c";
 256                         groups =  "i2c2_0";
 257                 };
 258         };
 259
 260         i2s1_pins: i2s1-pins {
 261                 mux {
 262                         function = "i2s";
 263                         groups =  "i2s_out_mclk_bclk_ws",
 264                                   "i2s1_in_data",
 265                                   "i2s1_out_data";
 266                 };
 267
 268                 conf {
 269                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 270                                "I2S_WS", "I2S_MCLK";
 271                         drive-strength = <12>;
 272                         bias-pull-down;
 273                 };
 274         };
 275
 276         irrx_pins: irrx-pins {
 277                 mux {
 278                         function = "ir";
 279                         groups =  "ir_1_rx";
 280                 };
 281         };
 282
 283         irtx_pins: irtx-pins {
 284                 mux {
 285                         function = "ir";
 286                         groups =  "ir_1_tx";
 287                 };
 288         };
 289
 290         /* Parallel nand is shared pin with eMMC */
 291         parallel_nand_pins: parallel-nand-pins {
 292                 mux {
 293                         function = "flash";
 294                         groups = "par_nand";
 295                 };
 296         };
 297
 298         pcie0_pins: pcie0-pins {
 299                 mux {
 300                         function = "pcie";
 301                         groups = "pcie0_pad_perst",
 302                                  "pcie0_1_waken",
 303                                  "pcie0_1_clkreq";
 304                 };
 305         };
 306
 307         pcie1_pins: pcie1-pins {
 308                 mux {
 309                         function = "pcie";
 310                         groups = "pcie1_pad_perst",
 311                                  "pcie1_0_waken",
 312                                  "pcie1_0_clkreq";
 313                 };
 314         };
 315
 316         pmic_bus_pins: pmic-bus-pins {
 317                 mux {
 318                         function = "pmic";
 319                         groups = "pmic_bus";
 320                 };
 321         };
 322
 323         pwm7_pins: pwm1-2-pins {
 324                 mux {
 325                         function = "pwm";
 326                         groups = "pwm_ch7_2";
 327                 };
 328         };
 329
 330         wled_pins: wled-pins {
 331                 mux {
 332                         function = "led";
 333                         groups = "wled";
 334                 };
 335         };
 336
 337         sd0_pins_default: sd0-pins-default {
 338                 mux {
 339                         function = "sd";
 340                         groups = "sd_0";
 341                 };
 342
 343                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 344                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 345                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 346                  */
 347                 conf-cmd-data {
 348                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 349                                "I2S2_IN","I2S4_OUT";
 350                         input-enable;
 351                         drive-strength = <8>;
 352                         bias-pull-up;
 353                 };
 354                 conf-clk {
 355                         pins = "I2S3_OUT";
 356                         drive-strength = <12>;
 357                         bias-pull-down;
 358                 };
 359                 conf-cd {
 360                         pins = "TXD3";
 361                         bias-pull-up;
 362                 };
 363         };
 364
 365         sd0_pins_uhs: sd0-pins-uhs {
 366                 mux {
 367                         function = "sd";
 368                         groups = "sd_0";
 369                 };
 370
 371                 conf-cmd-data {
 372                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 373                                "I2S2_IN","I2S4_OUT";
 374                         input-enable;
 375                         bias-pull-up;
 376                 };
 377
 378                 conf-clk {
 379                         pins = "I2S3_OUT";
 380                         bias-pull-down;
 381                 };
 382         };
 383
 384         /* Serial NAND is shared pin with SPI-NOR */
 385         serial_nand_pins: serial-nand-pins {
 386                 mux {
 387                         function = "flash";
 388                         groups = "snfi";
 389                 };
 390         };
 391
 392         spic0_pins: spic0-pins {
 393                 mux {
 394                         function = "spi";
 395                         groups = "spic0_0";
 396                 };
 397         };
 398
 399         spic1_pins: spic1-pins {
 400                 mux {
 401                         function = "spi";
 402                         groups = "spic1_0";
 403                 };
 404         };
 405
 406         /* SPI-NOR is shared pin with serial NAND */
 407         spi_nor_pins: spi-nor-pins {
 408                 mux {
 409                         function = "flash";
 410                         groups = "spi_nor";
 411                 };
 412         };
 413
 414         /* serial NAND is shared pin with SPI-NOR */
 415         serial_nand_pins: serial-nand-pins {
 416                 mux {
 417                         function = "flash";
 418                         groups = "snfi";
 419                 };
 420         };
 421
 422         uart0_pins: uart0-pins {
 423                 mux {
 424                         function = "uart";
 425                         groups = "uart0_0_tx_rx" ;
 426                 };
 427         };
 428
 429         uart2_pins: uart2-pins {
 430                 mux {
 431                         function = "uart";
 432                         groups = "uart2_1_tx_rx" ;
 433                 };
 434         };
 435
 436         watchdog_pins: watchdog-pins {
 437                 mux {
 438                         function = "watchdog";
 439                         groups = "watchdog";
 440                 };
 441         };
 442 };
 443
 444 &pwm {
 445         pinctrl-names = "default";
 446         pinctrl-0 = <&pwm7_pins>;
 447         status = "okay";
 448 };
 449
 450 &pwrap {
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pmic_bus_pins>;
 453
 454         status = "okay";
 455 };
 456
 457 &sata {
 458         status = "okay";
 459 };
 460
 461 &sata_phy {
 462         status = "okay";
 463 };
 464
 465 &spi0 {
 466         pinctrl-names = "default";
 467         pinctrl-0 = <&spic0_pins>;
 468         status = "okay";
 469 };
 470
 471 &spi1 {
 472         pinctrl-names = "default";
 473         pinctrl-0 = <&spic1_pins>;
 474         status = "okay";
 475 };
 476
 477 &ssusb {
 478         vusb33-supply = <&reg_3p3v>;
 479         vbus-supply = <&reg_5v>;
 480         status = "okay";
 481 };
 482
 483 &u3phy {
 484         status = "okay";
 485 };
 486
 487 &uart0 {
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&uart0_pins>;
 490         status = "okay";
 491 };
 492
 493 &uart2 {
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&uart2_pins>;
 496         status = "okay";
 497 };
 498
 499 &watchdog {
 500         pinctrl-names = "default";
 501         pinctrl-0 = <&watchdog_pins>;
 502         status = "okay";
 503 };