2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
13 #include "mt7622.dtsi"
14 #include "mt6380.dtsi"
17 model = "MediaTek MT7622 RFB1 board";
18 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
21 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
26 proc-supply = <&mt6380_vcpu_reg>;
27 sram-supply = <&mt6380_vm_reg>;
31 proc-supply = <&mt6380_vcpu_reg>;
32 sram-supply = <&mt6380_vm_reg>;
37 compatible = "gpio-keys";
38 poll-interval = <100>;
48 linux,code = <KEY_WPS_BUTTON>;
54 reg = <0 0x40000000 0 0x20000000>;
57 reg_1p8v: regulator-1p8v {
58 compatible = "regulator-fixed";
59 regulator-name = "fixed-1.8V";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <1800000>;
65 reg_3p3v: regulator-3p3v {
66 compatible = "regulator-fixed";
67 regulator-name = "fixed-3.3V";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
74 reg_5v: regulator-5v {
75 compatible = "regulator-fixed";
76 regulator-name = "fixed-5V";
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&irrx_pins>;
99 pinctrl-names = "default";
100 pinctrl-0 = <ð_pins>;
104 compatible = "mediatek,eth-mac";
106 phy-handle = <&phy5>;
110 #address-cells = <1>;
113 phy5: ethernet-phy@5 {
121 pinctrl-names = "default";
122 pinctrl-0 = <&i2c1_pins>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&i2c2_pins>;
133 pinctrl-names = "default", "state_uhs";
134 pinctrl-0 = <&emmc_pins_default>;
135 pinctrl-1 = <&emmc_pins_uhs>;
138 max-frequency = <50000000>;
141 vmmc-supply = <®_3p3v>;
142 vqmmc-supply = <®_1p8v>;
143 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
144 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
149 pinctrl-names = "default", "state_uhs";
150 pinctrl-0 = <&sd0_pins_default>;
151 pinctrl-1 = <&sd0_pins_uhs>;
154 max-frequency = <50000000>;
157 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
158 vmmc-supply = <®_3p3v>;
159 vqmmc-supply = <®_3p3v>;
160 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
161 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
165 pinctrl-names = "default";
166 pinctrl-0 = <¶llel_nand_pins>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&spi_nor_pins>;
176 compatible = "jedec,spi-nor";
182 pinctrl-names = "default";
183 pinctrl-0 = <&pcie0_pins>;
192 /* eMMC is shared pin with parallel NAND */
193 emmc_pins_default: emmc-pins-default {
195 function = "emmc", "emmc_rst";
199 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
200 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
201 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
204 pins = "NDL0", "NDL1", "NDL2",
205 "NDL3", "NDL4", "NDL5",
206 "NDL6", "NDL7", "NRB";
217 emmc_pins_uhs: emmc-pins-uhs {
224 pins = "NDL0", "NDL1", "NDL2",
225 "NDL3", "NDL4", "NDL5",
226 "NDL6", "NDL7", "NRB";
228 drive-strength = <4>;
234 drive-strength = <4>;
242 groups = "mdc_mdio", "rgmii_via_gmac2";
246 i2c1_pins: i2c1-pins {
253 i2c2_pins: i2c2-pins {
260 i2s1_pins: i2s1-pins {
263 groups = "i2s_out_mclk_bclk_ws",
269 pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
270 "I2S_WS", "I2S_MCLK";
271 drive-strength = <12>;
276 irrx_pins: irrx-pins {
283 irtx_pins: irtx-pins {
290 /* Parallel nand is shared pin with eMMC */
291 parallel_nand_pins: parallel-nand-pins {
298 pcie0_pins: pcie0-pins {
301 groups = "pcie0_pad_perst",
307 pcie1_pins: pcie1-pins {
310 groups = "pcie1_pad_perst",
316 pmic_bus_pins: pmic-bus-pins {
323 pwm7_pins: pwm1-2-pins {
326 groups = "pwm_ch7_2";
330 wled_pins: wled-pins {
337 sd0_pins_default: sd0-pins-default {
343 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
344 * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
345 * DAT2, DAT3, CMD, CLK for SD respectively.
348 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
349 "I2S2_IN","I2S4_OUT";
351 drive-strength = <8>;
356 drive-strength = <12>;
365 sd0_pins_uhs: sd0-pins-uhs {
372 pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
373 "I2S2_IN","I2S4_OUT";
384 /* Serial NAND is shared pin with SPI-NOR */
385 serial_nand_pins: serial-nand-pins {
392 spic0_pins: spic0-pins {
399 spic1_pins: spic1-pins {
406 /* SPI-NOR is shared pin with serial NAND */
407 spi_nor_pins: spi-nor-pins {
414 /* serial NAND is shared pin with SPI-NOR */
415 serial_nand_pins: serial-nand-pins {
422 uart0_pins: uart0-pins {
425 groups = "uart0_0_tx_rx" ;
429 uart2_pins: uart2-pins {
432 groups = "uart2_1_tx_rx" ;
436 watchdog_pins: watchdog-pins {
438 function = "watchdog";
445 pinctrl-names = "default";
446 pinctrl-0 = <&pwm7_pins>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&pmic_bus_pins>;
466 pinctrl-names = "default";
467 pinctrl-0 = <&spic0_pins>;
472 pinctrl-names = "default";
473 pinctrl-0 = <&spic1_pins>;
478 vusb33-supply = <®_3p3v>;
479 vbus-supply = <®_5v>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&uart0_pins>;
494 pinctrl-names = "default";
495 pinctrl-0 = <&uart2_pins>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&watchdog_pins>;