arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Ming Huang <ming.huang@mediatek.com>
   4  *         Sean Wang <sean.wang@mediatek.com>
   5  *
   6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   7  */
   8
   9 /dts-v1/;
  10 #include <dt-bindings/input/input.h>
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 #include "mt7622.dtsi"
  14 #include "mt6380.dtsi"
  15
  16 / {
  17         model = "MediaTek MT7622 RFB1 board";
  18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
  19
  20         chosen {
  21                 bootargs = "console=ttyS0,115200n1 swiotlb=512";
  22         };
  23
  24         cpus {
  25                 cpu@0 {
  26                         proc-supply = <&mt6380_vcpu_reg>;
  27                         sram-supply = <&mt6380_vm_reg>;
  28                 };
  29
  30                 cpu@1 {
  31                         proc-supply = <&mt6380_vcpu_reg>;
  32                         sram-supply = <&mt6380_vm_reg>;
  33                 };
  34         };
  35
  36         gpio-keys {
  37                 compatible = "gpio-keys-polled";
  38                 poll-interval = <100>;
  39
  40                 factory {
  41                         label = "factory";
  42                         linux,code = <BTN_0>;
  43                         gpios = <&pio 0 0>;
  44                 };
  45
  46                 wps {
  47                         label = "wps";
  48                         linux,code = <KEY_WPS_BUTTON>;
  49                         gpios = <&pio 102 0>;
  50                 };
  51         };
  52
  53         memory {
  54                 reg = <0 0x40000000 0 0x3F000000>;
  55         };
  56
  57         reg_1p8v: regulator-1p8v {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "fixed-1.8V";
  60                 regulator-min-microvolt = <1800000>;
  61                 regulator-max-microvolt = <1800000>;
  62                 regulator-always-on;
  63         };
  64
  65         reg_3p3v: regulator-3p3v {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "fixed-3.3V";
  68                 regulator-min-microvolt = <3300000>;
  69                 regulator-max-microvolt = <3300000>;
  70                 regulator-boot-on;
  71                 regulator-always-on;
  72         };
  73
  74         reg_5v: regulator-5v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "fixed-5V";
  77                 regulator-min-microvolt = <5000000>;
  78                 regulator-max-microvolt = <5000000>;
  79                 regulator-boot-on;
  80                 regulator-always-on;
  81         };
  82 };
  83
  84 &pcie {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pcie0_pins>;
  87         status = "okay";
  88
  89         pcie@0,0 {
  90                 status = "okay";
  91         };
  92 };
  93
  94 &pio {
  95         /* eMMC is shared pin with parallel NAND */
  96         emmc_pins_default: emmc-pins-default {
  97                 mux {
  98                         function = "emmc", "emmc_rst";
  99                         groups = "emmc";
 100                 };
 101
 102                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 103                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 104                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 105                  */
 106                 conf-cmd-dat {
 107                         pins = "NDL0", "NDL1", "NDL2",
 108                                "NDL3", "NDL4", "NDL5",
 109                                "NDL6", "NDL7", "NRB";
 110                         input-enable;
 111                         bias-pull-up;
 112                 };
 113
 114                 conf-clk {
 115                         pins = "NCLE";
 116                         bias-pull-down;
 117                 };
 118         };
 119
 120         emmc_pins_uhs: emmc-pins-uhs {
 121                 mux {
 122                         function = "emmc";
 123                         groups = "emmc";
 124                 };
 125
 126                 conf-cmd-dat {
 127                         pins = "NDL0", "NDL1", "NDL2",
 128                                "NDL3", "NDL4", "NDL5",
 129                                "NDL6", "NDL7", "NRB";
 130                         input-enable;
 131                         drive-strength = <4>;
 132                         bias-pull-up;
 133                 };
 134
 135                 conf-clk {
 136                         pins = "NCLE";
 137                         drive-strength = <4>;
 138                         bias-pull-down;
 139                 };
 140         };
 141
 142         eth_pins: eth-pins {
 143                 mux {
 144                         function = "eth";
 145                         groups = "mdc_mdio", "rgmii_via_gmac2";
 146                 };
 147         };
 148
 149         i2c1_pins: i2c1-pins {
 150                 mux {
 151                         function = "i2c";
 152                         groups =  "i2c1_0";
 153                 };
 154         };
 155
 156         i2c2_pins: i2c2-pins {
 157                 mux {
 158                         function = "i2c";
 159                         groups =  "i2c2_0";
 160                 };
 161         };
 162
 163         i2s1_pins: i2s1-pins {
 164                 mux {
 165                         function = "i2s";
 166                         groups =  "i2s_out_mclk_bclk_ws",
 167                                   "i2s1_in_data",
 168                                   "i2s1_out_data";
 169                 };
 170
 171                 conf {
 172                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 173                                "I2S_WS", "I2S_MCLK";
 174                         drive-strength = <12>;
 175                         bias-pull-down;
 176                 };
 177         };
 178
 179         irrx_pins: irrx-pins {
 180                 mux {
 181                         function = "ir";
 182                         groups =  "ir_1_rx";
 183                 };
 184         };
 185
 186         irtx_pins: irtx-pins {
 187                 mux {
 188                         function = "ir";
 189                         groups =  "ir_1_tx";
 190                 };
 191         };
 192
 193         /* Parallel nand is shared pin with eMMC */
 194         parallel_nand_pins: parallel-nand-pins {
 195                 mux {
 196                         function = "flash";
 197                         groups = "par_nand";
 198                 };
 199         };
 200
 201         pcie0_pins: pcie0-pins {
 202                 mux {
 203                         function = "pcie";
 204                         groups = "pcie0_pad_perst",
 205                                  "pcie0_1_waken",
 206                                  "pcie0_1_clkreq";
 207                 };
 208         };
 209
 210         pcie1_pins: pcie1-pins {
 211                 mux {
 212                         function = "pcie";
 213                         groups = "pcie1_pad_perst",
 214                                  "pcie1_0_waken",
 215                                  "pcie1_0_clkreq";
 216                 };
 217         };
 218
 219         pmic_bus_pins: pmic-bus-pins {
 220                 mux {
 221                         function = "pmic";
 222                         groups = "pmic_bus";
 223                 };
 224         };
 225
 226         pwm7_pins: pwm1-2-pins {
 227                 mux {
 228                         function = "pwm";
 229                         groups = "pwm_ch7_2";
 230                 };
 231         };
 232
 233         wled_pins: wled-pins {
 234                 mux {
 235                         function = "led";
 236                         groups = "wled";
 237                 };
 238         };
 239
 240         sd0_pins_default: sd0-pins-default {
 241                 mux {
 242                         function = "sd";
 243                         groups = "sd_0";
 244                 };
 245
 246                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 247                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 248                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 249                  */
 250                 conf-cmd-data {
 251                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 252                                "I2S2_IN","I2S4_OUT";
 253                         input-enable;
 254                         drive-strength = <8>;
 255                         bias-pull-up;
 256                 };
 257                 conf-clk {
 258                         pins = "I2S3_OUT";
 259                         drive-strength = <12>;
 260                         bias-pull-down;
 261                 };
 262                 conf-cd {
 263                         pins = "TXD3";
 264                         bias-pull-up;
 265                 };
 266         };
 267
 268         sd0_pins_uhs: sd0-pins-uhs {
 269                 mux {
 270                         function = "sd";
 271                         groups = "sd_0";
 272                 };
 273
 274                 conf-cmd-data {
 275                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 276                                "I2S2_IN","I2S4_OUT";
 277                         input-enable;
 278                         bias-pull-up;
 279                 };
 280
 281                 conf-clk {
 282                         pins = "I2S3_OUT";
 283                         bias-pull-down;
 284                 };
 285         };
 286
 287         /* Serial NAND is shared pin with SPI-NOR */
 288         serial_nand_pins: serial-nand-pins {
 289                 mux {
 290                         function = "flash";
 291                         groups = "snfi";
 292                 };
 293         };
 294
 295         spic0_pins: spic0-pins {
 296                 mux {
 297                         function = "spi";
 298                         groups = "spic0_0";
 299                 };
 300         };
 301
 302         spic1_pins: spic1-pins {
 303                 mux {
 304                         function = "spi";
 305                         groups = "spic1_0";
 306                 };
 307         };
 308
 309         /* SPI-NOR is shared pin with serial NAND */
 310         spi_nor_pins: spi-nor-pins {
 311                 mux {
 312                         function = "flash";
 313                         groups = "spi_nor";
 314                 };
 315         };
 316
 317         /* serial NAND is shared pin with SPI-NOR */
 318         serial_nand_pins: serial-nand-pins {
 319                 mux {
 320                         function = "flash";
 321                         groups = "snfi";
 322                 };
 323         };
 324
 325         uart0_pins: uart0-pins {
 326                 mux {
 327                         function = "uart";
 328                         groups = "uart0_0_tx_rx" ;
 329                 };
 330         };
 331
 332         uart2_pins: uart2-pins {
 333                 mux {
 334                         function = "uart";
 335                         groups = "uart2_1_tx_rx" ;
 336                 };
 337         };
 338
 339         watchdog_pins: watchdog-pins {
 340                 mux {
 341                         function = "watchdog";
 342                         groups = "watchdog";
 343                 };
 344         };
 345 };
 346
 347 &bch {
 348         status = "disabled";
 349 };
 350
 351 &btif {
 352         status = "okay";
 353 };
 354
 355 &cir {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&irrx_pins>;
 358         status = "okay";
 359 };
 360
 361 &eth {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&eth_pins>;
 364         status = "okay";
 365
 366         gmac1: mac@1 {
 367                 compatible = "mediatek,eth-mac";
 368                 reg = <1>;
 369                 phy-handle = <&phy5>;
 370         };
 371
 372         mdio-bus {
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375
 376                 phy5: ethernet-phy@5 {
 377                         reg = <5>;
 378                         phy-mode = "sgmii";
 379                 };
 380         };
 381 };
 382
 383 &i2c1 {
 384         pinctrl-names = "default";
 385         pinctrl-0 = <&i2c1_pins>;
 386         status = "okay";
 387 };
 388
 389 &i2c2 {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&i2c2_pins>;
 392         status = "okay";
 393 };
 394
 395 &mmc0 {
 396         pinctrl-names = "default", "state_uhs";
 397         pinctrl-0 = <&emmc_pins_default>;
 398         pinctrl-1 = <&emmc_pins_uhs>;
 399         status = "okay";
 400         bus-width = <8>;
 401         max-frequency = <50000000>;
 402         cap-mmc-highspeed;
 403         mmc-hs200-1_8v;
 404         vmmc-supply = <&reg_3p3v>;
 405         vqmmc-supply = <&reg_1p8v>;
 406         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 407         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 408         non-removable;
 409 };
 410
 411 &mmc1 {
 412         pinctrl-names = "default", "state_uhs";
 413         pinctrl-0 = <&sd0_pins_default>;
 414         pinctrl-1 = <&sd0_pins_uhs>;
 415         status = "okay";
 416         bus-width = <4>;
 417         max-frequency = <50000000>;
 418         cap-sd-highspeed;
 419         r_smpl = <1>;
 420         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 421         vmmc-supply = <&reg_3p3v>;
 422         vqmmc-supply = <&reg_3p3v>;
 423         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 424         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 425 };
 426
 427 &nandc {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&parallel_nand_pins>;
 430         status = "disabled";
 431 };
 432
 433 &nor_flash {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&spi_nor_pins>;
 436         status = "disabled";
 437
 438         flash@0 {
 439                 compatible = "jedec,spi-nor";
 440                 reg = <0>;
 441         };
 442 };
 443
 444 &pwm {
 445         pinctrl-names = "default";
 446         pinctrl-0 = <&pwm7_pins>;
 447         status = "okay";
 448 };
 449
 450 &pwrap {
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pmic_bus_pins>;
 453
 454         status = "okay";
 455 };
 456
 457 &sata {
 458         status = "okay";
 459 };
 460
 461 &sata_phy {
 462         status = "okay";
 463 };
 464
 465 &spi0 {
 466         pinctrl-names = "default";
 467         pinctrl-0 = <&spic0_pins>;
 468         status = "okay";
 469 };
 470
 471 &spi1 {
 472         pinctrl-names = "default";
 473         pinctrl-0 = <&spic1_pins>;
 474         status = "okay";
 475 };
 476
 477 &ssusb {
 478         vusb33-supply = <&reg_3p3v>;
 479         vbus-supply = <&reg_5v>;
 480         status = "okay";
 481 };
 482
 483 &u3phy {
 484         status = "okay";
 485 };
 486
 487 &uart0 {
 488         pinctrl-names = "default";
 489         pinctrl-0 = <&uart0_pins>;
 490         status = "okay";
 491 };
 492
 493 &uart2 {
 494         pinctrl-names = "default";
 495         pinctrl-0 = <&uart2_pins>;
 496         status = "okay";
 497 };
 498
 499 &watchdog {
 500         pinctrl-names = "default";
 501         pinctrl-0 = <&watchdog_pins>;
 502         status = "okay";
 503 };