arch/arm64/boot/dts/marvell/armada-cp110.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada CP110.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
   9
  10 #include "armada-common.dtsi"
  11
  12 #define CP110_PCIEx_IO_BASE(iface)      (CP110_PCIE_IO_BASE + (iface *  0x10000))
  13 #define CP110_PCIEx_MEM_BASE(iface)     (CP110_PCIE_MEM_BASE + (iface *  0x1000000))
  14 #define CP110_PCIEx_CONF_BASE(iface)    (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
  15
  16 / {
  17         /*
  18          * The contents of the node are defined below, in order to
  19          * save one indentation level
  20          */
  21         CP110_NAME: CP110_NAME { };
  22 };
  23
  24 &CP110_NAME {
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27         compatible = "simple-bus";
  28         interrupt-parent = <&CP110_LABEL(icu)>;
  29         ranges;
  30
  31         config-space@CP110_BASE {
  32                 #address-cells = <1>;
  33                 #size-cells = <1>;
  34                 compatible = "simple-bus";
  35                 ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
  36
  37                 CP110_LABEL(ethernet): ethernet@0 {
  38                         compatible = "marvell,armada-7k-pp22";
  39                         reg = <0x0 0x100000>, <0x129000 0xb000>;
  40                         clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
  41                                  <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
  42                                  <&CP110_LABEL(clk) 1 18>;
  43                         clock-names = "pp_clk", "gop_clk",
  44                                       "mg_clk", "mg_core_clk", "axi_clk";
  45                         marvell,system-controller = <&CP110_LABEL(syscon0)>;
  46                         status = "disabled";
  47                         dma-coherent;
  48
  49                         CP110_LABEL(eth0): eth0 {
  50                                 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
  51                                         <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
  52                                         <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
  53                                         <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
  54                                         <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
  55                                         <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
  56                                 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  57                                         "tx-cpu3", "rx-shared", "link";
  58                                 port-id = <0>;
  59                                 gop-port-id = <0>;
  60                                 status = "disabled";
  61                         };
  62
  63                         CP110_LABEL(eth1): eth1 {
  64                                 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
  65                                         <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
  66                                         <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
  67                                         <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
  68                                         <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
  69                                         <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
  70                                 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  71                                         "tx-cpu3", "rx-shared", "link";
  72                                 port-id = <1>;
  73                                 gop-port-id = <2>;
  74                                 status = "disabled";
  75                         };
  76
  77                         CP110_LABEL(eth2): eth2 {
  78                                 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
  79                                         <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
  80                                         <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
  81                                         <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
  82                                         <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
  83                                         <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
  84                                 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  85                                         "tx-cpu3", "rx-shared", "link";
  86                                 port-id = <2>;
  87                                 gop-port-id = <3>;
  88                                 status = "disabled";
  89                         };
  90                 };
  91
  92                 CP110_LABEL(comphy): phy@120000 {
  93                         compatible = "marvell,comphy-cp110";
  94                         reg = <0x120000 0x6000>;
  95                         marvell,system-controller = <&CP110_LABEL(syscon0)>;
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98
  99                         CP110_LABEL(comphy0): phy@0 {
 100                                 reg = <0>;
 101                                 #phy-cells = <1>;
 102                         };
 103
 104                         CP110_LABEL(comphy1): phy@1 {
 105                                 reg = <1>;
 106                                 #phy-cells = <1>;
 107                         };
 108
 109                         CP110_LABEL(comphy2): phy@2 {
 110                                 reg = <2>;
 111                                 #phy-cells = <1>;
 112                         };
 113
 114                         CP110_LABEL(comphy3): phy@3 {
 115                                 reg = <3>;
 116                                 #phy-cells = <1>;
 117                         };
 118
 119                         CP110_LABEL(comphy4): phy@4 {
 120                                 reg = <4>;
 121                                 #phy-cells = <1>;
 122                         };
 123
 124                         CP110_LABEL(comphy5): phy@5 {
 125                                 reg = <5>;
 126                                 #phy-cells = <1>;
 127                         };
 128                 };
 129
 130                 CP110_LABEL(mdio): mdio@12a200 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         compatible = "marvell,orion-mdio";
 134                         reg = <0x12a200 0x10>;
 135                         clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
 136                                  <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
 137                         status = "disabled";
 138                 };
 139
 140                 CP110_LABEL(xmdio): mdio@12a600 {
 141                         #address-cells = <1>;
 142                         #size-cells = <0>;
 143                         compatible = "marvell,xmdio";
 144                         reg = <0x12a600 0x10>;
 145                         clocks = <&CP110_LABEL(clk) 1 5>,
 146                                  <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
 147                         status = "disabled";
 148                 };
 149
 150                 CP110_LABEL(icu): interrupt-controller@1e0000 {
 151                         compatible = "marvell,cp110-icu";
 152                         reg = <0x1e0000 0x10>;
 153                         #interrupt-cells = <3>;
 154                         interrupt-controller;
 155                         msi-parent = <&gicp>;
 156                 };
 157
 158                 CP110_LABEL(rtc): rtc@284000 {
 159                         compatible = "marvell,armada-8k-rtc";
 160                         reg = <0x284000 0x20>, <0x284080 0x24>;
 161                         reg-names = "rtc", "rtc-soc";
 162                         interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
 163                 };
 164
 165                 CP110_LABEL(thermal): thermal@400078 {
 166                         compatible = "marvell,armada-cp110-thermal";
 167                         reg = <0x400078 0x4>,
 168                         <0x400070 0x8>;
 169                 };
 170
 171                 CP110_LABEL(syscon0): system-controller@440000 {
 172                         compatible = "syscon", "simple-mfd";
 173                         reg = <0x440000 0x2000>;
 174
 175                         CP110_LABEL(clk): clock {
 176                                 compatible = "marvell,cp110-clock";
 177                                 #clock-cells = <2>;
 178                         };
 179
 180                         CP110_LABEL(gpio1): gpio@100 {
 181                                 compatible = "marvell,armada-8k-gpio";
 182                                 offset = <0x100>;
 183                                 ngpios = <32>;
 184                                 gpio-controller;
 185                                 #gpio-cells = <2>;
 186                                 gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
 187                                 interrupt-controller;
 188                                 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
 189                                         <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
 190                                         <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
 191                                         <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
 192                                 status = "disabled";
 193                         };
 194
 195                         CP110_LABEL(gpio2): gpio@140 {
 196                                 compatible = "marvell,armada-8k-gpio";
 197                                 offset = <0x140>;
 198                                 ngpios = <31>;
 199                                 gpio-controller;
 200                                 #gpio-cells = <2>;
 201                                 gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
 202                                 interrupt-controller;
 203                                 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
 204                                         <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
 205                                         <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
 206                                         <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
 207                                 status = "disabled";
 208                         };
 209                 };
 210
 211                 CP110_LABEL(usb3_0): usb3@500000 {
 212                         compatible = "marvell,armada-8k-xhci",
 213                         "generic-xhci";
 214                         reg = <0x500000 0x4000>;
 215                         dma-coherent;
 216                         interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
 217                         clock-names = "core", "reg";
 218                         clocks = <&CP110_LABEL(clk) 1 22>,
 219                                  <&CP110_LABEL(clk) 1 16>;
 220                         status = "disabled";
 221                 };
 222
 223                 CP110_LABEL(usb3_1): usb3@510000 {
 224                         compatible = "marvell,armada-8k-xhci",
 225                         "generic-xhci";
 226                         reg = <0x510000 0x4000>;
 227                         dma-coherent;
 228                         interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
 229                         clock-names = "core", "reg";
 230                         clocks = <&CP110_LABEL(clk) 1 23>,
 231                                  <&CP110_LABEL(clk) 1 16>;
 232                         status = "disabled";
 233                 };
 234
 235                 CP110_LABEL(sata0): sata@540000 {
 236                         compatible = "marvell,armada-8k-ahci",
 237                         "generic-ahci";
 238                         reg = <0x540000 0x30000>;
 239                         dma-coherent;
 240                         interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
 241                         clocks = <&CP110_LABEL(clk) 1 15>,
 242                                  <&CP110_LABEL(clk) 1 16>;
 243                         status = "disabled";
 244                 };
 245
 246                 CP110_LABEL(xor0): xor@6a0000 {
 247                         compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 248                         reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
 249                         dma-coherent;
 250                         msi-parent = <&gic_v2m0>;
 251                         clock-names = "core", "reg";
 252                         clocks = <&CP110_LABEL(clk) 1 8>,
 253                                  <&CP110_LABEL(clk) 1 14>;
 254                 };
 255
 256                 CP110_LABEL(xor1): xor@6c0000 {
 257                         compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 258                         reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
 259                         dma-coherent;
 260                         msi-parent = <&gic_v2m0>;
 261                         clock-names = "core", "reg";
 262                         clocks = <&CP110_LABEL(clk) 1 7>,
 263                                  <&CP110_LABEL(clk) 1 14>;
 264                 };
 265
 266                 CP110_LABEL(spi0): spi@700600 {
 267                         compatible = "marvell,armada-380-spi";
 268                         reg = <0x700600 0x50>;
 269                         #address-cells = <0x1>;
 270                         #size-cells = <0x0>;
 271                         clock-names = "core", "axi";
 272                         clocks = <&CP110_LABEL(clk) 1 21>,
 273                                  <&CP110_LABEL(clk) 1 17>;
 274                         status = "disabled";
 275                 };
 276
 277                 CP110_LABEL(spi1): spi@700680 {
 278                         compatible = "marvell,armada-380-spi";
 279                         reg = <0x700680 0x50>;
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                         clock-names = "core", "axi";
 283                         clocks = <&CP110_LABEL(clk) 1 21>,
 284                                  <&CP110_LABEL(clk) 1 17>;
 285                         status = "disabled";
 286                 };
 287
 288                 CP110_LABEL(i2c0): i2c@701000 {
 289                         compatible = "marvell,mv78230-i2c";
 290                         reg = <0x701000 0x20>;
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
 294                         clock-names = "core", "reg";
 295                         clocks = <&CP110_LABEL(clk) 1 21>,
 296                                  <&CP110_LABEL(clk) 1 17>;
 297                         status = "disabled";
 298                 };
 299
 300                 CP110_LABEL(i2c1): i2c@701100 {
 301                         compatible = "marvell,mv78230-i2c";
 302                         reg = <0x701100 0x20>;
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
 306                         clock-names = "core", "reg";
 307                         clocks = <&CP110_LABEL(clk) 1 21>,
 308                                  <&CP110_LABEL(clk) 1 17>;
 309                         status = "disabled";
 310                 };
 311
 312                 CP110_LABEL(uart0): serial@702000 {
 313                         compatible = "snps,dw-apb-uart";
 314                         reg = <0x702000 0x100>;
 315                         reg-shift = <2>;
 316                         interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
 317                         reg-io-width = <1>;
 318                         clock-names = "baudclk", "apb_pclk";
 319                         clocks = <&CP110_LABEL(clk) 1 21>,
 320                                  <&CP110_LABEL(clk) 1 17>;
 321                         status = "disabled";
 322                 };
 323
 324                 CP110_LABEL(uart1): serial@702100 {
 325                         compatible = "snps,dw-apb-uart";
 326                         reg = <0x702100 0x100>;
 327                         reg-shift = <2>;
 328                         interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
 329                         reg-io-width = <1>;
 330                         clock-names = "baudclk", "apb_pclk";
 331                         clocks = <&CP110_LABEL(clk) 1 21>,
 332                                  <&CP110_LABEL(clk) 1 17>;
 333                         status = "disabled";
 334                 };
 335
 336                 CP110_LABEL(uart2): serial@702200 {
 337                         compatible = "snps,dw-apb-uart";
 338                         reg = <0x702200 0x100>;
 339                         reg-shift = <2>;
 340                         interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
 341                         reg-io-width = <1>;
 342                         clock-names = "baudclk", "apb_pclk";
 343                         clocks = <&CP110_LABEL(clk) 1 21>,
 344                                  <&CP110_LABEL(clk) 1 17>;
 345                         status = "disabled";
 346                 };
 347
 348                 CP110_LABEL(uart3): serial@702300 {
 349                         compatible = "snps,dw-apb-uart";
 350                         reg = <0x702300 0x100>;
 351                         reg-shift = <2>;
 352                         interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
 353                         reg-io-width = <1>;
 354                         clock-names = "baudclk", "apb_pclk";
 355                         clocks = <&CP110_LABEL(clk) 1 21>,
 356                                  <&CP110_LABEL(clk) 1 17>;
 357                         status = "disabled";
 358                 };
 359
 360                 CP110_LABEL(nand_controller): nand@720000 {
 361                         /*
 362                         * Due to the limitation of the pins available
 363                         * this controller is only usable on the CPM
 364                         * for A7K and on the CPS for A8K.
 365                         */
 366                         compatible = "marvell,armada-8k-nand-controller",
 367                                 "marvell,armada370-nand-controller";
 368                         reg = <0x720000 0x54>;
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 372                         clock-names = "core", "reg";
 373                         clocks = <&CP110_LABEL(clk) 1 2>,
 374                                  <&CP110_LABEL(clk) 1 17>;
 375                         marvell,system-controller = <&CP110_LABEL(syscon0)>;
 376                         status = "disabled";
 377                 };
 378
 379                 CP110_LABEL(trng): trng@760000 {
 380                         compatible = "marvell,armada-8k-rng",
 381                         "inside-secure,safexcel-eip76";
 382                         reg = <0x760000 0x7d>;
 383                         interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
 384                         clock-names = "core", "reg";
 385                         clocks = <&CP110_LABEL(clk) 1 25>,
 386                                  <&CP110_LABEL(clk) 1 17>;
 387                         status = "okay";
 388                 };
 389
 390                 CP110_LABEL(sdhci0): sdhci@780000 {
 391                         compatible = "marvell,armada-cp110-sdhci";
 392                         reg = <0x780000 0x300>;
 393                         interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
 394                         clock-names = "core", "axi";
 395                         clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
 396                         dma-coherent;
 397                         status = "disabled";
 398                 };
 399
 400                 CP110_LABEL(crypto): crypto@800000 {
 401                         compatible = "inside-secure,safexcel-eip197";
 402                         reg = <0x800000 0x200000>;
 403                         interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 404                                 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 405                                 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 406                                 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 407                                 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 408                                 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 409                         interrupt-names = "mem", "ring0", "ring1",
 410                                 "ring2", "ring3", "eip";
 411                         clock-names = "core", "reg";
 412                         clocks = <&CP110_LABEL(clk) 1 26>,
 413                                  <&CP110_LABEL(clk) 1 17>;
 414                         dma-coherent;
 415                 };
 416         };
 417
 418         CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
 419                 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 420                 reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
 421                       <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
 422                 reg-names = "ctrl", "config";
 423                 #address-cells = <3>;
 424                 #size-cells = <2>;
 425                 #interrupt-cells = <1>;
 426                 device_type = "pci";
 427                 dma-coherent;
 428                 msi-parent = <&gic_v2m0>;
 429
 430                 bus-range = <0 0xff>;
 431                 ranges =
 432                 /* downstream I/O */
 433                 <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0  CP110_PCIEx_IO_BASE(0) 0 0x10000
 434                 /* non-prefetchable memory */
 435                 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0  CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
 436                 interrupt-map-mask = <0 0 0 0>;
 437                 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 438                 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 439                 num-lanes = <1>;
 440                 clock-names = "core", "reg";
 441                 clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
 442                 status = "disabled";
 443         };
 444
 445         CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
 446                 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 447                 reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
 448                       <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
 449                 reg-names = "ctrl", "config";
 450                 #address-cells = <3>;
 451                 #size-cells = <2>;
 452                 #interrupt-cells = <1>;
 453                 device_type = "pci";
 454                 dma-coherent;
 455                 msi-parent = <&gic_v2m0>;
 456
 457                 bus-range = <0 0xff>;
 458                 ranges =
 459                 /* downstream I/O */
 460                 <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0  CP110_PCIEx_IO_BASE(1) 0 0x10000
 461                 /* non-prefetchable memory */
 462                 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0  CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
 463                 interrupt-map-mask = <0 0 0 0>;
 464                 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 465                 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 466
 467                 num-lanes = <1>;
 468                 clock-names = "core", "reg";
 469                 clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
 470                 status = "disabled";
 471         };
 472
 473         CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
 474                 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 475                 reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
 476                       <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
 477                 reg-names = "ctrl", "config";
 478                 #address-cells = <3>;
 479                 #size-cells = <2>;
 480                 #interrupt-cells = <1>;
 481                 device_type = "pci";
 482                 dma-coherent;
 483                 msi-parent = <&gic_v2m0>;
 484
 485                 bus-range = <0 0xff>;
 486                 ranges =
 487                 /* downstream I/O */
 488                 <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0  CP110_PCIEx_IO_BASE(2) 0 0x10000
 489                 /* non-prefetchable memory */
 490                 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0  CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
 491                 interrupt-map-mask = <0 0 0 0>;
 492                 interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 493                 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 494
 495                 num-lanes = <1>;
 496                 clock-names = "core", "reg";
 497                 clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
 498                 status = "disabled";
 499         };
 500 };