arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

   1 /*
   2  * Copyright (C) 2016 Marvell Technology Group Ltd.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPLv2 or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /*
  44  * Device Tree file for Marvell Armada CP110 Slave.
  45  */
  46
  47 #define ICU_GRP_NSR 0x0
  48
  49 / {
  50         cp110-slave {
  51                 #address-cells = <2>;
  52                 #size-cells = <2>;
  53                 compatible = "simple-bus";
  54                 interrupt-parent = <&cps_icu>;
  55                 ranges;
  56
  57                 config-space@f4000000 {
  58                         #address-cells = <1>;
  59                         #size-cells = <1>;
  60                         compatible = "simple-bus";
  61                         ranges = <0x0 0x0 0xf4000000 0x2000000>;
  62
  63                         cps_ethernet: ethernet@0 {
  64                                 compatible = "marvell,armada-7k-pp22";
  65                                 reg = <0x0 0x100000>, <0x129000 0xb000>;
  66                                 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>,
  67                                          <&cps_clk 1 5>, <&cps_clk 1 18>;
  68                                 clock-names = "pp_clk", "gop_clk",
  69                                               "mg_clk", "axi_clk";
  70                                 marvell,system-controller = <&cps_syscon0>;
  71                                 status = "disabled";
  72                                 dma-coherent;
  73
  74                                 cps_eth0: eth0 {
  75                                         interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
  76                                                      <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
  77                                                      <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
  78                                                      <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
  79                                                      <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
  80                                                      <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
  81                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  82                                                           "tx-cpu3", "rx-shared", "link";
  83                                         port-id = <0>;
  84                                         gop-port-id = <0>;
  85                                         status = "disabled";
  86                                 };
  87
  88                                 cps_eth1: eth1 {
  89                                         interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
  90                                                      <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
  91                                                      <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
  92                                                      <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
  93                                                      <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
  94                                                      <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
  95                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  96                                                           "tx-cpu3", "rx-shared", "link";
  97                                         port-id = <1>;
  98                                         gop-port-id = <2>;
  99                                         status = "disabled";
 100                                 };
 101
 102                                 cps_eth2: eth2 {
 103                                         interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
 104                                                      <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 105                                                      <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 106                                                      <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
 107                                                      <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
 108                                                      <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
 109                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
 110                                                           "tx-cpu3", "rx-shared", "link";
 111                                         port-id = <2>;
 112                                         gop-port-id = <3>;
 113                                         status = "disabled";
 114                                 };
 115                         };
 116
 117                         cps_comphy: phy@120000 {
 118                                 compatible = "marvell,comphy-cp110";
 119                                 reg = <0x120000 0x6000>;
 120                                 marvell,system-controller = <&cps_syscon0>;
 121                                 #address-cells = <1>;
 122                                 #size-cells = <0>;
 123
 124                                 cps_comphy0: phy@0 {
 125                                         reg = <0>;
 126                                         #phy-cells = <1>;
 127                                 };
 128
 129                                 cps_comphy1: phy@1 {
 130                                         reg = <1>;
 131                                         #phy-cells = <1>;
 132                                 };
 133
 134                                 cps_comphy2: phy@2 {
 135                                         reg = <2>;
 136                                         #phy-cells = <1>;
 137                                 };
 138
 139                                 cps_comphy3: phy@3 {
 140                                         reg = <3>;
 141                                         #phy-cells = <1>;
 142                                 };
 143
 144                                 cps_comphy4: phy@4 {
 145                                         reg = <4>;
 146                                         #phy-cells = <1>;
 147                                 };
 148
 149                                 cps_comphy5: phy@5 {
 150                                         reg = <5>;
 151                                         #phy-cells = <1>;
 152                                 };
 153                         };
 154
 155                         cps_mdio: mdio@12a200 {
 156                                 #address-cells = <1>;
 157                                 #size-cells = <0>;
 158                                 compatible = "marvell,orion-mdio";
 159                                 reg = <0x12a200 0x10>;
 160                                 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>,
 161                                          <&cps_clk 1 6>, <&cps_clk 1 18>;
 162                                 status = "disabled";
 163                         };
 164
 165                         cps_xmdio: mdio@12a600 {
 166                                 #address-cells = <1>;
 167                                 #size-cells = <0>;
 168                                 compatible = "marvell,xmdio";
 169                                 reg = <0x12a600 0x10>;
 170                                 status = "disabled";
 171                         };
 172
 173                         cps_icu: interrupt-controller@1e0000 {
 174                                 compatible = "marvell,cp110-icu";
 175                                 reg = <0x1e0000 0x10>;
 176                                 #interrupt-cells = <3>;
 177                                 interrupt-controller;
 178                                 msi-parent = <&gicp>;
 179                         };
 180
 181                         cps_rtc: rtc@284000 {
 182                                 compatible = "marvell,armada-8k-rtc";
 183                                 reg = <0x284000 0x20>, <0x284080 0x24>;
 184                                 reg-names = "rtc", "rtc-soc";
 185                                 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
 186                         };
 187
 188                         cps_syscon0: system-controller@440000 {
 189                                 compatible = "syscon", "simple-mfd";
 190                                 reg = <0x440000 0x2000>;
 191
 192                                 cps_clk: clock {
 193                                         compatible = "marvell,cp110-clock";
 194                                         #clock-cells = <2>;
 195                                 };
 196
 197                                 cps_gpio1: gpio@100 {
 198                                         compatible = "marvell,armada-8k-gpio";
 199                                         offset = <0x100>;
 200                                         ngpios = <32>;
 201                                         gpio-controller;
 202                                         #gpio-cells = <2>;
 203                                         gpio-ranges = <&cps_pinctrl 0 0 32>;
 204                                         interrupt-controller;
 205                                         interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
 206                                                      <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
 207                                                      <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
 208                                                      <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
 209                                         status = "disabled";
 210                                 };
 211
 212                                 cps_gpio2: gpio@140 {
 213                                         compatible = "marvell,armada-8k-gpio";
 214                                         offset = <0x140>;
 215                                         ngpios = <31>;
 216                                         gpio-controller;
 217                                         #gpio-cells = <2>;
 218                                         gpio-ranges = <&cps_pinctrl 0 32 31>;
 219                                         interrupt-controller;
 220                                         interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
 221                                                      <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
 222                                                      <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
 223                                                      <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
 224                                         status = "disabled";
 225                                 };
 226
 227                         };
 228
 229                         cps_usb3_0: usb3@500000 {
 230                                 compatible = "marvell,armada-8k-xhci",
 231                                              "generic-xhci";
 232                                 reg = <0x500000 0x4000>;
 233                                 dma-coherent;
 234                                 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
 235                                 clocks = <&cps_clk 1 22>;
 236                                 status = "disabled";
 237                         };
 238
 239                         cps_usb3_1: usb3@510000 {
 240                                 compatible = "marvell,armada-8k-xhci",
 241                                              "generic-xhci";
 242                                 reg = <0x510000 0x4000>;
 243                                 dma-coherent;
 244                                 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
 245                                 clocks = <&cps_clk 1 23>;
 246                                 status = "disabled";
 247                         };
 248
 249                         cps_sata0: sata@540000 {
 250                                 compatible = "marvell,armada-8k-ahci",
 251                                              "generic-ahci";
 252                                 reg = <0x540000 0x30000>;
 253                                 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
 254                                 clocks = <&cps_clk 1 15>;
 255                                 status = "disabled";
 256                         };
 257
 258                         cps_xor0: xor@6a0000 {
 259                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 260                                 reg = <0x6a0000 0x1000>,
 261                                       <0x6b0000 0x1000>;
 262                                 dma-coherent;
 263                                 msi-parent = <&gic_v2m0>;
 264                                 clocks = <&cps_clk 1 8>;
 265                         };
 266
 267                         cps_xor1: xor@6c0000 {
 268                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 269                                 reg = <0x6c0000 0x1000>,
 270                                       <0x6d0000 0x1000>;
 271                                 dma-coherent;
 272                                 msi-parent = <&gic_v2m0>;
 273                                 clocks = <&cps_clk 1 7>;
 274                         };
 275
 276                         cps_spi0: spi@700600 {
 277                                 compatible = "marvell,armada-380-spi";
 278                                 reg = <0x700600 0x50>;
 279                                 #address-cells = <0x1>;
 280                                 #size-cells = <0x0>;
 281                                 cell-index = <3>;
 282                                 clocks = <&cps_clk 1 21>;
 283                                 status = "disabled";
 284                         };
 285
 286                         cps_spi1: spi@700680 {
 287                                 compatible = "marvell,armada-380-spi";
 288                                 reg = <0x700680 0x50>;
 289                                 #address-cells = <1>;
 290                                 #size-cells = <0>;
 291                                 cell-index = <4>;
 292                                 clocks = <&cps_clk 1 21>;
 293                                 status = "disabled";
 294                         };
 295
 296                         cps_i2c0: i2c@701000 {
 297                                 compatible = "marvell,mv78230-i2c";
 298                                 reg = <0x701000 0x20>;
 299                                 #address-cells = <1>;
 300                                 #size-cells = <0>;
 301                                 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
 302                                 clocks = <&cps_clk 1 21>;
 303                                 status = "disabled";
 304                         };
 305
 306                         cps_i2c1: i2c@701100 {
 307                                 compatible = "marvell,mv78230-i2c";
 308                                 reg = <0x701100 0x20>;
 309                                 #address-cells = <1>;
 310                                 #size-cells = <0>;
 311                                 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&cps_clk 1 21>;
 313                                 status = "disabled";
 314                         };
 315
 316                         cps_nand: nand@720000 {
 317                                 /*
 318                                  * Due to the limiation of the pin available
 319                                  * this controller is only usable on the CPM
 320                                  * for A7K and on the CPS for A8K.
 321                                  */
 322                                 compatible = "marvell,armada370-nand",
 323                                              "marvell,armada370-nand";
 324                                 reg = <0x720000 0x54>;
 325                                 #address-cells = <1>;
 326                                 #size-cells = <1>;
 327                                 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&cps_clk 1 2>;
 329                                 status = "disabled";
 330                         };
 331
 332                         cps_trng: trng@760000 {
 333                                 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
 334                                 reg = <0x760000 0x7d>;
 335                                 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
 336                                 clocks = <&cps_clk 1 25>;
 337                                 status = "okay";
 338                         };
 339
 340                         cps_crypto: crypto@800000 {
 341                                 compatible = "inside-secure,safexcel-eip197";
 342                                 reg = <0x800000 0x200000>;
 343                                 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 344                                              <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 345                                              <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 346                                              <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 347                                              <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 348                                              <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 349                                 interrupt-names = "mem", "ring0", "ring1",
 350                                                   "ring2", "ring3", "eip";
 351                                 clocks = <&cps_clk 1 26>;
 352                                 dma-coherent;
 353                                 /*
 354                                  * The cryptographic engine found on the cp110
 355                                  * master is enabled by default at the SoC
 356                                  * level. Because it is not possible as of now
 357                                  * to enable two cryptographic engines in
 358                                  * parallel, disable this one by default.
 359                                  */
 360                                 status = "disabled";
 361                         };
 362                 };
 363
 364                 cps_pcie0: pcie@f4600000 {
 365                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 366                         reg = <0 0xf4600000 0 0x10000>,
 367                               <0 0xfaf00000 0 0x80000>;
 368                         reg-names = "ctrl", "config";
 369                         #address-cells = <3>;
 370                         #size-cells = <2>;
 371                         #interrupt-cells = <1>;
 372                         device_type = "pci";
 373                         dma-coherent;
 374                         msi-parent = <&gic_v2m0>;
 375
 376                         bus-range = <0 0xff>;
 377                         ranges =
 378                                 /* downstream I/O */
 379                                 <0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
 380                                 /* non-prefetchable memory */
 381                                 0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
 382                         interrupt-map-mask = <0 0 0 0>;
 383                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 384                         interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 385                         num-lanes = <1>;
 386                         clocks = <&cps_clk 1 13>;
 387                         status = "disabled";
 388                 };
 389
 390                 cps_pcie1: pcie@f4620000 {
 391                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 392                         reg = <0 0xf4620000 0 0x10000>,
 393                               <0 0xfbf00000 0 0x80000>;
 394                         reg-names = "ctrl", "config";
 395                         #address-cells = <3>;
 396                         #size-cells = <2>;
 397                         #interrupt-cells = <1>;
 398                         device_type = "pci";
 399                         dma-coherent;
 400                         msi-parent = <&gic_v2m0>;
 401
 402                         bus-range = <0 0xff>;
 403                         ranges =
 404                                 /* downstream I/O */
 405                                 <0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
 406                                 /* non-prefetchable memory */
 407                                 0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
 408                         interrupt-map-mask = <0 0 0 0>;
 409                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 410                         interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 411
 412                         num-lanes = <1>;
 413                         clocks = <&cps_clk 1 11>;
 414                         status = "disabled";
 415                 };
 416
 417                 cps_pcie2: pcie@f4640000 {
 418                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 419                         reg = <0 0xf4640000 0 0x10000>,
 420                               <0 0xfcf00000 0 0x80000>;
 421                         reg-names = "ctrl", "config";
 422                         #address-cells = <3>;
 423                         #size-cells = <2>;
 424                         #interrupt-cells = <1>;
 425                         device_type = "pci";
 426                         dma-coherent;
 427                         msi-parent = <&gic_v2m0>;
 428
 429                         bus-range = <0 0xff>;
 430                         ranges =
 431                                 /* downstream I/O */
 432                                 <0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
 433                                 /* non-prefetchable memory */
 434                                 0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
 435                         interrupt-map-mask = <0 0 0 0>;
 436                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 437                         interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 438
 439                         num-lanes = <1>;
 440                         clocks = <&cps_clk 1 12>;
 441                         status = "disabled";
 442                 };
 443         };
 444 };