arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

   1 /*
   2  * Copyright (C) 2016 Marvell Technology Group Ltd.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPLv2 or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /*
  44  * Device Tree file for Marvell Armada CP110 Slave.
  45  */
  46
  47 #define ICU_GRP_NSR 0x0
  48
  49 / {
  50         cp110-slave {
  51                 #address-cells = <2>;
  52                 #size-cells = <2>;
  53                 compatible = "simple-bus";
  54                 interrupt-parent = <&cps_icu>;
  55                 ranges;
  56
  57                 config-space@f4000000 {
  58                         #address-cells = <1>;
  59                         #size-cells = <1>;
  60                         compatible = "simple-bus";
  61                         ranges = <0x0 0x0 0xf4000000 0x2000000>;
  62
  63                         cps_ethernet: ethernet@0 {
  64                                 compatible = "marvell,armada-7k-pp22";
  65                                 reg = <0x0 0x100000>, <0x129000 0xb000>;
  66                                 clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
  67                                 clock-names = "pp_clk", "gop_clk", "mg_clk";
  68                                 marvell,system-controller = <&cps_syscon0>;
  69                                 status = "disabled";
  70                                 dma-coherent;
  71
  72                                 cps_eth0: eth0 {
  73                                         interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
  74                                                      <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
  75                                                      <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
  76                                                      <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
  77                                                      <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;
  78                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  79                                                           "tx-cpu3", "rx-shared";
  80                                         port-id = <0>;
  81                                         gop-port-id = <0>;
  82                                         status = "disabled";
  83                                 };
  84
  85                                 cps_eth1: eth1 {
  86                                         interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
  87                                                      <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
  88                                                      <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
  89                                                      <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
  90                                                      <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;
  91                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
  92                                                           "tx-cpu3", "rx-shared";
  93                                         port-id = <1>;
  94                                         gop-port-id = <2>;
  95                                         status = "disabled";
  96                                 };
  97
  98                                 cps_eth2: eth2 {
  99                                         interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
 100                                                      <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
 101                                                      <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
 102                                                      <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
 103                                                      <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;
 104                                         interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
 105                                                           "tx-cpu3", "rx-shared";
 106                                         port-id = <2>;
 107                                         gop-port-id = <3>;
 108                                         status = "disabled";
 109                                 };
 110                         };
 111
 112                         cps_mdio: mdio@12a200 {
 113                                 #address-cells = <1>;
 114                                 #size-cells = <0>;
 115                                 compatible = "marvell,orion-mdio";
 116                                 reg = <0x12a200 0x10>;
 117                                 clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
 118                                 status = "disabled";
 119                         };
 120
 121                         cps_xmdio: mdio@12a600 {
 122                                 #address-cells = <1>;
 123                                 #size-cells = <0>;
 124                                 compatible = "marvell,xmdio";
 125                                 reg = <0x12a600 0x10>;
 126                                 status = "disabled";
 127                         };
 128
 129                         cps_icu: interrupt-controller@1e0000 {
 130                                 compatible = "marvell,cp110-icu";
 131                                 reg = <0x1e0000 0x10>;
 132                                 #interrupt-cells = <3>;
 133                                 interrupt-controller;
 134                                 msi-parent = <&gicp>;
 135                         };
 136
 137                         cps_rtc: rtc@284000 {
 138                                 compatible = "marvell,armada-8k-rtc";
 139                                 reg = <0x284000 0x20>, <0x284080 0x24>;
 140                                 reg-names = "rtc", "rtc-soc";
 141                                 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
 142                         };
 143
 144                         cps_syscon0: system-controller@440000 {
 145                                 compatible = "syscon", "simple-mfd";
 146                                 reg = <0x440000 0x1000>;
 147
 148                                 cps_clk: clock {
 149                                         compatible = "marvell,cp110-clock";
 150                                         #clock-cells = <2>;
 151                                 };
 152
 153                                 cps_gpio1: gpio@100 {
 154                                         compatible = "marvell,armada-8k-gpio";
 155                                         offset = <0x100>;
 156                                         ngpios = <32>;
 157                                         gpio-controller;
 158                                         #gpio-cells = <2>;
 159                                         gpio-ranges = <&cps_pinctrl 0 0 32>;
 160                                         interrupt-controller;
 161                                         interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
 162                                                      <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
 163                                                      <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
 164                                                      <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
 165                                         status = "disabled";
 166                                 };
 167
 168                                 cps_gpio2: gpio@140 {
 169                                         compatible = "marvell,armada-8k-gpio";
 170                                         offset = <0x140>;
 171                                         ngpios = <31>;
 172                                         gpio-controller;
 173                                         #gpio-cells = <2>;
 174                                         gpio-ranges = <&cps_pinctrl 0 32 31>;
 175                                         interrupt-controller;
 176                                         interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
 177                                                      <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
 178                                                      <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
 179                                                      <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
 180                                         status = "disabled";
 181                                 };
 182
 183                         };
 184
 185                         cps_usb3_0: usb3@500000 {
 186                                 compatible = "marvell,armada-8k-xhci",
 187                                              "generic-xhci";
 188                                 reg = <0x500000 0x4000>;
 189                                 dma-coherent;
 190                                 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
 191                                 clocks = <&cps_clk 1 22>;
 192                                 status = "disabled";
 193                         };
 194
 195                         cps_usb3_1: usb3@510000 {
 196                                 compatible = "marvell,armada-8k-xhci",
 197                                              "generic-xhci";
 198                                 reg = <0x510000 0x4000>;
 199                                 dma-coherent;
 200                                 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
 201                                 clocks = <&cps_clk 1 23>;
 202                                 status = "disabled";
 203                         };
 204
 205                         cps_sata0: sata@540000 {
 206                                 compatible = "marvell,armada-8k-ahci",
 207                                              "generic-ahci";
 208                                 reg = <0x540000 0x30000>;
 209                                 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
 210                                 clocks = <&cps_clk 1 15>;
 211                                 status = "disabled";
 212                         };
 213
 214                         cps_xor0: xor@6a0000 {
 215                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 216                                 reg = <0x6a0000 0x1000>,
 217                                       <0x6b0000 0x1000>;
 218                                 dma-coherent;
 219                                 msi-parent = <&gic_v2m0>;
 220                                 clocks = <&cps_clk 1 8>;
 221                         };
 222
 223                         cps_xor1: xor@6c0000 {
 224                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 225                                 reg = <0x6c0000 0x1000>,
 226                                       <0x6d0000 0x1000>;
 227                                 dma-coherent;
 228                                 msi-parent = <&gic_v2m0>;
 229                                 clocks = <&cps_clk 1 7>;
 230                         };
 231
 232                         cps_spi0: spi@700600 {
 233                                 compatible = "marvell,armada-380-spi";
 234                                 reg = <0x700600 0x50>;
 235                                 #address-cells = <0x1>;
 236                                 #size-cells = <0x0>;
 237                                 cell-index = <3>;
 238                                 clocks = <&cps_clk 1 21>;
 239                                 status = "disabled";
 240                         };
 241
 242                         cps_spi1: spi@700680 {
 243                                 compatible = "marvell,armada-380-spi";
 244                                 reg = <0x700680 0x50>;
 245                                 #address-cells = <1>;
 246                                 #size-cells = <0>;
 247                                 cell-index = <4>;
 248                                 clocks = <&cps_clk 1 21>;
 249                                 status = "disabled";
 250                         };
 251
 252                         cps_i2c0: i2c@701000 {
 253                                 compatible = "marvell,mv78230-i2c";
 254                                 reg = <0x701000 0x20>;
 255                                 #address-cells = <1>;
 256                                 #size-cells = <0>;
 257                                 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
 258                                 clocks = <&cps_clk 1 21>;
 259                                 status = "disabled";
 260                         };
 261
 262                         cps_i2c1: i2c@701100 {
 263                                 compatible = "marvell,mv78230-i2c";
 264                                 reg = <0x701100 0x20>;
 265                                 #address-cells = <1>;
 266                                 #size-cells = <0>;
 267                                 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
 268                                 clocks = <&cps_clk 1 21>;
 269                                 status = "disabled";
 270                         };
 271
 272                         cps_nand: nand@720000 {
 273                                 /*
 274                                  * Due to the limiation of the pin available
 275                                  * this controller is only usable on the CPM
 276                                  * for A7K and on the CPS for A8K.
 277                                  */
 278                                 compatible = "marvell,armada370-nand";
 279                                 reg = <0x720000 0x54>;
 280                                 #address-cells = <1>;
 281                                 #size-cells = <1>;
 282                                 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
 283                                 clocks = <&cps_clk 1 2>;
 284                                 status = "disabled";
 285                         };
 286
 287                         cps_trng: trng@760000 {
 288                                 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
 289                                 reg = <0x760000 0x7d>;
 290                                 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
 291                                 clocks = <&cps_clk 1 25>;
 292                                 status = "okay";
 293                         };
 294
 295                         cps_crypto: crypto@800000 {
 296                                 compatible = "inside-secure,safexcel-eip197";
 297                                 reg = <0x800000 0x200000>;
 298                                 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
 299                                              <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
 300                                              <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
 301                                              <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
 302                                              <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
 303                                              <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
 304                                 interrupt-names = "mem", "ring0", "ring1",
 305                                                   "ring2", "ring3", "eip";
 306                                 clocks = <&cps_clk 1 26>;
 307                                 dma-coherent;
 308                                 /*
 309                                  * The cryptographic engine found on the cp110
 310                                  * master is enabled by default at the SoC
 311                                  * level. Because it is not possible as of now
 312                                  * to enable two cryptographic engines in
 313                                  * parallel, disable this one by default.
 314                                  */
 315                                 status = "disabled";
 316                         };
 317                 };
 318
 319                 cps_pcie0: pcie@f4600000 {
 320                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 321                         reg = <0 0xf4600000 0 0x10000>,
 322                               <0 0xfaf00000 0 0x80000>;
 323                         reg-names = "ctrl", "config";
 324                         #address-cells = <3>;
 325                         #size-cells = <2>;
 326                         #interrupt-cells = <1>;
 327                         device_type = "pci";
 328                         dma-coherent;
 329                         msi-parent = <&gic_v2m0>;
 330
 331                         bus-range = <0 0xff>;
 332                         ranges =
 333                                 /* downstream I/O */
 334                                 <0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
 335                                 /* non-prefetchable memory */
 336                                 0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
 337                         interrupt-map-mask = <0 0 0 0>;
 338                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 339                         interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
 340                         num-lanes = <1>;
 341                         clocks = <&cps_clk 1 13>;
 342                         status = "disabled";
 343                 };
 344
 345                 cps_pcie1: pcie@f4620000 {
 346                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 347                         reg = <0 0xf4620000 0 0x10000>,
 348                               <0 0xfbf00000 0 0x80000>;
 349                         reg-names = "ctrl", "config";
 350                         #address-cells = <3>;
 351                         #size-cells = <2>;
 352                         #interrupt-cells = <1>;
 353                         device_type = "pci";
 354                         dma-coherent;
 355                         msi-parent = <&gic_v2m0>;
 356
 357                         bus-range = <0 0xff>;
 358                         ranges =
 359                                 /* downstream I/O */
 360                                 <0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
 361                                 /* non-prefetchable memory */
 362                                 0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
 363                         interrupt-map-mask = <0 0 0 0>;
 364                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 365                         interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
 366
 367                         num-lanes = <1>;
 368                         clocks = <&cps_clk 1 11>;
 369                         status = "disabled";
 370                 };
 371
 372                 cps_pcie2: pcie@f4640000 {
 373                         compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
 374                         reg = <0 0xf4640000 0 0x10000>,
 375                               <0 0xfcf00000 0 0x80000>;
 376                         reg-names = "ctrl", "config";
 377                         #address-cells = <3>;
 378                         #size-cells = <2>;
 379                         #interrupt-cells = <1>;
 380                         device_type = "pci";
 381                         dma-coherent;
 382                         msi-parent = <&gic_v2m0>;
 383
 384                         bus-range = <0 0xff>;
 385                         ranges =
 386                                 /* downstream I/O */
 387                                 <0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
 388                                 /* non-prefetchable memory */
 389                                 0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
 390                         interrupt-map-mask = <0 0 0 0>;
 391                         interrupt-map = <0 0 0 0 &cps_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 392                         interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
 393
 394                         num-lanes = <1>;
 395                         clocks = <&cps_clk 1 12>;
 396                         status = "disabled";
 397                 };
 398         };
 399 };