2 * Copyright (C) 2016 Marvell Technology Group Ltd.
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
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27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
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33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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44 * Device Tree file for Marvell Armada CP110 Master.
47 #define ICU_GRP_NSR 0x0
53 compatible = "simple-bus";
54 interrupt-parent = <&cpm_icu>;
57 config-space@f2000000 {
60 compatible = "simple-bus";
61 ranges = <0x0 0x0 0xf2000000 0x2000000>;
63 cpm_ethernet: ethernet@0 {
64 compatible = "marvell,armada-7k-pp22";
65 reg = <0x0 0x100000>, <0x129000 0xb000>;
66 clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>,
67 <&cpm_clk 1 5>, <&cpm_clk 1 18>;
68 clock-names = "pp_clk", "gop_clk",
70 marvell,system-controller = <&cpm_syscon0>;
75 interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
76 <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
77 <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
78 <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
79 <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
80 <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
81 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
82 "tx-cpu3", "rx-shared", "link";
89 interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
90 <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
91 <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
92 <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
93 <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
94 <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
95 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
96 "tx-cpu3", "rx-shared", "link";
103 interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
104 <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
105 <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
106 <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
107 <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
108 <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
110 "tx-cpu3", "rx-shared", "link";
117 cpm_comphy: phy@120000 {
118 compatible = "marvell,comphy-cp110";
119 reg = <0x120000 0x6000>;
120 marvell,system-controller = <&cpm_syscon0>;
121 #address-cells = <1>;
155 cpm_mdio: mdio@12a200 {
156 #address-cells = <1>;
158 compatible = "marvell,orion-mdio";
159 reg = <0x12a200 0x10>;
160 clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>,
161 <&cpm_clk 1 6>, <&cpm_clk 1 18>;
165 cpm_xmdio: mdio@12a600 {
166 #address-cells = <1>;
168 compatible = "marvell,xmdio";
169 reg = <0x12a600 0x10>;
173 cpm_icu: interrupt-controller@1e0000 {
174 compatible = "marvell,cp110-icu";
175 reg = <0x1e0000 0x10>;
176 #interrupt-cells = <3>;
177 interrupt-controller;
178 msi-parent = <&gicp>;
181 cpm_rtc: rtc@284000 {
182 compatible = "marvell,armada-8k-rtc";
183 reg = <0x284000 0x20>, <0x284080 0x24>;
184 reg-names = "rtc", "rtc-soc";
185 interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
188 cpm_syscon0: system-controller@440000 {
189 compatible = "syscon", "simple-mfd";
190 reg = <0x440000 0x2000>;
193 compatible = "marvell,cp110-clock";
197 cpm_gpio1: gpio@100 {
198 compatible = "marvell,armada-8k-gpio";
203 gpio-ranges = <&cpm_pinctrl 0 0 32>;
204 interrupt-controller;
205 interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
206 <ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
207 <ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
208 <ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
212 cpm_gpio2: gpio@140 {
213 compatible = "marvell,armada-8k-gpio";
218 gpio-ranges = <&cpm_pinctrl 0 32 31>;
219 interrupt-controller;
220 interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
221 <ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
222 <ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
223 <ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
228 cpm_usb3_0: usb3@500000 {
229 compatible = "marvell,armada-8k-xhci",
231 reg = <0x500000 0x4000>;
233 interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&cpm_clk 1 22>;
238 cpm_usb3_1: usb3@510000 {
239 compatible = "marvell,armada-8k-xhci",
241 reg = <0x510000 0x4000>;
243 interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&cpm_clk 1 23>;
248 cpm_sata0: sata@540000 {
249 compatible = "marvell,armada-8k-ahci",
251 reg = <0x540000 0x30000>;
252 interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cpm_clk 1 15>;
257 cpm_xor0: xor@6a0000 {
258 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
259 reg = <0x6a0000 0x1000>,
262 msi-parent = <&gic_v2m0>;
263 clocks = <&cpm_clk 1 8>;
266 cpm_xor1: xor@6c0000 {
267 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
268 reg = <0x6c0000 0x1000>,
271 msi-parent = <&gic_v2m0>;
272 clocks = <&cpm_clk 1 7>;
275 cpm_spi0: spi@700600 {
276 compatible = "marvell,armada-380-spi";
277 reg = <0x700600 0x50>;
278 #address-cells = <0x1>;
281 clocks = <&cpm_clk 1 21>;
285 cpm_spi1: spi@700680 {
286 compatible = "marvell,armada-380-spi";
287 reg = <0x700680 0x50>;
288 #address-cells = <1>;
291 clocks = <&cpm_clk 1 21>;
295 cpm_i2c0: i2c@701000 {
296 compatible = "marvell,mv78230-i2c";
297 reg = <0x701000 0x20>;
298 #address-cells = <1>;
300 interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&cpm_clk 1 21>;
305 cpm_i2c1: i2c@701100 {
306 compatible = "marvell,mv78230-i2c";
307 reg = <0x701100 0x20>;
308 #address-cells = <1>;
310 interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&cpm_clk 1 21>;
315 cpm_nand: nand@720000 {
317 * Due to the limiation of the pin available
318 * this controller is only usable on the CPM
319 * for A7K and on the CPS for A8K.
321 compatible = "marvell,armada-8k-nand",
322 "marvell,armada370-nand";
323 reg = <0x720000 0x54>;
324 #address-cells = <1>;
326 interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&cpm_clk 1 2>;
328 marvell,system-controller = <&cpm_syscon0>;
332 cpm_trng: trng@760000 {
333 compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
334 reg = <0x760000 0x7d>;
335 interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&cpm_clk 1 25>;
340 cpm_sdhci0: sdhci@780000 {
341 compatible = "marvell,armada-cp110-sdhci";
342 reg = <0x780000 0x300>;
343 interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
344 clock-names = "core","axi";
345 clocks = <&cpm_clk 1 4>, <&cpm_clk 1 18>;
350 cpm_crypto: crypto@800000 {
351 compatible = "inside-secure,safexcel-eip197";
352 reg = <0x800000 0x200000>;
353 interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
354 <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
355 <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
356 <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
357 <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
358 <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
359 interrupt-names = "mem", "ring0", "ring1",
360 "ring2", "ring3", "eip";
361 clocks = <&cpm_clk 1 26>;
366 cpm_pcie0: pcie@f2600000 {
367 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
368 reg = <0 0xf2600000 0 0x10000>,
369 <0 0xf6f00000 0 0x80000>;
370 reg-names = "ctrl", "config";
371 #address-cells = <3>;
373 #interrupt-cells = <1>;
376 msi-parent = <&gic_v2m0>;
378 bus-range = <0 0xff>;
381 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
382 /* non-prefetchable memory */
383 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
384 interrupt-map-mask = <0 0 0 0>;
385 interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
386 interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&cpm_clk 1 13>;
392 cpm_pcie1: pcie@f2620000 {
393 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
394 reg = <0 0xf2620000 0 0x10000>,
395 <0 0xf7f00000 0 0x80000>;
396 reg-names = "ctrl", "config";
397 #address-cells = <3>;
399 #interrupt-cells = <1>;
402 msi-parent = <&gic_v2m0>;
404 bus-range = <0 0xff>;
407 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
408 /* non-prefetchable memory */
409 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
410 interrupt-map-mask = <0 0 0 0>;
411 interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
412 interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&cpm_clk 1 11>;
419 cpm_pcie2: pcie@f2640000 {
420 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
421 reg = <0 0xf2640000 0 0x10000>,
422 <0 0xf8f00000 0 0x80000>;
423 reg-names = "ctrl", "config";
424 #address-cells = <3>;
426 #interrupt-cells = <1>;
429 msi-parent = <&gic_v2m0>;
431 bus-range = <0 0xff>;
434 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
435 /* non-prefetchable memory */
436 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
437 interrupt-map-mask = <0 0 0 0>;
438 interrupt-map = <0 0 0 0 &cpm_icu ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
439 interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cpm_clk 1 12>;