arch/arm64/boot/dts/marvell/armada-ap806.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada AP806.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 /dts-v1/;
  12
  13 / {
  14         model = "Marvell Armada AP806";
  15         compatible = "marvell,armada-ap806";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 gpio0 = &ap_gpio;
  23                 spi0 = &spi0;
  24         };
  25
  26         psci {
  27                 compatible = "arm,psci-0.2";
  28                 method = "smc";
  29         };
  30
  31         reserved-memory {
  32                 #address-cells = <2>;
  33                 #size-cells = <2>;
  34                 ranges;
  35
  36                 /*
  37                  * This area matches the mapping done with a
  38                  * mainline U-Boot, and should be updated by the
  39                  * bootloader.
  40                  */
  41
  42                 psci-area@4000000 {
  43                         reg = <0x0 0x4000000 0x0 0x200000>;
  44                         no-map;
  45                 };
  46         };
  47
  48         ap806 {
  49                 #address-cells = <2>;
  50                 #size-cells = <2>;
  51                 compatible = "simple-bus";
  52                 interrupt-parent = <&gic>;
  53                 ranges;
  54
  55                 config-space@f0000000 {
  56                         #address-cells = <1>;
  57                         #size-cells = <1>;
  58                         compatible = "simple-bus";
  59                         ranges = <0x0 0x0 0xf0000000 0x1000000>;
  60
  61                         gic: interrupt-controller@210000 {
  62                                 compatible = "arm,gic-400";
  63                                 #interrupt-cells = <3>;
  64                                 #address-cells = <1>;
  65                                 #size-cells = <1>;
  66                                 ranges;
  67                                 interrupt-controller;
  68                                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  69                                 reg = <0x210000 0x10000>,
  70                                       <0x220000 0x20000>,
  71                                       <0x240000 0x20000>,
  72                                       <0x260000 0x20000>;
  73
  74                                 gic_v2m0: v2m@280000 {
  75                                         compatible = "arm,gic-v2m-frame";
  76                                         msi-controller;
  77                                         reg = <0x280000 0x1000>;
  78                                         arm,msi-base-spi = <160>;
  79                                         arm,msi-num-spis = <32>;
  80                                 };
  81                                 gic_v2m1: v2m@290000 {
  82                                         compatible = "arm,gic-v2m-frame";
  83                                         msi-controller;
  84                                         reg = <0x290000 0x1000>;
  85                                         arm,msi-base-spi = <192>;
  86                                         arm,msi-num-spis = <32>;
  87                                 };
  88                                 gic_v2m2: v2m@2a0000 {
  89                                         compatible = "arm,gic-v2m-frame";
  90                                         msi-controller;
  91                                         reg = <0x2a0000 0x1000>;
  92                                         arm,msi-base-spi = <224>;
  93                                         arm,msi-num-spis = <32>;
  94                                 };
  95                                 gic_v2m3: v2m@2b0000 {
  96                                         compatible = "arm,gic-v2m-frame";
  97                                         msi-controller;
  98                                         reg = <0x2b0000 0x1000>;
  99                                         arm,msi-base-spi = <256>;
 100                                         arm,msi-num-spis = <32>;
 101                                 };
 102                         };
 103
 104                         timer {
 105                                 compatible = "arm,armv8-timer";
 106                                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 107                                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 108                                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 109                                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 110                         };
 111
 112                         pmu {
 113                                 compatible = "arm,cortex-a72-pmu";
 114                                 interrupt-parent = <&pic>;
 115                                 interrupts = <17>;
 116                         };
 117
 118                         odmi: odmi@300000 {
 119                                 compatible = "marvell,odmi-controller";
 120                                 interrupt-controller;
 121                                 msi-controller;
 122                                 marvell,odmi-frames = <4>;
 123                                 reg = <0x300000 0x4000>,
 124                                       <0x304000 0x4000>,
 125                                       <0x308000 0x4000>,
 126                                       <0x30C000 0x4000>;
 127                                 marvell,spi-base = <128>, <136>, <144>, <152>;
 128                         };
 129
 130                         gicp: gicp@3f0040 {
 131                                 compatible = "marvell,ap806-gicp";
 132                                 reg = <0x3f0040 0x10>;
 133                                 marvell,spi-ranges = <64 64>, <288 64>;
 134                                 msi-controller;
 135                         };
 136
 137                         pic: interrupt-controller@3f0100 {
 138                                 compatible = "marvell,armada-8k-pic";
 139                                 reg = <0x3f0100 0x10>;
 140                                 #interrupt-cells = <1>;
 141                                 interrupt-controller;
 142                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
 143                         };
 144
 145                         sei: interrupt-controller@3f0200 {
 146                                 compatible = "marvell,ap806-sei";
 147                                 reg = <0x3f0200 0x40>;
 148                                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 149                                 #interrupt-cells = <1>;
 150                                 interrupt-controller;
 151                                 msi-controller;
 152                         };
 153
 154                         xor@400000 {
 155                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 156                                 reg = <0x400000 0x1000>,
 157                                       <0x410000 0x1000>;
 158                                 msi-parent = <&gic_v2m0>;
 159                                 clocks = <&ap_clk 3>;
 160                                 dma-coherent;
 161                         };
 162
 163                         xor@420000 {
 164                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 165                                 reg = <0x420000 0x1000>,
 166                                       <0x430000 0x1000>;
 167                                 msi-parent = <&gic_v2m0>;
 168                                 clocks = <&ap_clk 3>;
 169                                 dma-coherent;
 170                         };
 171
 172                         xor@440000 {
 173                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 174                                 reg = <0x440000 0x1000>,
 175                                       <0x450000 0x1000>;
 176                                 msi-parent = <&gic_v2m0>;
 177                                 clocks = <&ap_clk 3>;
 178                                 dma-coherent;
 179                         };
 180
 181                         xor@460000 {
 182                                 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
 183                                 reg = <0x460000 0x1000>,
 184                                       <0x470000 0x1000>;
 185                                 msi-parent = <&gic_v2m0>;
 186                                 clocks = <&ap_clk 3>;
 187                                 dma-coherent;
 188                         };
 189
 190                         spi0: spi@510600 {
 191                                 compatible = "marvell,armada-380-spi";
 192                                 reg = <0x510600 0x50>;
 193                                 #address-cells = <1>;
 194                                 #size-cells = <0>;
 195                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 196                                 clocks = <&ap_clk 3>;
 197                                 status = "disabled";
 198                         };
 199
 200                         i2c0: i2c@511000 {
 201                                 compatible = "marvell,mv78230-i2c";
 202                                 reg = <0x511000 0x20>;
 203                                 #address-cells = <1>;
 204                                 #size-cells = <0>;
 205                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 206                                 timeout-ms = <1000>;
 207                                 clocks = <&ap_clk 3>;
 208                                 status = "disabled";
 209                         };
 210
 211                         uart0: serial@512000 {
 212                                 compatible = "snps,dw-apb-uart";
 213                                 reg = <0x512000 0x100>;
 214                                 reg-shift = <2>;
 215                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 216                                 reg-io-width = <1>;
 217                                 clocks = <&ap_clk 3>;
 218                                 status = "disabled";
 219                         };
 220
 221                         uart1: serial@512100 {
 222                                 compatible = "snps,dw-apb-uart";
 223                                 reg = <0x512100 0x100>;
 224                                 reg-shift = <2>;
 225                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 226                                 reg-io-width = <1>;
 227                                 clocks = <&ap_clk 3>;
 228                                 status = "disabled";
 229
 230                         };
 231
 232                         watchdog: watchdog@610000 {
 233                                 compatible = "arm,sbsa-gwdt";
 234                                 reg = <0x610000 0x1000>, <0x600000 0x1000>;
 235                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 236                         };
 237
 238                         ap_sdhci0: sdhci@6e0000 {
 239                                 compatible = "marvell,armada-ap806-sdhci";
 240                                 reg = <0x6e0000 0x300>;
 241                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 242                                 clock-names = "core";
 243                                 clocks = <&ap_clk 4>;
 244                                 dma-coherent;
 245                                 marvell,xenon-phy-slow-mode;
 246                                 status = "disabled";
 247                         };
 248
 249                         ap_syscon: system-controller@6f4000 {
 250                                 compatible = "syscon", "simple-mfd";
 251                                 reg = <0x6f4000 0x2000>;
 252
 253                                 ap_clk: clock {
 254                                         compatible = "marvell,ap806-clock";
 255                                         #clock-cells = <1>;
 256                                 };
 257
 258                                 ap_pinctrl: pinctrl {
 259                                         compatible = "marvell,ap806-pinctrl";
 260
 261                                         uart0_pins: uart0-pins {
 262                                                 marvell,pins = "mpp11", "mpp19";
 263                                                 marvell,function = "uart0";
 264                                         };
 265                                 };
 266
 267                                 ap_gpio: gpio@1040 {
 268                                         compatible = "marvell,armada-8k-gpio";
 269                                         offset = <0x1040>;
 270                                         ngpios = <20>;
 271                                         gpio-controller;
 272                                         #gpio-cells = <2>;
 273                                         gpio-ranges = <&ap_pinctrl 0 0 20>;
 274                                 };
 275                         };
 276
 277                         ap_syscon1: system-controller@6f8000 {
 278                                 compatible = "syscon", "simple-mfd";
 279                                 reg = <0x6f8000 0x1000>;
 280                                 #address-cells = <1>;
 281                                 #size-cells = <1>;
 282
 283                                 ap_thermal: thermal-sensor@80 {
 284                                         compatible = "marvell,armada-ap806-thermal";
 285                                         reg = <0x80 0x10>;
 286                                         interrupt-parent = <&sei>;
 287                                         interrupts = <18>;
 288                                         #thermal-sensor-cells = <1>;
 289                                 };
 290                         };
 291                 };
 292         };
 293
 294         /*
 295          * The thermal IP features one internal sensor plus, if applicable, one
 296          * remote channel wired to one sensor per CPU.
 297          *
 298          * Only one thermal zone per AP/CP may trigger interrupts at a time, the
 299          * first one that will have a critical trip point will be chosen.
 300          *
 301          * The cooling maps are always empty as there are no cooling devices.
 302          */
 303         thermal-zones {
 304                 ap_thermal_ic: ap-thermal-ic {
 305                         polling-delay-passive = <0>; /* Interrupt driven */
 306                         polling-delay = <0>; /* Interrupt driven */
 307
 308                         thermal-sensors = <&ap_thermal 0>;
 309
 310                         trips {
 311                                 ap_crit: ap-crit {
 312                                         temperature = <100000>; /* mC degrees */
 313                                         hysteresis = <2000>; /* mC degrees */
 314                                         type = "critical";
 315                                 };
 316                         };
 317
 318                         cooling-maps { };
 319                 };
 320
 321                 ap_thermal_cpu1: ap-thermal-cpu1 {
 322                         polling-delay-passive = <1000>;
 323                         polling-delay = <1000>;
 324
 325                         thermal-sensors = <&ap_thermal 1>;
 326
 327                         trips { };
 328                         cooling-maps { };
 329                 };
 330
 331                 ap_thermal_cpu2: ap-thermal-cpu2 {
 332                         polling-delay-passive = <1000>;
 333                         polling-delay = <1000>;
 334
 335                         thermal-sensors = <&ap_thermal 2>;
 336
 337                         trips { };
 338                         cooling-maps { };
 339                 };
 340
 341                 ap_thermal_cpu3: ap-thermal-cpu3 {
 342                         polling-delay-passive = <1000>;
 343                         polling-delay = <1000>;
 344
 345                         thermal-sensors = <&ap_thermal 3>;
 346
 347                         trips { };
 348                         cooling-maps { };
 349                 };
 350
 351                 ap_thermal_cpu4: ap-thermal-cpu4 {
 352                         polling-delay-passive = <1000>;
 353                         polling-delay = <1000>;
 354
 355                         thermal-sensors = <&ap_thermal 4>;
 356
 357                         trips { };
 358                         cooling-maps { };
 359                 };
 360         };
 361 };