1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada AP806.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
14 model = "Marvell Armada AP806";
15 compatible = "marvell,armada-ap806";
27 compatible = "arm,psci-0.2";
34 compatible = "simple-bus";
35 interrupt-parent = <&gic>;
38 config-space@f0000000 {
41 compatible = "simple-bus";
42 ranges = <0x0 0x0 0xf0000000 0x1000000>;
44 gic: interrupt-controller@210000 {
45 compatible = "arm,gic-400";
46 #interrupt-cells = <3>;
51 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
52 reg = <0x210000 0x10000>,
57 gic_v2m0: v2m@280000 {
58 compatible = "arm,gic-v2m-frame";
60 reg = <0x280000 0x1000>;
61 arm,msi-base-spi = <160>;
62 arm,msi-num-spis = <32>;
64 gic_v2m1: v2m@290000 {
65 compatible = "arm,gic-v2m-frame";
67 reg = <0x290000 0x1000>;
68 arm,msi-base-spi = <192>;
69 arm,msi-num-spis = <32>;
71 gic_v2m2: v2m@2a0000 {
72 compatible = "arm,gic-v2m-frame";
74 reg = <0x2a0000 0x1000>;
75 arm,msi-base-spi = <224>;
76 arm,msi-num-spis = <32>;
78 gic_v2m3: v2m@2b0000 {
79 compatible = "arm,gic-v2m-frame";
81 reg = <0x2b0000 0x1000>;
82 arm,msi-base-spi = <256>;
83 arm,msi-num-spis = <32>;
88 compatible = "arm,armv8-timer";
89 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
91 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
96 compatible = "arm,cortex-a72-pmu";
97 interrupt-parent = <&pic>;
102 compatible = "marvell,odmi-controller";
103 interrupt-controller;
105 marvell,odmi-frames = <4>;
106 reg = <0x300000 0x4000>,
110 marvell,spi-base = <128>, <136>, <144>, <152>;
114 compatible = "marvell,ap806-gicp";
115 reg = <0x3f0040 0x10>;
116 marvell,spi-ranges = <64 64>, <288 64>;
120 pic: interrupt-controller@3f0100 {
121 compatible = "marvell,armada-8k-pic";
122 reg = <0x3f0100 0x10>;
123 #interrupt-cells = <1>;
124 interrupt-controller;
125 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
128 sei: interrupt-controller@3f0200 {
129 compatible = "marvell,ap806-sei";
130 reg = <0x3f0200 0x40>;
131 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
132 #interrupt-cells = <1>;
133 interrupt-controller;
138 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
139 reg = <0x400000 0x1000>,
141 msi-parent = <&gic_v2m0>;
142 clocks = <&ap_clk 3>;
147 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
148 reg = <0x420000 0x1000>,
150 msi-parent = <&gic_v2m0>;
151 clocks = <&ap_clk 3>;
156 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
157 reg = <0x440000 0x1000>,
159 msi-parent = <&gic_v2m0>;
160 clocks = <&ap_clk 3>;
165 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
166 reg = <0x460000 0x1000>,
168 msi-parent = <&gic_v2m0>;
169 clocks = <&ap_clk 3>;
174 compatible = "marvell,armada-380-spi";
175 reg = <0x510600 0x50>;
176 #address-cells = <1>;
178 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&ap_clk 3>;
184 compatible = "marvell,mv78230-i2c";
185 reg = <0x511000 0x20>;
186 #address-cells = <1>;
188 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&ap_clk 3>;
194 uart0: serial@512000 {
195 compatible = "snps,dw-apb-uart";
196 reg = <0x512000 0x100>;
198 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&ap_clk 3>;
204 uart1: serial@512100 {
205 compatible = "snps,dw-apb-uart";
206 reg = <0x512100 0x100>;
208 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&ap_clk 3>;
215 watchdog: watchdog@610000 {
216 compatible = "arm,sbsa-gwdt";
217 reg = <0x610000 0x1000>, <0x600000 0x1000>;
218 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
221 ap_sdhci0: sdhci@6e0000 {
222 compatible = "marvell,armada-ap806-sdhci";
223 reg = <0x6e0000 0x300>;
224 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
225 clock-names = "core";
226 clocks = <&ap_clk 4>;
228 marvell,xenon-phy-slow-mode;
232 ap_syscon: system-controller@6f4000 {
233 compatible = "syscon", "simple-mfd";
234 reg = <0x6f4000 0x2000>;
237 compatible = "marvell,ap806-clock";
241 ap_pinctrl: pinctrl {
242 compatible = "marvell,ap806-pinctrl";
244 uart0_pins: uart0-pins {
245 marvell,pins = "mpp11", "mpp19";
246 marvell,function = "uart0";
251 compatible = "marvell,armada-8k-gpio";
256 gpio-ranges = <&ap_pinctrl 0 0 20>;
260 ap_syscon1: system-controller@6f8000 {
261 compatible = "syscon", "simple-mfd";
262 reg = <0x6f8000 0x1000>;
263 #address-cells = <1>;
266 ap_thermal: thermal-sensor@80 {
267 compatible = "marvell,armada-ap806-thermal";
269 #thermal-sensor-cells = <1>;
276 * The thermal IP features one internal sensor plus, if applicable, one
277 * remote channel wired to one sensor per CPU.
279 * The cooling maps are always empty as there are no cooling devices.
282 ap_thermal_ic: ap-thermal-ic {
283 polling-delay-passive = <1000>;
284 polling-delay = <1000>;
286 thermal-sensors = <&ap_thermal 0>;
292 ap_thermal_cpu1: ap-thermal-cpu1 {
293 polling-delay-passive = <1000>;
294 polling-delay = <1000>;
296 thermal-sensors = <&ap_thermal 1>;
302 ap_thermal_cpu2: ap-thermal-cpu2 {
303 polling-delay-passive = <1000>;
304 polling-delay = <1000>;
306 thermal-sensors = <&ap_thermal 2>;
312 ap_thermal_cpu3: ap-thermal-cpu3 {
313 polling-delay-passive = <1000>;
314 polling-delay = <1000>;
316 thermal-sensors = <&ap_thermal 3>;
322 ap_thermal_cpu4: ap-thermal-cpu4 {
323 polling-delay-passive = <1000>;
324 polling-delay = <1000>;
326 thermal-sensors = <&ap_thermal 4>;