1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada AP806.
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
14 model = "Marvell Armada AP806";
15 compatible = "marvell,armada-ap806";
27 compatible = "arm,psci-0.2";
36 entry_method = "arm,pcsi";
38 CPU_SLEEP_0: cpu-sleep-0 {
39 compatible = "arm,idle-state";
41 arm,psci-suspend-param = <0x0010000>;
42 entry-latency-us = <80>;
43 exit-latency-us = <160>;
44 min-residency-us = <320>;
47 CLUSTER_SLEEP_0: cluster-sleep-0 {
48 compatible = "arm,idle-state";
50 arm,psci-suspend-param = <0x1010000>;
51 entry-latency-us = <500>;
52 exit-latency-us = <1000>;
53 min-residency-us = <2500>;
61 compatible = "simple-bus";
62 interrupt-parent = <&gic>;
65 config-space@f0000000 {
68 compatible = "simple-bus";
69 ranges = <0x0 0x0 0xf0000000 0x1000000>;
71 gic: interrupt-controller@210000 {
72 compatible = "arm,gic-400";
73 #interrupt-cells = <3>;
78 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
79 reg = <0x210000 0x10000>,
84 gic_v2m0: v2m@280000 {
85 compatible = "arm,gic-v2m-frame";
87 reg = <0x280000 0x1000>;
88 arm,msi-base-spi = <160>;
89 arm,msi-num-spis = <32>;
91 gic_v2m1: v2m@290000 {
92 compatible = "arm,gic-v2m-frame";
94 reg = <0x290000 0x1000>;
95 arm,msi-base-spi = <192>;
96 arm,msi-num-spis = <32>;
98 gic_v2m2: v2m@2a0000 {
99 compatible = "arm,gic-v2m-frame";
101 reg = <0x2a0000 0x1000>;
102 arm,msi-base-spi = <224>;
103 arm,msi-num-spis = <32>;
105 gic_v2m3: v2m@2b0000 {
106 compatible = "arm,gic-v2m-frame";
108 reg = <0x2b0000 0x1000>;
109 arm,msi-base-spi = <256>;
110 arm,msi-num-spis = <32>;
115 compatible = "arm,armv8-timer";
116 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
123 compatible = "arm,cortex-a72-pmu";
124 interrupt-parent = <&pic>;
129 compatible = "marvell,odmi-controller";
130 interrupt-controller;
132 marvell,odmi-frames = <4>;
133 reg = <0x300000 0x4000>,
137 marvell,spi-base = <128>, <136>, <144>, <152>;
141 compatible = "marvell,ap806-gicp";
142 reg = <0x3f0040 0x10>;
143 marvell,spi-ranges = <64 64>, <288 64>;
147 pic: interrupt-controller@3f0100 {
148 compatible = "marvell,armada-8k-pic";
149 reg = <0x3f0100 0x10>;
150 #interrupt-cells = <1>;
151 interrupt-controller;
152 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
155 sei: interrupt-controller@3f0200 {
156 compatible = "marvell,ap806-sei";
157 reg = <0x3f0200 0x40>;
158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
159 #interrupt-cells = <1>;
160 interrupt-controller;
165 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
166 reg = <0x400000 0x1000>,
168 msi-parent = <&gic_v2m0>;
169 clocks = <&ap_clk 3>;
174 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
175 reg = <0x420000 0x1000>,
177 msi-parent = <&gic_v2m0>;
178 clocks = <&ap_clk 3>;
183 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
184 reg = <0x440000 0x1000>,
186 msi-parent = <&gic_v2m0>;
187 clocks = <&ap_clk 3>;
192 compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
193 reg = <0x460000 0x1000>,
195 msi-parent = <&gic_v2m0>;
196 clocks = <&ap_clk 3>;
201 compatible = "marvell,armada-380-spi";
202 reg = <0x510600 0x50>;
203 #address-cells = <1>;
205 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&ap_clk 3>;
211 compatible = "marvell,mv78230-i2c";
212 reg = <0x511000 0x20>;
213 #address-cells = <1>;
215 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&ap_clk 3>;
221 uart0: serial@512000 {
222 compatible = "snps,dw-apb-uart";
223 reg = <0x512000 0x100>;
225 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&ap_clk 3>;
231 uart1: serial@512100 {
232 compatible = "snps,dw-apb-uart";
233 reg = <0x512100 0x100>;
235 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&ap_clk 3>;
242 watchdog: watchdog@610000 {
243 compatible = "arm,sbsa-gwdt";
244 reg = <0x610000 0x1000>, <0x600000 0x1000>;
245 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
248 ap_sdhci0: sdhci@6e0000 {
249 compatible = "marvell,armada-ap806-sdhci";
250 reg = <0x6e0000 0x300>;
251 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
252 clock-names = "core";
253 clocks = <&ap_clk 4>;
255 marvell,xenon-phy-slow-mode;
259 ap_syscon: system-controller@6f4000 {
260 compatible = "syscon", "simple-mfd";
261 reg = <0x6f4000 0x2000>;
264 compatible = "marvell,ap806-clock";
268 ap_pinctrl: pinctrl {
269 compatible = "marvell,ap806-pinctrl";
271 uart0_pins: uart0-pins {
272 marvell,pins = "mpp11", "mpp19";
273 marvell,function = "uart0";
278 compatible = "marvell,armada-8k-gpio";
283 gpio-ranges = <&ap_pinctrl 0 0 20>;
287 ap_syscon1: system-controller@6f8000 {
288 compatible = "syscon", "simple-mfd";
289 reg = <0x6f8000 0x1000>;
290 #address-cells = <1>;
293 ap_thermal: thermal-sensor@80 {
294 compatible = "marvell,armada-ap806-thermal";
296 #thermal-sensor-cells = <1>;
303 * The thermal IP features one internal sensor plus, if applicable, one
304 * remote channel wired to one sensor per CPU.
306 * The cooling maps are always empty as there are no cooling devices.
309 ap_thermal_ic: ap-thermal-ic {
310 polling-delay-passive = <1000>;
311 polling-delay = <1000>;
313 thermal-sensors = <&ap_thermal 0>;
319 ap_thermal_cpu1: ap-thermal-cpu1 {
320 polling-delay-passive = <1000>;
321 polling-delay = <1000>;
323 thermal-sensors = <&ap_thermal 1>;
329 ap_thermal_cpu2: ap-thermal-cpu2 {
330 polling-delay-passive = <1000>;
331 polling-delay = <1000>;
333 thermal-sensors = <&ap_thermal 2>;
339 ap_thermal_cpu3: ap-thermal-cpu3 {
340 polling-delay-passive = <1000>;
341 polling-delay = <1000>;
343 thermal-sensors = <&ap_thermal 3>;
349 ap_thermal_cpu4: ap-thermal-cpu4 {
350 polling-delay-passive = <1000>;
351 polling-delay = <1000>;
353 thermal-sensors = <&ap_thermal 4>;