1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2016 Marvell Technology Group Ltd.
5 * Device Tree file for Marvell Armada 7040 Development board platform
8 #include <dt-bindings/gpio/gpio.h>
9 #include "armada-7040.dtsi"
12 model = "Marvell Armada 7040 DB board";
13 compatible = "marvell,armada7040-db", "marvell,armada7040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
17 stdout-path = "serial0:115200n8";
21 device_type = "memory";
22 reg = <0x0 0x0 0x0 0x80000000>;
26 ethernet0 = &cp0_eth0;
27 ethernet1 = &cp0_eth1;
28 ethernet2 = &cp0_eth2;
31 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
32 compatible = "regulator-fixed";
33 regulator-name = "usb3h0-vbus";
34 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <5000000>;
37 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
40 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
41 compatible = "regulator-fixed";
42 regulator-name = "usb3h1-vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
46 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
49 cp0_usb3_0_phy: cp0-usb3-0-phy {
50 compatible = "usb-nop-xceiv";
51 vcc-supply = <&cp0_reg_usb3_0_vbus>;
54 cp0_usb3_1_phy: cp0-usb3-1-phy {
55 compatible = "usb-nop-xceiv";
56 vcc-supply = <&cp0_reg_usb3_1_vbus>;
62 clock-frequency = <100000>;
69 compatible = "jedec,spi-nor";
71 spi-max-frequency = <10000000>;
74 compatible = "fixed-partitions";
84 reg = <0x200000 0xce0000>;
92 pinctrl-0 = <&uart0_pins>;
93 pinctrl-names = "default";
103 clock-frequency = <100000>;
105 expander0: pca9555@21 {
106 compatible = "nxp,pca9555";
107 pinctrl-names = "default";
112 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect
113 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit
114 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
115 * IO0_3: USB2_DEVICE_DETECT
116 * IO0_4: GPIO_0 IO1_4: SD_Status
117 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable
118 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
119 * IO0_7: IO1_7: SDIO_Vcntrl
124 &cp0_nand_controller {
126 * SPI on CPM and NAND have common pins on this board. We can
127 * use only one at a time. To enable the NAND (which will
128 * disable the SPI), the "status = "okay";" line have to be
131 pinctrl-0 = <&nand_pins>, <&nand_rb>;
132 pinctrl-names = "default";
136 label = "pxa3xx_nand-0";
139 nand-ecc-strength = <4>;
140 nand-ecc-step-size = <512>;
143 compatible = "fixed-partitions";
144 #address-cells = <1>;
154 reg = <0x200000 0xe00000>;
158 label = "Filesystem";
159 reg = <0x1000000 0x3f000000>;
170 compatible = "jedec,spi-nor";
172 spi-max-frequency = <20000000>;
175 compatible = "fixed-partitions";
176 #address-cells = <1>;
181 reg = <0x0 0x200000>;
185 label = "Filesystem";
186 reg = <0x200000 0xe00000>;
197 usb-phy = <&cp0_usb3_0_phy>;
202 usb-phy = <&cp0_usb3_1_phy>;
217 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
223 phy0: ethernet-phy@0 {
226 phy1: ethernet-phy@1 {
238 phy-mode = "10gbase-kr";
239 /* Generic PHY, providing serdes lanes */
240 phys = <&cp0_comphy2 0>;
253 /* Generic PHY, providing serdes lanes */
254 phys = <&cp0_comphy0 1>;
260 phy-mode = "rgmii-id";