2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 * Copyright (C) 2016 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
13 * a) This file is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
18 * This file is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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47 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 model = "Marvell Armada 37xx SoC";
51 compatible = "marvell,armada3700";
52 interrupt-parent = <&gic>;
66 compatible = "arm,cortex-a53", "arm,armv8";
68 enable-method = "psci";
73 compatible = "arm,psci-0.2";
78 compatible = "arm,armv8-timer";
79 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
86 compatible = "arm,armv8-pmuv3";
87 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
91 compatible = "simple-bus";
96 internal-regs@d0000000 {
99 compatible = "simple-bus";
100 /* 32M internal register @ 0xd000_0000 */
101 ranges = <0x0 0x0 0xd0000000 0x2000000>;
104 compatible = "marvell,armada-3700-spi";
105 #address-cells = <1>;
107 reg = <0x10600 0xA00>;
108 clocks = <&nb_periph_clk 7>;
109 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
115 compatible = "marvell,armada-3700-i2c";
116 reg = <0x11000 0x24>;
117 #address-cells = <1>;
119 clocks = <&nb_periph_clk 10>;
120 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
126 compatible = "marvell,armada-3700-i2c";
127 reg = <0x11080 0x24>;
128 #address-cells = <1>;
130 clocks = <&nb_periph_clk 9>;
131 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
136 uart0: serial@12000 {
137 compatible = "marvell,armada-3700-uart";
138 reg = <0x12000 0x200>;
141 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
144 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
148 uart1: serial@12200 {
149 compatible = "marvell,armada-3700-uart-ext";
150 reg = <0x12200 0x30>;
153 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
154 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
155 interrupt-names = "uart-tx", "uart-rx";
159 nb_periph_clk: nb-periph-clk@13000 {
160 compatible = "marvell,armada-3700-periph-clock-nb";
161 reg = <0x13000 0x100>;
162 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
163 <&tbg 3>, <&xtalclk>;
167 sb_periph_clk: sb-periph-clk@18000 {
168 compatible = "marvell,armada-3700-periph-clock-sb";
169 reg = <0x18000 0x100>;
170 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
171 <&tbg 3>, <&xtalclk>;
176 compatible = "marvell,armada-3700-tbg-clock";
177 reg = <0x13200 0x100>;
182 pinctrl_nb: pinctrl@13800 {
183 compatible = "marvell,armada3710-nb-pinctrl",
184 "syscon", "simple-mfd";
185 reg = <0x13800 0x100>, <0x13C00 0x20>;
188 gpio-ranges = <&pinctrl_nb 0 0 36>;
191 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
206 compatible = "marvell,armada-3700-xtal-clock";
207 clock-output-names = "xtal";
211 spi_quad_pins: spi-quad-pins {
216 i2c1_pins: i2c1-pins {
221 i2c2_pins: i2c2-pins {
226 uart1_pins: uart1-pins {
231 uart2_pins: uart2-pins {
237 pinctrl_sb: pinctrl@18800 {
238 compatible = "marvell,armada3710-sb-pinctrl",
239 "syscon", "simple-mfd";
240 reg = <0x18800 0x100>, <0x18C00 0x20>;
243 gpio-ranges = <&pinctrl_sb 0 0 30>;
246 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
253 rgmii_pins: mii-pins {
260 eth0: ethernet@30000 {
261 compatible = "marvell,armada-3700-neta";
262 reg = <0x30000 0x4000>;
263 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&sb_periph_clk 8>;
269 #address-cells = <1>;
271 compatible = "marvell,orion-mdio";
275 eth1: ethernet@40000 {
276 compatible = "marvell,armada-3700-neta";
277 reg = <0x40000 0x4000>;
278 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&sb_periph_clk 7>;
284 compatible = "marvell,armada3700-xhci",
286 reg = <0x58000 0x4000>;
287 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&sb_periph_clk 12>;
293 compatible = "marvell,armada-3700-ehci";
294 reg = <0x5e000 0x2000>;
295 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
300 compatible = "marvell,armada-3700-xor";
301 reg = <0x60900 0x100>,
305 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
308 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
312 sdhci1: sdhci@d0000 {
313 compatible = "marvell,armada-3700-sdhci",
314 "marvell,sdhci-xenon";
315 reg = <0xd0000 0x300>,
317 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&nb_periph_clk 0>;
319 clock-names = "core";
323 sdhci0: sdhci@d8000 {
324 compatible = "marvell,armada-3700-sdhci",
325 "marvell,sdhci-xenon";
326 reg = <0xd8000 0x300>,
328 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&nb_periph_clk 0>;
330 clock-names = "core";
335 compatible = "marvell,armada-3700-ahci";
336 reg = <0xe0000 0x2000>;
337 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
341 gic: interrupt-controller@1d00000 {
342 compatible = "arm,gic-v3";
343 #interrupt-cells = <3>;
344 interrupt-controller;
345 reg = <0x1d00000 0x10000>, /* GICD */
346 <0x1d40000 0x40000>, /* GICR */
347 <0x1d80000 0x2000>, /* GICC */
348 <0x1d90000 0x2000>, /* GICH */
349 <0x1da0000 0x20000>; /* GICV */
350 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
354 pcie0: pcie@d0070000 {
355 compatible = "marvell,armada-3700-pcie";
358 reg = <0 0xd0070000 0 0x20000>;
359 #address-cells = <3>;
361 bus-range = <0x00 0xff>;
362 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
363 #interrupt-cells = <1>;
364 msi-parent = <&pcie0>;
366 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
367 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
368 interrupt-map-mask = <0 0 0 7>;
369 interrupt-map = <0 0 0 1 &pcie_intc 0>,
370 <0 0 0 2 &pcie_intc 1>,
371 <0 0 0 3 &pcie_intc 2>,
372 <0 0 0 4 &pcie_intc 3>;
373 pcie_intc: interrupt-controller {
374 interrupt-controller;
375 #interrupt-cells = <1>;