1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
5 * Copyright (C) 2016 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
30 compatible = "arm,cortex-a53", "arm,armv8";
32 clocks = <&nb_periph_clk 16>;
33 enable-method = "psci";
38 compatible = "arm,psci-0.2";
43 compatible = "arm,armv8-timer";
44 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
51 compatible = "arm,armv8-pmuv3";
52 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
56 compatible = "simple-bus";
61 internal-regs@d0000000 {
64 compatible = "simple-bus";
65 /* 32M internal register @ 0xd000_0000 */
66 ranges = <0x0 0x0 0xd0000000 0x2000000>;
69 compatible = "marvell,armada-3700-spi";
72 reg = <0x10600 0xA00>;
73 clocks = <&nb_periph_clk 7>;
74 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
80 compatible = "marvell,armada-3700-i2c";
84 clocks = <&nb_periph_clk 10>;
85 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
91 compatible = "marvell,armada-3700-i2c";
95 clocks = <&nb_periph_clk 9>;
96 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
101 uart0: serial@12000 {
102 compatible = "marvell,armada-3700-uart";
103 reg = <0x12000 0x200>;
106 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
109 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
113 uart1: serial@12200 {
114 compatible = "marvell,armada-3700-uart-ext";
115 reg = <0x12200 0x30>;
118 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
119 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
120 interrupt-names = "uart-tx", "uart-rx";
124 nb_periph_clk: nb-periph-clk@13000 {
125 compatible = "marvell,armada-3700-periph-clock-nb";
126 reg = <0x13000 0x100>;
127 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
128 <&tbg 3>, <&xtalclk>;
132 sb_periph_clk: sb-periph-clk@18000 {
133 compatible = "marvell,armada-3700-periph-clock-sb";
134 reg = <0x18000 0x100>;
135 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
136 <&tbg 3>, <&xtalclk>;
141 compatible = "marvell,armada-3700-tbg-clock";
142 reg = <0x13200 0x100>;
147 pinctrl_nb: pinctrl@13800 {
148 compatible = "marvell,armada3710-nb-pinctrl",
149 "syscon", "simple-mfd";
150 reg = <0x13800 0x100>, <0x13C00 0x20>;
154 gpio-ranges = <&pinctrl_nb 0 0 36>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
159 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
174 compatible = "marvell,armada-3700-xtal-clock";
175 clock-output-names = "xtal";
179 spi_quad_pins: spi-quad-pins {
184 i2c1_pins: i2c1-pins {
189 i2c2_pins: i2c2-pins {
194 uart1_pins: uart1-pins {
199 uart2_pins: uart2-pins {
205 nb_pm: syscon@14000 {
206 compatible = "marvell,armada-3700-nb-pm",
208 reg = <0x14000 0x60>;
211 pinctrl_sb: pinctrl@18800 {
212 compatible = "marvell,armada3710-sb-pinctrl",
213 "syscon", "simple-mfd";
214 reg = <0x18800 0x100>, <0x18C00 0x20>;
218 gpio-ranges = <&pinctrl_sb 0 0 30>;
220 interrupt-controller;
221 #interrupt-cells = <2>;
223 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
230 rgmii_pins: mii-pins {
237 eth0: ethernet@30000 {
238 compatible = "marvell,armada-3700-neta";
239 reg = <0x30000 0x4000>;
240 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&sb_periph_clk 8>;
246 #address-cells = <1>;
248 compatible = "marvell,orion-mdio";
252 eth1: ethernet@40000 {
253 compatible = "marvell,armada-3700-neta";
254 reg = <0x40000 0x4000>;
255 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&sb_periph_clk 7>;
261 compatible = "marvell,armada3700-xhci",
263 reg = <0x58000 0x4000>;
264 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&sb_periph_clk 12>;
270 compatible = "marvell,armada-3700-ehci";
271 reg = <0x5e000 0x2000>;
272 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
277 compatible = "marvell,armada-3700-xor";
278 reg = <0x60900 0x100>,
282 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
285 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
289 crypto: crypto@90000 {
290 compatible = "inside-secure,safexcel-eip97";
291 reg = <0x90000 0x20000>;
292 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
298 interrupt-names = "mem", "ring0", "ring1",
299 "ring2", "ring3", "eip";
300 clocks = <&nb_periph_clk 15>;
303 sdhci1: sdhci@d0000 {
304 compatible = "marvell,armada-3700-sdhci",
305 "marvell,sdhci-xenon";
306 reg = <0xd0000 0x300>,
308 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&nb_periph_clk 0>;
310 clock-names = "core";
314 sdhci0: sdhci@d8000 {
315 compatible = "marvell,armada-3700-sdhci",
316 "marvell,sdhci-xenon";
317 reg = <0xd8000 0x300>,
319 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&nb_periph_clk 0>;
321 clock-names = "core";
326 compatible = "marvell,armada-3700-ahci";
327 reg = <0xe0000 0x2000>;
328 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
332 gic: interrupt-controller@1d00000 {
333 compatible = "arm,gic-v3";
334 #interrupt-cells = <3>;
335 interrupt-controller;
336 reg = <0x1d00000 0x10000>, /* GICD */
337 <0x1d40000 0x40000>, /* GICR */
338 <0x1d80000 0x2000>, /* GICC */
339 <0x1d90000 0x2000>, /* GICH */
340 <0x1da0000 0x20000>; /* GICV */
341 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
345 pcie0: pcie@d0070000 {
346 compatible = "marvell,armada-3700-pcie";
349 reg = <0 0xd0070000 0 0x20000>;
350 #address-cells = <3>;
352 bus-range = <0x00 0xff>;
353 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
354 #interrupt-cells = <1>;
355 msi-parent = <&pcie0>;
357 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
358 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
359 interrupt-map-mask = <0 0 0 7>;
360 interrupt-map = <0 0 0 1 &pcie_intc 0>,
361 <0 0 0 2 &pcie_intc 1>,
362 <0 0 0 3 &pcie_intc 2>,
363 <0 0 0 4 &pcie_intc 3>;
364 pcie_intc: interrupt-controller {
365 interrupt-controller;
366 #interrupt-cells = <1>;