2 * dts file for Hisilicon Hi6220 SoC
4 * Copyright (C) 2015, Hisilicon Ltd.
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/reset/hisi,hi6220-resets.h>
9 #include <dt-bindings/clock/hi6220-clock.h>
10 #include <dt-bindings/pinctrl/hisi.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "hisilicon,hi6220";
15 interrupt-parent = <&gic>;
20 compatible = "arm,psci-0.2";
60 entry-method = "psci";
62 CPU_SLEEP: cpu-sleep {
63 compatible = "arm,idle-state";
65 arm,psci-suspend-param = <0x0010000>;
66 entry-latency-us = <700>;
67 exit-latency-us = <250>;
68 min-residency-us = <1000>;
71 CLUSTER_SLEEP: cluster-sleep {
72 compatible = "arm,idle-state";
74 arm,psci-suspend-param = <0x1010000>;
75 entry-latency-us = <1000>;
76 exit-latency-us = <700>;
77 min-residency-us = <2700>;
78 wakeup-latency-us = <1500>;
83 compatible = "arm,cortex-a53", "arm,armv8";
86 enable-method = "psci";
87 next-level-cache = <&CLUSTER0_L2>;
88 clocks = <&stub_clock 0>;
89 operating-points-v2 = <&cpu_opp_table>;
90 cooling-min-level = <4>;
91 cooling-max-level = <0>;
92 #cooling-cells = <2>; /* min followed by max */
93 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
94 dynamic-power-coefficient = <311>;
98 compatible = "arm,cortex-a53", "arm,armv8";
101 enable-method = "psci";
102 next-level-cache = <&CLUSTER0_L2>;
103 operating-points-v2 = <&cpu_opp_table>;
104 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
108 compatible = "arm,cortex-a53", "arm,armv8";
111 enable-method = "psci";
112 next-level-cache = <&CLUSTER0_L2>;
113 operating-points-v2 = <&cpu_opp_table>;
114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
118 compatible = "arm,cortex-a53", "arm,armv8";
121 enable-method = "psci";
122 next-level-cache = <&CLUSTER0_L2>;
123 operating-points-v2 = <&cpu_opp_table>;
124 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
128 compatible = "arm,cortex-a53", "arm,armv8";
131 enable-method = "psci";
132 next-level-cache = <&CLUSTER1_L2>;
133 operating-points-v2 = <&cpu_opp_table>;
134 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
138 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 next-level-cache = <&CLUSTER1_L2>;
143 operating-points-v2 = <&cpu_opp_table>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
148 compatible = "arm,cortex-a53", "arm,armv8";
151 enable-method = "psci";
152 next-level-cache = <&CLUSTER1_L2>;
153 operating-points-v2 = <&cpu_opp_table>;
154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
158 compatible = "arm,cortex-a53", "arm,armv8";
161 enable-method = "psci";
162 next-level-cache = <&CLUSTER1_L2>;
163 operating-points-v2 = <&cpu_opp_table>;
164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
167 CLUSTER0_L2: l2-cache0 {
168 compatible = "cache";
171 CLUSTER1_L2: l2-cache1 {
172 compatible = "cache";
176 cpu_opp_table: cpu_opp_table {
177 compatible = "operating-points-v2";
181 opp-hz = /bits/ 64 <208000000>;
182 opp-microvolt = <1040000>;
183 clock-latency-ns = <500000>;
186 opp-hz = /bits/ 64 <432000000>;
187 opp-microvolt = <1040000>;
188 clock-latency-ns = <500000>;
191 opp-hz = /bits/ 64 <729000000>;
192 opp-microvolt = <1090000>;
193 clock-latency-ns = <500000>;
196 opp-hz = /bits/ 64 <960000000>;
197 opp-microvolt = <1180000>;
198 clock-latency-ns = <500000>;
201 opp-hz = /bits/ 64 <1200000000>;
202 opp-microvolt = <1330000>;
203 clock-latency-ns = <500000>;
207 gic: interrupt-controller@f6801000 {
208 compatible = "arm,gic-400";
209 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
210 <0x0 0xf6802000 0 0x2000>, /* GICC */
211 <0x0 0xf6804000 0 0x2000>, /* GICH */
212 <0x0 0xf6806000 0 0x2000>; /* GICV */
213 #address-cells = <0>;
214 #interrupt-cells = <3>;
215 interrupt-controller;
216 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
220 compatible = "arm,armv8-timer";
221 interrupt-parent = <&gic>;
222 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
223 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
224 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
225 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
229 compatible = "simple-bus";
230 #address-cells = <2>;
234 sram: sram@fff80000 {
235 compatible = "hisilicon,hi6220-sramctrl", "syscon";
236 reg = <0x0 0xfff80000 0x0 0x12000>;
239 ao_ctrl: ao_ctrl@f7800000 {
240 compatible = "hisilicon,hi6220-aoctrl", "syscon";
241 reg = <0x0 0xf7800000 0x0 0x2000>;
245 sys_ctrl: sys_ctrl@f7030000 {
246 compatible = "hisilicon,hi6220-sysctrl", "syscon";
247 reg = <0x0 0xf7030000 0x0 0x2000>;
252 media_ctrl: media_ctrl@f4410000 {
253 compatible = "hisilicon,hi6220-mediactrl", "syscon";
254 reg = <0x0 0xf4410000 0x0 0x1000>;
259 pm_ctrl: pm_ctrl@f7032000 {
260 compatible = "hisilicon,hi6220-pmctrl", "syscon";
261 reg = <0x0 0xf7032000 0x0 0x1000>;
265 medianoc_ade: medianoc_ade@f4520000 {
266 compatible = "syscon";
267 reg = <0x0 0xf4520000 0x0 0x4000>;
270 stub_clock: stub_clock {
271 compatible = "hisilicon,hi6220-stub-clk";
272 hisilicon,hi6220-clk-sram = <&sram>;
274 mbox-names = "mbox-tx";
275 mboxes = <&mailbox 1 0 11>;
278 uart0: uart@f8015000 { /* console */
279 compatible = "arm,pl011", "arm,primecell";
280 reg = <0x0 0xf8015000 0x0 0x1000>;
281 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
282 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
283 <&ao_ctrl HI6220_UART0_PCLK>;
284 clock-names = "uartclk", "apb_pclk";
287 uart1: uart@f7111000 {
288 compatible = "arm,pl011", "arm,primecell";
289 reg = <0x0 0xf7111000 0x0 0x1000>;
290 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
292 <&sys_ctrl HI6220_UART1_PCLK>;
293 clock-names = "uartclk", "apb_pclk";
294 pinctrl-names = "default";
295 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
299 uart2: uart@f7112000 {
300 compatible = "arm,pl011", "arm,primecell";
301 reg = <0x0 0xf7112000 0x0 0x1000>;
302 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
304 <&sys_ctrl HI6220_UART2_PCLK>;
305 clock-names = "uartclk", "apb_pclk";
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
311 uart3: uart@f7113000 {
312 compatible = "arm,pl011", "arm,primecell";
313 reg = <0x0 0xf7113000 0x0 0x1000>;
314 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
316 <&sys_ctrl HI6220_UART3_PCLK>;
317 clock-names = "uartclk", "apb_pclk";
318 pinctrl-names = "default";
319 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
323 uart4: uart@f7114000 {
324 compatible = "arm,pl011", "arm,primecell";
325 reg = <0x0 0xf7114000 0x0 0x1000>;
326 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
328 <&sys_ctrl HI6220_UART4_PCLK>;
329 clock-names = "uartclk", "apb_pclk";
330 pinctrl-names = "default";
331 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
336 compatible = "hisilicon,k3-dma-1.0";
337 reg = <0x0 0xf7370000 0x0 0x1000>;
341 interrupts = <0 84 4>;
342 clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
344 dma-type = "hi6220_dma";
348 dual_timer0: timer@f8008000 {
349 compatible = "arm,sp804", "arm,primecell";
350 reg = <0x0 0xf8008000 0x0 0x1000>;
351 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
354 <&ao_ctrl HI6220_TIMER0_PCLK>,
355 <&ao_ctrl HI6220_TIMER0_PCLK>;
356 clock-names = "timer1", "timer2", "apb_pclk";
360 compatible = "arm,pl031", "arm,primecell";
361 reg = <0x0 0xf8003000 0x0 0x1000>;
362 interrupts = <0 12 4>;
363 clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
364 clock-names = "apb_pclk";
368 compatible = "arm,pl031", "arm,primecell";
369 reg = <0x0 0xf8004000 0x0 0x1000>;
370 interrupts = <0 8 4>;
371 clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
372 clock-names = "apb_pclk";
375 pmx0: pinmux@f7010000 {
376 compatible = "pinctrl-single";
377 reg = <0x0 0xf7010000 0x0 0x27c>;
378 #address-cells = <1>;
380 #pinctrl-cells = <1>;
381 #gpio-range-cells = <3>;
382 pinctrl-single,register-width = <32>;
383 pinctrl-single,function-mask = <7>;
384 pinctrl-single,gpio-range = <
385 &range 80 8 MUX_M0 /* gpio 3: [0..7] */
386 &range 88 8 MUX_M0 /* gpio 4: [0..7] */
387 &range 96 8 MUX_M0 /* gpio 5: [0..7] */
388 &range 104 8 MUX_M0 /* gpio 6: [0..7] */
389 &range 112 8 MUX_M0 /* gpio 7: [0..7] */
390 &range 120 2 MUX_M0 /* gpio 8: [0..1] */
391 &range 2 6 MUX_M1 /* gpio 8: [2..7] */
392 &range 8 8 MUX_M1 /* gpio 9: [0..7] */
393 &range 0 1 MUX_M1 /* gpio 10: [0] */
394 &range 16 7 MUX_M1 /* gpio 10: [1..7] */
395 &range 23 3 MUX_M1 /* gpio 11: [0..2] */
396 &range 28 5 MUX_M1 /* gpio 11: [3..7] */
397 &range 33 3 MUX_M1 /* gpio 12: [0..2] */
398 &range 43 5 MUX_M1 /* gpio 12: [3..7] */
399 &range 48 8 MUX_M1 /* gpio 13: [0..7] */
400 &range 56 8 MUX_M1 /* gpio 14: [0..7] */
401 &range 74 6 MUX_M1 /* gpio 15: [0..5] */
402 &range 122 1 MUX_M1 /* gpio 15: [6] */
403 &range 126 1 MUX_M1 /* gpio 15: [7] */
404 &range 127 8 MUX_M1 /* gpio 16: [0..7] */
405 &range 135 8 MUX_M1 /* gpio 17: [0..7] */
406 &range 143 8 MUX_M1 /* gpio 18: [0..7] */
407 &range 151 8 MUX_M1 /* gpio 19: [0..7] */
410 #pinctrl-single,gpio-range-cells = <3>;
414 pmx1: pinmux@f7010800 {
415 compatible = "pinconf-single";
416 reg = <0x0 0xf7010800 0x0 0x28c>;
417 #address-cells = <1>;
419 #pinctrl-cells = <1>;
420 pinctrl-single,register-width = <32>;
423 pmx2: pinmux@f8001800 {
424 compatible = "pinconf-single";
425 reg = <0x0 0xf8001800 0x0 0x78>;
426 #address-cells = <1>;
428 #pinctrl-cells = <1>;
429 pinctrl-single,register-width = <32>;
432 gpio0: gpio@f8011000 {
433 compatible = "arm,pl061", "arm,primecell";
434 reg = <0x0 0xf8011000 0x0 0x1000>;
435 interrupts = <0 52 0x4>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 clocks = <&ao_ctrl 2>;
441 clock-names = "apb_pclk";
444 gpio1: gpio@f8012000 {
445 compatible = "arm,pl061", "arm,primecell";
446 reg = <0x0 0xf8012000 0x0 0x1000>;
447 interrupts = <0 53 0x4>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 clocks = <&ao_ctrl 2>;
453 clock-names = "apb_pclk";
456 gpio2: gpio@f8013000 {
457 compatible = "arm,pl061", "arm,primecell";
458 reg = <0x0 0xf8013000 0x0 0x1000>;
459 interrupts = <0 54 0x4>;
462 interrupt-controller;
463 #interrupt-cells = <2>;
464 clocks = <&ao_ctrl 2>;
465 clock-names = "apb_pclk";
468 gpio3: gpio@f8014000 {
469 compatible = "arm,pl061", "arm,primecell";
470 reg = <0x0 0xf8014000 0x0 0x1000>;
471 interrupts = <0 55 0x4>;
474 gpio-ranges = <&pmx0 0 80 8>;
475 interrupt-controller;
476 #interrupt-cells = <2>;
477 clocks = <&ao_ctrl 2>;
478 clock-names = "apb_pclk";
481 gpio4: gpio@f7020000 {
482 compatible = "arm,pl061", "arm,primecell";
483 reg = <0x0 0xf7020000 0x0 0x1000>;
484 interrupts = <0 56 0x4>;
487 gpio-ranges = <&pmx0 0 88 8>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 clocks = <&ao_ctrl 2>;
491 clock-names = "apb_pclk";
494 gpio5: gpio@f7021000 {
495 compatible = "arm,pl061", "arm,primecell";
496 reg = <0x0 0xf7021000 0x0 0x1000>;
497 interrupts = <0 57 0x4>;
500 gpio-ranges = <&pmx0 0 96 8>;
501 interrupt-controller;
502 #interrupt-cells = <2>;
503 clocks = <&ao_ctrl 2>;
504 clock-names = "apb_pclk";
507 gpio6: gpio@f7022000 {
508 compatible = "arm,pl061", "arm,primecell";
509 reg = <0x0 0xf7022000 0x0 0x1000>;
510 interrupts = <0 58 0x4>;
513 gpio-ranges = <&pmx0 0 104 8>;
514 interrupt-controller;
515 #interrupt-cells = <2>;
516 clocks = <&ao_ctrl 2>;
517 clock-names = "apb_pclk";
520 gpio7: gpio@f7023000 {
521 compatible = "arm,pl061", "arm,primecell";
522 reg = <0x0 0xf7023000 0x0 0x1000>;
523 interrupts = <0 59 0x4>;
526 gpio-ranges = <&pmx0 0 112 8>;
527 interrupt-controller;
528 #interrupt-cells = <2>;
529 clocks = <&ao_ctrl 2>;
530 clock-names = "apb_pclk";
533 gpio8: gpio@f7024000 {
534 compatible = "arm,pl061", "arm,primecell";
535 reg = <0x0 0xf7024000 0x0 0x1000>;
536 interrupts = <0 60 0x4>;
539 gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
540 interrupt-controller;
541 #interrupt-cells = <2>;
542 clocks = <&ao_ctrl 2>;
543 clock-names = "apb_pclk";
546 gpio9: gpio@f7025000 {
547 compatible = "arm,pl061", "arm,primecell";
548 reg = <0x0 0xf7025000 0x0 0x1000>;
549 interrupts = <0 61 0x4>;
552 gpio-ranges = <&pmx0 0 8 8>;
553 interrupt-controller;
554 #interrupt-cells = <2>;
555 clocks = <&ao_ctrl 2>;
556 clock-names = "apb_pclk";
559 gpio10: gpio@f7026000 {
560 compatible = "arm,pl061", "arm,primecell";
561 reg = <0x0 0xf7026000 0x0 0x1000>;
562 interrupts = <0 62 0x4>;
565 gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
566 interrupt-controller;
567 #interrupt-cells = <2>;
568 clocks = <&ao_ctrl 2>;
569 clock-names = "apb_pclk";
572 gpio11: gpio@f7027000 {
573 compatible = "arm,pl061", "arm,primecell";
574 reg = <0x0 0xf7027000 0x0 0x1000>;
575 interrupts = <0 63 0x4>;
578 gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
579 interrupt-controller;
580 #interrupt-cells = <2>;
581 clocks = <&ao_ctrl 2>;
582 clock-names = "apb_pclk";
585 gpio12: gpio@f7028000 {
586 compatible = "arm,pl061", "arm,primecell";
587 reg = <0x0 0xf7028000 0x0 0x1000>;
588 interrupts = <0 64 0x4>;
591 gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
594 clocks = <&ao_ctrl 2>;
595 clock-names = "apb_pclk";
598 gpio13: gpio@f7029000 {
599 compatible = "arm,pl061", "arm,primecell";
600 reg = <0x0 0xf7029000 0x0 0x1000>;
601 interrupts = <0 65 0x4>;
604 gpio-ranges = <&pmx0 0 48 8>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
607 clocks = <&ao_ctrl 2>;
608 clock-names = "apb_pclk";
611 gpio14: gpio@f702a000 {
612 compatible = "arm,pl061", "arm,primecell";
613 reg = <0x0 0xf702a000 0x0 0x1000>;
614 interrupts = <0 66 0x4>;
617 gpio-ranges = <&pmx0 0 56 8>;
618 interrupt-controller;
619 #interrupt-cells = <2>;
620 clocks = <&ao_ctrl 2>;
621 clock-names = "apb_pclk";
624 gpio15: gpio@f702b000 {
625 compatible = "arm,pl061", "arm,primecell";
626 reg = <0x0 0xf702b000 0x0 0x1000>;
627 interrupts = <0 67 0x4>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 clocks = <&ao_ctrl 2>;
638 clock-names = "apb_pclk";
641 gpio16: gpio@f702c000 {
642 compatible = "arm,pl061", "arm,primecell";
643 reg = <0x0 0xf702c000 0x0 0x1000>;
644 interrupts = <0 68 0x4>;
647 gpio-ranges = <&pmx0 0 127 8>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
650 clocks = <&ao_ctrl 2>;
651 clock-names = "apb_pclk";
654 gpio17: gpio@f702d000 {
655 compatible = "arm,pl061", "arm,primecell";
656 reg = <0x0 0xf702d000 0x0 0x1000>;
657 interrupts = <0 69 0x4>;
660 gpio-ranges = <&pmx0 0 135 8>;
661 interrupt-controller;
662 #interrupt-cells = <2>;
663 clocks = <&ao_ctrl 2>;
664 clock-names = "apb_pclk";
667 gpio18: gpio@f702e000 {
668 compatible = "arm,pl061", "arm,primecell";
669 reg = <0x0 0xf702e000 0x0 0x1000>;
670 interrupts = <0 70 0x4>;
673 gpio-ranges = <&pmx0 0 143 8>;
674 interrupt-controller;
675 #interrupt-cells = <2>;
676 clocks = <&ao_ctrl 2>;
677 clock-names = "apb_pclk";
680 gpio19: gpio@f702f000 {
681 compatible = "arm,pl061", "arm,primecell";
682 reg = <0x0 0xf702f000 0x0 0x1000>;
683 interrupts = <0 71 0x4>;
686 gpio-ranges = <&pmx0 0 151 8>;
687 interrupt-controller;
688 #interrupt-cells = <2>;
689 clocks = <&ao_ctrl 2>;
690 clock-names = "apb_pclk";
694 compatible = "arm,pl022", "arm,primecell";
695 reg = <0x0 0xf7106000 0x0 0x1000>;
696 interrupts = <0 50 4>;
699 clocks = <&sys_ctrl HI6220_SPI_CLK>;
700 clock-names = "apb_pclk";
701 pinctrl-names = "default";
702 pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
704 cs-gpios = <&gpio6 2 0>;
709 compatible = "snps,designware-i2c";
710 reg = <0x0 0xf7100000 0x0 0x1000>;
711 interrupts = <0 44 4>;
712 clocks = <&sys_ctrl HI6220_I2C0_CLK>;
713 i2c-sda-hold-time-ns = <300>;
714 pinctrl-names = "default";
715 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
720 compatible = "snps,designware-i2c";
721 reg = <0x0 0xf7101000 0x0 0x1000>;
722 clocks = <&sys_ctrl HI6220_I2C1_CLK>;
723 interrupts = <0 45 4>;
724 i2c-sda-hold-time-ns = <300>;
725 pinctrl-names = "default";
726 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
731 compatible = "snps,designware-i2c";
732 reg = <0x0 0xf7102000 0x0 0x1000>;
733 clocks = <&sys_ctrl HI6220_I2C2_CLK>;
734 interrupts = <0 46 4>;
735 i2c-sda-hold-time-ns = <300>;
736 pinctrl-names = "default";
737 pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
742 compatible = "hisilicon,hi6220-usb-phy";
744 phy-supply = <®_5v_hub>;
745 hisilicon,peripheral-syscon = <&sys_ctrl>;
749 compatible = "hisilicon,hi6220-usb";
750 reg = <0x0 0xf72c0000 0x0 0x40000>;
752 phy-names = "usb2-phy";
753 clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
756 g-rx-fifo-size = <512>;
757 g-np-tx-fifo-size = <128>;
758 g-tx-fifo-size = <128 128 128 128 128 128>;
759 interrupts = <0 77 0x4>;
762 mailbox: mailbox@f7510000 {
763 compatible = "hisilicon,hi6220-mbox";
764 reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
765 <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
766 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
770 dwmmc_0: dwmmc0@f723d000 {
771 compatible = "hisilicon,hi6220-dw-mshc";
772 reg = <0x0 0xf723d000 0x0 0x1000>;
773 interrupts = <0x0 0x48 0x4>;
774 clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
775 clock-names = "ciu", "biu";
776 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
777 reset-names = "reset";
778 pinctrl-names = "default";
779 pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
780 &emmc_cfg_func &emmc_rst_cfg_func>;
783 dwmmc_1: dwmmc1@f723e000 {
784 compatible = "hisilicon,hi6220-dw-mshc";
785 hisilicon,peripheral-syscon = <&ao_ctrl>;
786 reg = <0x0 0xf723e000 0x0 0x1000>;
787 interrupts = <0x0 0x49 0x4>;
788 #address-cells = <0x1>;
790 clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
791 clock-names = "ciu", "biu";
792 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
793 reset-names = "reset";
794 pinctrl-names = "default", "idle";
795 pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
796 pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
799 dwmmc_2: dwmmc2@f723f000 {
800 compatible = "hisilicon,hi6220-dw-mshc";
801 reg = <0x0 0xf723f000 0x0 0x1000>;
802 interrupts = <0x0 0x4a 0x4>;
803 clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
804 clock-names = "ciu", "biu";
805 resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
806 reset-names = "reset";
807 pinctrl-names = "default", "idle";
808 pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
809 pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
812 tsensor: tsensor@0,f7030700 {
813 compatible = "hisilicon,tsensor";
814 reg = <0x0 0xf7030700 0x0 0x1000>;
815 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&sys_ctrl 22>;
817 clock-names = "thermal_clk";
818 #thermal-sensor-cells = <1>;
822 compatible = "hisilicon,hi6210-i2s";
823 reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
824 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
825 clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
826 <&sys_ctrl HI6220_BBPPLL0_DIV>;
827 clock-names = "dacodec", "i2s-base";
828 dmas = <&dma0 15 &dma0 14>;
829 dma-names = "rx", "tx";
830 hisilicon,sysctrl-syscon = <&sys_ctrl>;
831 #sound-dai-cells = <1>;
837 polling-delay = <1000>;
838 polling-delay-passive = <100>;
839 sustainable-power = <3326>;
842 thermal-sensors = <&tsensor 2>;
845 threshold: trip-point@0 {
846 temperature = <65000>;
851 target: trip-point@1 {
852 temperature = <75000>;
861 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
868 compatible = "hisilicon,hi6220-ade";
869 reg = <0x0 0xf4100000 0x0 0x7800>;
870 reg-names = "ade_base";
871 hisilicon,noc-syscon = <&medianoc_ade>;
872 resets = <&media_ctrl MEDIA_ADE>;
873 interrupts = <0 115 4>; /* ldi interrupt */
875 clocks = <&media_ctrl HI6220_ADE_CORE>,
876 <&media_ctrl HI6220_CODEC_JPEG>,
877 <&media_ctrl HI6220_ADE_PIX_SRC>;
879 clock-names = "clk_ade_core",
883 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
884 <&media_ctrl HI6220_CODEC_JPEG>;
885 assigned-clock-rates = <360000000>, <288000000>;
891 remote-endpoint = <&dsi_in>;
897 compatible = "hisilicon,hi6220-dsi";
898 reg = <0x0 0xf4107800 0x0 0x100>;
899 clocks = <&media_ctrl HI6220_DSI_PCLK>;
900 clock-names = "pclk";
904 #address-cells = <1>;
907 /* 0 for input port */
911 remote-endpoint = <&ade_out>;
918 compatible = "arm,coresight-cpu-debug","arm,primecell";
919 reg = <0 0xf6590000 0 0x1000>;
920 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
921 clock-names = "apb_pclk";
926 compatible = "arm,coresight-cpu-debug","arm,primecell";
927 reg = <0 0xf6592000 0 0x1000>;
928 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
929 clock-names = "apb_pclk";
934 compatible = "arm,coresight-cpu-debug","arm,primecell";
935 reg = <0 0xf6594000 0 0x1000>;
936 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
937 clock-names = "apb_pclk";
942 compatible = "arm,coresight-cpu-debug","arm,primecell";
943 reg = <0 0xf6596000 0 0x1000>;
944 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
945 clock-names = "apb_pclk";
950 compatible = "arm,coresight-cpu-debug","arm,primecell";
951 reg = <0 0xf65d0000 0 0x1000>;
952 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
953 clock-names = "apb_pclk";
958 compatible = "arm,coresight-cpu-debug","arm,primecell";
959 reg = <0 0xf65d2000 0 0x1000>;
960 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
961 clock-names = "apb_pclk";
966 compatible = "arm,coresight-cpu-debug","arm,primecell";
967 reg = <0 0xf65d4000 0 0x1000>;
968 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
969 clock-names = "apb_pclk";
974 compatible = "arm,coresight-cpu-debug","arm,primecell";
975 reg = <0 0xf65d6000 0 0x1000>;
976 clocks = <&sys_ctrl HI6220_DAPB_CLK>;
977 clock-names = "apb_pclk";