arch/arm64/boot/dts/hisilicon/hi6220.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Hisilicon Hi6220 SoC
   4  *
   5  * Copyright (C) 2015, Hisilicon Ltd.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
  10 #include <dt-bindings/clock/hi6220-clock.h>
  11 #include <dt-bindings/pinctrl/hisi.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "hisilicon,hi6220";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         psci {
  21                 compatible = "arm,psci-0.2";
  22                 method = "smc";
  23         };
  24
  25         cpus {
  26                 #address-cells = <2>;
  27                 #size-cells = <0>;
  28
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&cpu0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&cpu1>;
  36                                 };
  37                                 core2 {
  38                                         cpu = <&cpu2>;
  39                                 };
  40                                 core3 {
  41                                         cpu = <&cpu3>;
  42                                 };
  43                         };
  44                         cluster1 {
  45                                 core0 {
  46                                         cpu = <&cpu4>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&cpu5>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&cpu6>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&cpu7>;
  56                                 };
  57                         };
  58                 };
  59
  60                 idle-states {
  61                         entry-method = "psci";
  62
  63                         CPU_SLEEP: cpu-sleep {
  64                                 compatible = "arm,idle-state";
  65                                 local-timer-stop;
  66                                 arm,psci-suspend-param = <0x0010000>;
  67                                 entry-latency-us = <700>;
  68                                 exit-latency-us = <250>;
  69                                 min-residency-us = <1000>;
  70                         };
  71
  72                         CLUSTER_SLEEP: cluster-sleep {
  73                                 compatible = "arm,idle-state";
  74                                 local-timer-stop;
  75                                 arm,psci-suspend-param = <0x1010000>;
  76                                 entry-latency-us = <1000>;
  77                                 exit-latency-us = <700>;
  78                                 min-residency-us = <2700>;
  79                                 wakeup-latency-us = <1500>;
  80                         };
  81                 };
  82
  83                 cpu0: cpu@0 {
  84                         compatible = "arm,cortex-a53";
  85                         device_type = "cpu";
  86                         reg = <0x0 0x0>;
  87                         enable-method = "psci";
  88                         next-level-cache = <&CLUSTER0_L2>;
  89                         clocks = <&stub_clock 0>;
  90                         operating-points-v2 = <&cpu_opp_table>;
  91                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  92                         #cooling-cells = <2>; /* min followed by max */
  93                         dynamic-power-coefficient = <311>;
  94                 };
  95
  96                 cpu1: cpu@1 {
  97                         compatible = "arm,cortex-a53";
  98                         device_type = "cpu";
  99                         reg = <0x0 0x1>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&CLUSTER0_L2>;
 102                         clocks = <&stub_clock 0>;
 103                         operating-points-v2 = <&cpu_opp_table>;
 104                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 105                         #cooling-cells = <2>; /* min followed by max */
 106                         dynamic-power-coefficient = <311>;
 107                 };
 108
 109                 cpu2: cpu@2 {
 110                         compatible = "arm,cortex-a53";
 111                         device_type = "cpu";
 112                         reg = <0x0 0x2>;
 113                         enable-method = "psci";
 114                         next-level-cache = <&CLUSTER0_L2>;
 115                         clocks = <&stub_clock 0>;
 116                         operating-points-v2 = <&cpu_opp_table>;
 117                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 118                         #cooling-cells = <2>; /* min followed by max */
 119                         dynamic-power-coefficient = <311>;
 120                 };
 121
 122                 cpu3: cpu@3 {
 123                         compatible = "arm,cortex-a53";
 124                         device_type = "cpu";
 125                         reg = <0x0 0x3>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&CLUSTER0_L2>;
 128                         clocks = <&stub_clock 0>;
 129                         operating-points-v2 = <&cpu_opp_table>;
 130                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 131                         #cooling-cells = <2>; /* min followed by max */
 132                         dynamic-power-coefficient = <311>;
 133                 };
 134
 135                 cpu4: cpu@100 {
 136                         compatible = "arm,cortex-a53";
 137                         device_type = "cpu";
 138                         reg = <0x0 0x100>;
 139                         enable-method = "psci";
 140                         next-level-cache = <&CLUSTER1_L2>;
 141                         clocks = <&stub_clock 0>;
 142                         operating-points-v2 = <&cpu_opp_table>;
 143                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 144                         #cooling-cells = <2>; /* min followed by max */
 145                         dynamic-power-coefficient = <311>;
 146                 };
 147
 148                 cpu5: cpu@101 {
 149                         compatible = "arm,cortex-a53";
 150                         device_type = "cpu";
 151                         reg = <0x0 0x101>;
 152                         enable-method = "psci";
 153                         next-level-cache = <&CLUSTER1_L2>;
 154                         clocks = <&stub_clock 0>;
 155                         operating-points-v2 = <&cpu_opp_table>;
 156                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 157                         #cooling-cells = <2>; /* min followed by max */
 158                         dynamic-power-coefficient = <311>;
 159                 };
 160
 161                 cpu6: cpu@102 {
 162                         compatible = "arm,cortex-a53";
 163                         device_type = "cpu";
 164                         reg = <0x0 0x102>;
 165                         enable-method = "psci";
 166                         next-level-cache = <&CLUSTER1_L2>;
 167                         clocks = <&stub_clock 0>;
 168                         operating-points-v2 = <&cpu_opp_table>;
 169                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 170                         #cooling-cells = <2>; /* min followed by max */
 171                         dynamic-power-coefficient = <311>;
 172                 };
 173
 174                 cpu7: cpu@103 {
 175                         compatible = "arm,cortex-a53";
 176                         device_type = "cpu";
 177                         reg = <0x0 0x103>;
 178                         enable-method = "psci";
 179                         next-level-cache = <&CLUSTER1_L2>;
 180                         clocks = <&stub_clock 0>;
 181                         operating-points-v2 = <&cpu_opp_table>;
 182                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 183                         #cooling-cells = <2>; /* min followed by max */
 184                         dynamic-power-coefficient = <311>;
 185                 };
 186
 187                 CLUSTER0_L2: l2-cache0 {
 188                         compatible = "cache";
 189                 };
 190
 191                 CLUSTER1_L2: l2-cache1 {
 192                         compatible = "cache";
 193                 };
 194         };
 195
 196         cpu_opp_table: cpu_opp_table {
 197                 compatible = "operating-points-v2";
 198                 opp-shared;
 199
 200                 opp00 {
 201                         opp-hz = /bits/ 64 <208000000>;
 202                         opp-microvolt = <1040000>;
 203                         clock-latency-ns = <500000>;
 204                 };
 205                 opp01 {
 206                         opp-hz = /bits/ 64 <432000000>;
 207                         opp-microvolt = <1040000>;
 208                         clock-latency-ns = <500000>;
 209                 };
 210                 opp02 {
 211                         opp-hz = /bits/ 64 <729000000>;
 212                         opp-microvolt = <1090000>;
 213                         clock-latency-ns = <500000>;
 214                 };
 215                 opp03 {
 216                         opp-hz = /bits/ 64 <960000000>;
 217                         opp-microvolt = <1180000>;
 218                         clock-latency-ns = <500000>;
 219                 };
 220                 opp04 {
 221                         opp-hz = /bits/ 64 <1200000000>;
 222                         opp-microvolt = <1330000>;
 223                         clock-latency-ns = <500000>;
 224                 };
 225         };
 226
 227         gic: interrupt-controller@f6801000 {
 228                 compatible = "arm,gic-400";
 229                 reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
 230                       <0x0 0xf6802000 0 0x2000>, /* GICC */
 231                       <0x0 0xf6804000 0 0x2000>, /* GICH */
 232                       <0x0 0xf6806000 0 0x2000>; /* GICV */
 233                 #address-cells = <0>;
 234                 #interrupt-cells = <3>;
 235                 interrupt-controller;
 236                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 237         };
 238
 239         timer {
 240                 compatible = "arm,armv8-timer";
 241                 interrupt-parent = <&gic>;
 242                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 243                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 244                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 245                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 246         };
 247
 248         soc {
 249                 compatible = "simple-bus";
 250                 #address-cells = <2>;
 251                 #size-cells = <2>;
 252                 ranges;
 253
 254                 sram: sram@fff80000 {
 255                         compatible = "hisilicon,hi6220-sramctrl", "syscon";
 256                         reg = <0x0 0xfff80000 0x0 0x12000>;
 257                 };
 258
 259                 ao_ctrl: ao_ctrl@f7800000 {
 260                         compatible = "hisilicon,hi6220-aoctrl", "syscon";
 261                         reg = <0x0 0xf7800000 0x0 0x2000>;
 262                         #clock-cells = <1>;
 263                 };
 264
 265                 sys_ctrl: sys_ctrl@f7030000 {
 266                         compatible = "hisilicon,hi6220-sysctrl", "syscon";
 267                         reg = <0x0 0xf7030000 0x0 0x2000>;
 268                         #clock-cells = <1>;
 269                         #reset-cells = <1>;
 270                 };
 271
 272                 media_ctrl: media_ctrl@f4410000 {
 273                         compatible = "hisilicon,hi6220-mediactrl", "syscon";
 274                         reg = <0x0 0xf4410000 0x0 0x1000>;
 275                         #clock-cells = <1>;
 276                         #reset-cells = <1>;
 277                 };
 278
 279                 pm_ctrl: pm_ctrl@f7032000 {
 280                         compatible = "hisilicon,hi6220-pmctrl", "syscon";
 281                         reg = <0x0 0xf7032000 0x0 0x1000>;
 282                         #clock-cells = <1>;
 283                 };
 284
 285                 acpu_sctrl: acpu_sctrl@f6504000 {
 286                         compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";
 287                         reg = <0x0 0xf6504000 0x0 0x1000>;
 288                         #clock-cells = <1>;
 289                 };
 290
 291                 medianoc_ade: medianoc_ade@f4520000 {
 292                         compatible = "syscon";
 293                         reg = <0x0 0xf4520000 0x0 0x4000>;
 294                 };
 295
 296                 stub_clock: stub_clock {
 297                         compatible = "hisilicon,hi6220-stub-clk";
 298                         hisilicon,hi6220-clk-sram = <&sram>;
 299                         #clock-cells = <1>;
 300                         mbox-names = "mbox-tx";
 301                         mboxes = <&mailbox 1 0 11>;
 302                 };
 303
 304                 uart0: uart@f8015000 {  /* console */
 305                         compatible = "arm,pl011", "arm,primecell";
 306                         reg = <0x0 0xf8015000 0x0 0x1000>;
 307                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 308                         clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 309                                  <&ao_ctrl HI6220_UART0_PCLK>;
 310                         clock-names = "uartclk", "apb_pclk";
 311                 };
 312
 313                 uart1: uart@f7111000 {
 314                         compatible = "arm,pl011", "arm,primecell";
 315                         reg = <0x0 0xf7111000 0x0 0x1000>;
 316                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 318                                  <&sys_ctrl HI6220_UART1_PCLK>;
 319                         clock-names = "uartclk", "apb_pclk";
 320                         pinctrl-names = "default";
 321                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
 322                         dmas = <&dma0 8 &dma0 9>;
 323                         dma-names = "rx", "tx";
 324                         status = "disabled";
 325                 };
 326
 327                 uart2: uart@f7112000 {
 328                         compatible = "arm,pl011", "arm,primecell";
 329                         reg = <0x0 0xf7112000 0x0 0x1000>;
 330                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 331                         clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 332                                  <&sys_ctrl HI6220_UART2_PCLK>;
 333                         clock-names = "uartclk", "apb_pclk";
 334                         pinctrl-names = "default";
 335                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 336                         status = "disabled";
 337                 };
 338
 339                 uart3: uart@f7113000 {
 340                         compatible = "arm,pl011", "arm,primecell";
 341                         reg = <0x0 0xf7113000 0x0 0x1000>;
 342                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 343                         clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 344                                  <&sys_ctrl HI6220_UART3_PCLK>;
 345                         clock-names = "uartclk", "apb_pclk";
 346                         pinctrl-names = "default";
 347                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 348                         status = "disabled";
 349                 };
 350
 351                 uart4: uart@f7114000 {
 352                         compatible = "arm,pl011", "arm,primecell";
 353                         reg = <0x0 0xf7114000 0x0 0x1000>;
 354                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 356                                  <&sys_ctrl HI6220_UART4_PCLK>;
 357                         clock-names = "uartclk", "apb_pclk";
 358                         pinctrl-names = "default";
 359                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 360                         status = "disabled";
 361                 };
 362
 363                 dma0: dma@f7370000 {
 364                         compatible = "hisilicon,k3-dma-1.0";
 365                         reg = <0x0 0xf7370000 0x0 0x1000>;
 366                         #dma-cells = <1>;
 367                         dma-channels = <15>;
 368                         dma-requests = <32>;
 369                         interrupts = <0 84 4>;
 370                         clocks = <&sys_ctrl HI6220_EDMAC_ACLK>;
 371                         dma-no-cci;
 372                         dma-type = "hi6220_dma";
 373                         status = "ok";
 374                 };
 375
 376                 dual_timer0: timer@f8008000 {
 377                         compatible = "arm,sp804", "arm,primecell";
 378                         reg = <0x0 0xf8008000 0x0 0x1000>;
 379                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 380                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 381                         clocks = <&ao_ctrl HI6220_TIMER0_PCLK>,
 382                                  <&ao_ctrl HI6220_TIMER0_PCLK>,
 383                                  <&ao_ctrl HI6220_TIMER0_PCLK>;
 384                         clock-names = "timer1", "timer2", "apb_pclk";
 385                 };
 386
 387                 rtc0: rtc@f8003000 {
 388                         compatible = "arm,pl031", "arm,primecell";
 389                         reg = <0x0 0xf8003000 0x0 0x1000>;
 390                         interrupts = <0 12 4>;
 391                         clocks = <&ao_ctrl HI6220_RTC0_PCLK>;
 392                         clock-names = "apb_pclk";
 393                 };
 394
 395                 rtc1: rtc@f8004000 {
 396                         compatible = "arm,pl031", "arm,primecell";
 397                         reg = <0x0 0xf8004000 0x0 0x1000>;
 398                         interrupts = <0 8 4>;
 399                         clocks = <&ao_ctrl HI6220_RTC1_PCLK>;
 400                         clock-names = "apb_pclk";
 401                 };
 402
 403                 pmx0: pinmux@f7010000 {
 404                         compatible = "pinctrl-single";
 405                         reg = <0x0 0xf7010000  0x0 0x27c>;
 406                         #address-cells = <1>;
 407                         #size-cells = <1>;
 408                         #pinctrl-cells = <1>;
 409                         #gpio-range-cells = <3>;
 410                         pinctrl-single,register-width = <32>;
 411                         pinctrl-single,function-mask = <7>;
 412                         pinctrl-single,gpio-range = <
 413                                 &range  80  8 MUX_M0 /* gpio  3: [0..7] */
 414                                 &range  88  8 MUX_M0 /* gpio  4: [0..7] */
 415                                 &range  96  8 MUX_M0 /* gpio  5: [0..7] */
 416                                 &range 104  8 MUX_M0 /* gpio  6: [0..7] */
 417                                 &range 112  8 MUX_M0 /* gpio  7: [0..7] */
 418                                 &range 120  2 MUX_M0 /* gpio  8: [0..1] */
 419                                 &range   2  6 MUX_M1 /* gpio  8: [2..7] */
 420                                 &range   8  8 MUX_M1 /* gpio  9: [0..7] */
 421                                 &range   0  1 MUX_M1 /* gpio 10: [0]    */
 422                                 &range  16  7 MUX_M1 /* gpio 10: [1..7] */
 423                                 &range  23  3 MUX_M1 /* gpio 11: [0..2] */
 424                                 &range  28  5 MUX_M1 /* gpio 11: [3..7] */
 425                                 &range  33  3 MUX_M1 /* gpio 12: [0..2] */
 426                                 &range  43  5 MUX_M1 /* gpio 12: [3..7] */
 427                                 &range  48  8 MUX_M1 /* gpio 13: [0..7] */
 428                                 &range  56  8 MUX_M1 /* gpio 14: [0..7] */
 429                                 &range  74  6 MUX_M1 /* gpio 15: [0..5] */
 430                                 &range 122  1 MUX_M1 /* gpio 15: [6]    */
 431                                 &range 126  1 MUX_M1 /* gpio 15: [7]    */
 432                                 &range 127  8 MUX_M1 /* gpio 16: [0..7] */
 433                                 &range 135  8 MUX_M1 /* gpio 17: [0..7] */
 434                                 &range 143  8 MUX_M1 /* gpio 18: [0..7] */
 435                                 &range 151  8 MUX_M1 /* gpio 19: [0..7] */
 436                         >;
 437                         range: gpio-range {
 438                                 #pinctrl-single,gpio-range-cells = <3>;
 439                         };
 440                 };
 441
 442                 pmx1: pinmux@f7010800 {
 443                         compatible = "pinconf-single";
 444                         reg = <0x0 0xf7010800 0x0 0x28c>;
 445                         #address-cells = <1>;
 446                         #size-cells = <1>;
 447                         #pinctrl-cells = <1>;
 448                         pinctrl-single,register-width = <32>;
 449                 };
 450
 451                 pmx2: pinmux@f8001800 {
 452                         compatible = "pinconf-single";
 453                         reg = <0x0 0xf8001800 0x0 0x78>;
 454                         #address-cells = <1>;
 455                         #size-cells = <1>;
 456                         #pinctrl-cells = <1>;
 457                         pinctrl-single,register-width = <32>;
 458                 };
 459
 460                 gpio0: gpio@f8011000 {
 461                         compatible = "arm,pl061", "arm,primecell";
 462                         reg = <0x0 0xf8011000 0x0 0x1000>;
 463                         interrupts = <0 52 0x4>;
 464                         gpio-controller;
 465                         #gpio-cells = <2>;
 466                         interrupt-controller;
 467                         #interrupt-cells = <2>;
 468                         clocks = <&ao_ctrl 2>;
 469                         clock-names = "apb_pclk";
 470                 };
 471
 472                 gpio1: gpio@f8012000 {
 473                         compatible = "arm,pl061", "arm,primecell";
 474                         reg = <0x0 0xf8012000 0x0 0x1000>;
 475                         interrupts = <0 53 0x4>;
 476                         gpio-controller;
 477                         #gpio-cells = <2>;
 478                         interrupt-controller;
 479                         #interrupt-cells = <2>;
 480                         clocks = <&ao_ctrl 2>;
 481                         clock-names = "apb_pclk";
 482                 };
 483
 484                 gpio2: gpio@f8013000 {
 485                         compatible = "arm,pl061", "arm,primecell";
 486                         reg = <0x0 0xf8013000 0x0 0x1000>;
 487                         interrupts = <0 54 0x4>;
 488                         gpio-controller;
 489                         #gpio-cells = <2>;
 490                         interrupt-controller;
 491                         #interrupt-cells = <2>;
 492                         clocks = <&ao_ctrl 2>;
 493                         clock-names = "apb_pclk";
 494                 };
 495
 496                 gpio3: gpio@f8014000 {
 497                         compatible = "arm,pl061", "arm,primecell";
 498                         reg = <0x0 0xf8014000 0x0 0x1000>;
 499                         interrupts = <0 55 0x4>;
 500                         gpio-controller;
 501                         #gpio-cells = <2>;
 502                         gpio-ranges = <&pmx0 0 80 8>;
 503                         interrupt-controller;
 504                         #interrupt-cells = <2>;
 505                         clocks = <&ao_ctrl 2>;
 506                         clock-names = "apb_pclk";
 507                 };
 508
 509                 gpio4: gpio@f7020000 {
 510                         compatible = "arm,pl061", "arm,primecell";
 511                         reg = <0x0 0xf7020000 0x0 0x1000>;
 512                         interrupts = <0 56 0x4>;
 513                         gpio-controller;
 514                         #gpio-cells = <2>;
 515                         gpio-ranges = <&pmx0 0 88 8>;
 516                         interrupt-controller;
 517                         #interrupt-cells = <2>;
 518                         clocks = <&ao_ctrl 2>;
 519                         clock-names = "apb_pclk";
 520                 };
 521
 522                 gpio5: gpio@f7021000 {
 523                         compatible = "arm,pl061", "arm,primecell";
 524                         reg = <0x0 0xf7021000 0x0 0x1000>;
 525                         interrupts = <0 57 0x4>;
 526                         gpio-controller;
 527                         #gpio-cells = <2>;
 528                         gpio-ranges = <&pmx0 0 96 8>;
 529                         interrupt-controller;
 530                         #interrupt-cells = <2>;
 531                         clocks = <&ao_ctrl 2>;
 532                         clock-names = "apb_pclk";
 533                 };
 534
 535                 gpio6: gpio@f7022000 {
 536                         compatible = "arm,pl061", "arm,primecell";
 537                         reg = <0x0 0xf7022000 0x0 0x1000>;
 538                         interrupts = <0 58 0x4>;
 539                         gpio-controller;
 540                         #gpio-cells = <2>;
 541                         gpio-ranges = <&pmx0 0 104 8>;
 542                         interrupt-controller;
 543                         #interrupt-cells = <2>;
 544                         clocks = <&ao_ctrl 2>;
 545                         clock-names = "apb_pclk";
 546                 };
 547
 548                 gpio7: gpio@f7023000 {
 549                         compatible = "arm,pl061", "arm,primecell";
 550                         reg = <0x0 0xf7023000 0x0 0x1000>;
 551                         interrupts = <0 59 0x4>;
 552                         gpio-controller;
 553                         #gpio-cells = <2>;
 554                         gpio-ranges = <&pmx0 0 112 8>;
 555                         interrupt-controller;
 556                         #interrupt-cells = <2>;
 557                         clocks = <&ao_ctrl 2>;
 558                         clock-names = "apb_pclk";
 559                 };
 560
 561                 gpio8: gpio@f7024000 {
 562                         compatible = "arm,pl061", "arm,primecell";
 563                         reg = <0x0 0xf7024000 0x0 0x1000>;
 564                         interrupts = <0 60 0x4>;
 565                         gpio-controller;
 566                         #gpio-cells = <2>;
 567                         gpio-ranges = <&pmx0 0 120 2 &pmx0 2 2 6>;
 568                         interrupt-controller;
 569                         #interrupt-cells = <2>;
 570                         clocks = <&ao_ctrl 2>;
 571                         clock-names = "apb_pclk";
 572                 };
 573
 574                 gpio9: gpio@f7025000 {
 575                         compatible = "arm,pl061", "arm,primecell";
 576                         reg = <0x0 0xf7025000 0x0 0x1000>;
 577                         interrupts = <0 61 0x4>;
 578                         gpio-controller;
 579                         #gpio-cells = <2>;
 580                         gpio-ranges = <&pmx0 0 8 8>;
 581                         interrupt-controller;
 582                         #interrupt-cells = <2>;
 583                         clocks = <&ao_ctrl 2>;
 584                         clock-names = "apb_pclk";
 585                 };
 586
 587                 gpio10: gpio@f7026000 {
 588                         compatible = "arm,pl061", "arm,primecell";
 589                         reg = <0x0 0xf7026000 0x0 0x1000>;
 590                         interrupts = <0 62 0x4>;
 591                         gpio-controller;
 592                         #gpio-cells = <2>;
 593                         gpio-ranges = <&pmx0 0 0 1 &pmx0 1 16 7>;
 594                         interrupt-controller;
 595                         #interrupt-cells = <2>;
 596                         clocks = <&ao_ctrl 2>;
 597                         clock-names = "apb_pclk";
 598                 };
 599
 600                 gpio11: gpio@f7027000 {
 601                         compatible = "arm,pl061", "arm,primecell";
 602                         reg = <0x0 0xf7027000 0x0 0x1000>;
 603                         interrupts = <0 63 0x4>;
 604                         gpio-controller;
 605                         #gpio-cells = <2>;
 606                         gpio-ranges = <&pmx0 0 23 3 &pmx0 3 28 5>;
 607                         interrupt-controller;
 608                         #interrupt-cells = <2>;
 609                         clocks = <&ao_ctrl 2>;
 610                         clock-names = "apb_pclk";
 611                 };
 612
 613                 gpio12: gpio@f7028000 {
 614                         compatible = "arm,pl061", "arm,primecell";
 615                         reg = <0x0 0xf7028000 0x0 0x1000>;
 616                         interrupts = <0 64 0x4>;
 617                         gpio-controller;
 618                         #gpio-cells = <2>;
 619                         gpio-ranges = <&pmx0 0 33 3 &pmx0 3 43 5>;
 620                         interrupt-controller;
 621                         #interrupt-cells = <2>;
 622                         clocks = <&ao_ctrl 2>;
 623                         clock-names = "apb_pclk";
 624                 };
 625
 626                 gpio13: gpio@f7029000 {
 627                         compatible = "arm,pl061", "arm,primecell";
 628                         reg = <0x0 0xf7029000 0x0 0x1000>;
 629                         interrupts = <0 65 0x4>;
 630                         gpio-controller;
 631                         #gpio-cells = <2>;
 632                         gpio-ranges = <&pmx0 0 48 8>;
 633                         interrupt-controller;
 634                         #interrupt-cells = <2>;
 635                         clocks = <&ao_ctrl 2>;
 636                         clock-names = "apb_pclk";
 637                 };
 638
 639                 gpio14: gpio@f702a000 {
 640                         compatible = "arm,pl061", "arm,primecell";
 641                         reg = <0x0 0xf702a000 0x0 0x1000>;
 642                         interrupts = <0 66 0x4>;
 643                         gpio-controller;
 644                         #gpio-cells = <2>;
 645                         gpio-ranges = <&pmx0 0 56 8>;
 646                         interrupt-controller;
 647                         #interrupt-cells = <2>;
 648                         clocks = <&ao_ctrl 2>;
 649                         clock-names = "apb_pclk";
 650                 };
 651
 652                 gpio15: gpio@f702b000 {
 653                         compatible = "arm,pl061", "arm,primecell";
 654                         reg = <0x0 0xf702b000 0x0 0x1000>;
 655                         interrupts = <0 67 0x4>;
 656                         gpio-controller;
 657                         #gpio-cells = <2>;
 658                         gpio-ranges = <
 659                                 &pmx0 0 74 6
 660                                 &pmx0 6 122 1
 661                                 &pmx0 7 126 1
 662                         >;
 663                         interrupt-controller;
 664                         #interrupt-cells = <2>;
 665                         clocks = <&ao_ctrl 2>;
 666                         clock-names = "apb_pclk";
 667                 };
 668
 669                 gpio16: gpio@f702c000 {
 670                         compatible = "arm,pl061", "arm,primecell";
 671                         reg = <0x0 0xf702c000 0x0 0x1000>;
 672                         interrupts = <0 68 0x4>;
 673                         gpio-controller;
 674                         #gpio-cells = <2>;
 675                         gpio-ranges = <&pmx0 0 127 8>;
 676                         interrupt-controller;
 677                         #interrupt-cells = <2>;
 678                         clocks = <&ao_ctrl 2>;
 679                         clock-names = "apb_pclk";
 680                 };
 681
 682                 gpio17: gpio@f702d000 {
 683                         compatible = "arm,pl061", "arm,primecell";
 684                         reg = <0x0 0xf702d000 0x0 0x1000>;
 685                         interrupts = <0 69 0x4>;
 686                         gpio-controller;
 687                         #gpio-cells = <2>;
 688                         gpio-ranges = <&pmx0 0 135 8>;
 689                         interrupt-controller;
 690                         #interrupt-cells = <2>;
 691                         clocks = <&ao_ctrl 2>;
 692                         clock-names = "apb_pclk";
 693                 };
 694
 695                 gpio18: gpio@f702e000 {
 696                         compatible = "arm,pl061", "arm,primecell";
 697                         reg = <0x0 0xf702e000 0x0 0x1000>;
 698                         interrupts = <0 70 0x4>;
 699                         gpio-controller;
 700                         #gpio-cells = <2>;
 701                         gpio-ranges = <&pmx0 0 143 8>;
 702                         interrupt-controller;
 703                         #interrupt-cells = <2>;
 704                         clocks = <&ao_ctrl 2>;
 705                         clock-names = "apb_pclk";
 706                 };
 707
 708                 gpio19: gpio@f702f000 {
 709                         compatible = "arm,pl061", "arm,primecell";
 710                         reg = <0x0 0xf702f000 0x0 0x1000>;
 711                         interrupts = <0 71 0x4>;
 712                         gpio-controller;
 713                         #gpio-cells = <2>;
 714                         gpio-ranges = <&pmx0 0 151 8>;
 715                         interrupt-controller;
 716                         #interrupt-cells = <2>;
 717                         clocks = <&ao_ctrl 2>;
 718                         clock-names = "apb_pclk";
 719                 };
 720
 721                 spi0: spi@f7106000 {
 722                         compatible = "arm,pl022", "arm,primecell";
 723                         reg = <0x0 0xf7106000 0x0 0x1000>;
 724                         interrupts = <0 50 4>;
 725                         bus-id = <0>;
 726                         enable-dma = <0>;
 727                         clocks = <&sys_ctrl HI6220_SPI_CLK>;
 728                         clock-names = "apb_pclk";
 729                         pinctrl-names = "default";
 730                         pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
 731                         num-cs = <1>;
 732                         cs-gpios = <&gpio6 2 0>;
 733                         status = "disabled";
 734                 };
 735
 736                 i2c0: i2c@f7100000 {
 737                         compatible = "snps,designware-i2c";
 738                         reg = <0x0 0xf7100000 0x0 0x1000>;
 739                         interrupts = <0 44 4>;
 740                         clocks = <&sys_ctrl HI6220_I2C0_CLK>;
 741                         i2c-sda-hold-time-ns = <300>;
 742                         pinctrl-names = "default";
 743                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 744                         status = "disabled";
 745                 };
 746
 747                 i2c1: i2c@f7101000 {
 748                         compatible = "snps,designware-i2c";
 749                         reg = <0x0 0xf7101000 0x0 0x1000>;
 750                         clocks = <&sys_ctrl HI6220_I2C1_CLK>;
 751                         interrupts = <0 45 4>;
 752                         i2c-sda-hold-time-ns = <300>;
 753                         pinctrl-names = "default";
 754                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 755                         status = "disabled";
 756                 };
 757
 758                 i2c2: i2c@f7102000 {
 759                         compatible = "snps,designware-i2c";
 760                         reg = <0x0 0xf7102000 0x0 0x1000>;
 761                         clocks = <&sys_ctrl HI6220_I2C2_CLK>;
 762                         interrupts = <0 46 4>;
 763                         i2c-sda-hold-time-ns = <300>;
 764                         pinctrl-names = "default";
 765                         pinctrl-0 = <&i2c2_pmx_func &i2c2_cfg_func>;
 766                         status = "disabled";
 767                 };
 768
 769                 usb_phy: usbphy {
 770                         compatible = "hisilicon,hi6220-usb-phy";
 771                         #phy-cells = <0>;
 772                         phy-supply = <&reg_5v_hub>;
 773                         hisilicon,peripheral-syscon = <&sys_ctrl>;
 774                 };
 775
 776                 usb: usb@f72c0000 {
 777                         compatible = "hisilicon,hi6220-usb";
 778                         reg = <0x0 0xf72c0000 0x0 0x40000>;
 779                         phys = <&usb_phy>;
 780                         phy-names = "usb2-phy";
 781                         clocks = <&sys_ctrl HI6220_USBOTG_HCLK>;
 782                         clock-names = "otg";
 783                         dr_mode = "otg";
 784                         g-rx-fifo-size = <512>;
 785                         g-np-tx-fifo-size = <128>;
 786                         g-tx-fifo-size = <128 128 128 128 128 128 128 128
 787                                            16  16  16  16  16  16  16>;
 788                         interrupts = <0 77 0x4>;
 789                 };
 790
 791                 mailbox: mailbox@f7510000 {
 792                         compatible = "hisilicon,hi6220-mbox";
 793                         reg = <0x0 0xf7510000 0x0 0x1000>, /* IPC_S */
 794                               <0x0 0x06dff800 0x0 0x0800>; /* Mailbox buffer */
 795                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 796                         #mbox-cells = <3>;
 797                 };
 798
 799                 dwmmc_0: dwmmc0@f723d000 {
 800                         compatible = "hisilicon,hi6220-dw-mshc";
 801                         reg = <0x0 0xf723d000 0x0 0x1000>;
 802                         interrupts = <0x0 0x48 0x4>;
 803                         clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 804                         clock-names = "ciu", "biu";
 805                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
 806                         reset-names = "reset";
 807                         pinctrl-names = "default";
 808                         pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
 809                                      &emmc_cfg_func &emmc_rst_cfg_func>;
 810                 };
 811
 812                 dwmmc_1: dwmmc1@f723e000 {
 813                         compatible = "hisilicon,hi6220-dw-mshc";
 814                         hisilicon,peripheral-syscon = <&ao_ctrl>;
 815                         reg = <0x0 0xf723e000 0x0 0x1000>;
 816                         interrupts = <0x0 0x49 0x4>;
 817                         #address-cells = <0x1>;
 818                         #size-cells = <0x0>;
 819                         clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
 820                         clock-names = "ciu", "biu";
 821                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
 822                         reset-names = "reset";
 823                         pinctrl-names = "default", "idle";
 824                         pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
 825                         pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
 826                 };
 827
 828                 dwmmc_2: dwmmc2@f723f000 {
 829                         compatible = "hisilicon,hi6220-dw-mshc";
 830                         reg = <0x0 0xf723f000 0x0 0x1000>;
 831                         interrupts = <0x0 0x4a 0x4>;
 832                         clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 833                         clock-names = "ciu", "biu";
 834                         resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
 835                         reset-names = "reset";
 836                         pinctrl-names = "default", "idle";
 837                         pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
 838                         pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
 839                 };
 840
 841                 watchdog0: watchdog@f8005000 {
 842                         compatible = "arm,sp805-wdt", "arm,primecell";
 843                         reg = <0x0 0xf8005000 0x0 0x1000>;
 844                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 845                         clocks = <&ao_ctrl HI6220_WDT0_PCLK>;
 846                         clock-names = "apb_pclk";
 847                 };
 848
 849                 tsensor: tsensor@0,f7030700 {
 850                         compatible = "hisilicon,tsensor";
 851                         reg = <0x0 0xf7030700 0x0 0x1000>;
 852                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 853                         clocks = <&sys_ctrl 22>;
 854                         clock-names = "thermal_clk";
 855                         #thermal-sensor-cells = <1>;
 856                 };
 857
 858                 i2s0: i2s@f7118000{
 859                         compatible = "hisilicon,hi6210-i2s";
 860                         reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
 861                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
 862                         clocks = <&sys_ctrl HI6220_DACODEC_PCLK>,
 863                                  <&sys_ctrl HI6220_BBPPLL0_DIV>;
 864                         clock-names = "dacodec", "i2s-base";
 865                         dmas = <&dma0 15 &dma0 14>;
 866                         dma-names = "rx", "tx";
 867                         hisilicon,sysctrl-syscon = <&sys_ctrl>;
 868                         #sound-dai-cells = <1>;
 869                 };
 870
 871                 thermal-zones {
 872
 873                         cls0: cls0 {
 874                                 polling-delay = <1000>;
 875                                 polling-delay-passive = <100>;
 876                                 sustainable-power = <3326>;
 877
 878                                 /* sensor ID */
 879                                 thermal-sensors = <&tsensor 2>;
 880
 881                                 trips {
 882                                         threshold: trip-point@0 {
 883                                                 temperature = <65000>;
 884                                                 hysteresis = <0>;
 885                                                 type = "passive";
 886                                         };
 887
 888                                         target: trip-point@1 {
 889                                                 temperature = <75000>;
 890                                                 hysteresis = <0>;
 891                                                 type = "passive";
 892                                         };
 893                                 };
 894
 895                                 cooling-maps {
 896                                         map0 {
 897                                                 trip = <&target>;
 898                                                 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 899                                                                  <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 900                                                                  <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 901                                                                  <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 902                                                                  <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 903                                                                  <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 904                                                                  <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 905                                                                  <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 906                                         };
 907                                 };
 908                         };
 909                 };
 910
 911                 ade: ade@f4100000 {
 912                         compatible = "hisilicon,hi6220-ade";
 913                         reg = <0x0 0xf4100000 0x0 0x7800>;
 914                         reg-names = "ade_base";
 915                         hisilicon,noc-syscon = <&medianoc_ade>;
 916                         resets = <&media_ctrl MEDIA_ADE>;
 917                         interrupts = <0 115 4>; /* ldi interrupt */
 918
 919                         clocks = <&media_ctrl HI6220_ADE_CORE>,
 920                                  <&media_ctrl HI6220_CODEC_JPEG>,
 921                                  <&media_ctrl HI6220_ADE_PIX_SRC>;
 922                         /*clock name*/
 923                         clock-names  = "clk_ade_core",
 924                                        "clk_codec_jpeg",
 925                                        "clk_ade_pix";
 926
 927                         assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
 928                                 <&media_ctrl HI6220_CODEC_JPEG>;
 929                         assigned-clock-rates = <360000000>, <288000000>;
 930                         dma-coherent;
 931                         status = "disabled";
 932
 933                         port {
 934                                 ade_out: endpoint {
 935                                         remote-endpoint = <&dsi_in>;
 936                                 };
 937                         };
 938                 };
 939
 940                 dsi: dsi@f4107800 {
 941                         compatible = "hisilicon,hi6220-dsi";
 942                         reg = <0x0 0xf4107800 0x0 0x100>;
 943                         clocks = <&media_ctrl  HI6220_DSI_PCLK>;
 944                         clock-names = "pclk";
 945                         status = "disabled";
 946
 947                         ports {
 948                                 #address-cells = <1>;
 949                                 #size-cells = <0>;
 950
 951                                 /* 0 for input port */
 952                                 port@0 {
 953                                         reg = <0>;
 954                                         dsi_in: endpoint {
 955                                                 remote-endpoint = <&ade_out>;
 956                                         };
 957                                 };
 958                         };
 959                 };
 960
 961                 debug@f6590000 {
 962                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 963                         reg = <0 0xf6590000 0 0x1000>;
 964                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 965                         clock-names = "apb_pclk";
 966                         cpu = <&cpu0>;
 967                 };
 968
 969                 debug@f6592000 {
 970                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 971                         reg = <0 0xf6592000 0 0x1000>;
 972                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 973                         clock-names = "apb_pclk";
 974                         cpu = <&cpu1>;
 975                 };
 976
 977                 debug@f6594000 {
 978                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 979                         reg = <0 0xf6594000 0 0x1000>;
 980                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 981                         clock-names = "apb_pclk";
 982                         cpu = <&cpu2>;
 983                 };
 984
 985                 debug@f6596000 {
 986                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 987                         reg = <0 0xf6596000 0 0x1000>;
 988                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 989                         clock-names = "apb_pclk";
 990                         cpu = <&cpu3>;
 991                 };
 992
 993                 debug@f65d0000 {
 994                         compatible = "arm,coresight-cpu-debug","arm,primecell";
 995                         reg = <0 0xf65d0000 0 0x1000>;
 996                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
 997                         clock-names = "apb_pclk";
 998                         cpu = <&cpu4>;
 999                 };
1000
1001                 debug@f65d2000 {
1002                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1003                         reg = <0 0xf65d2000 0 0x1000>;
1004                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1005                         clock-names = "apb_pclk";
1006                         cpu = <&cpu5>;
1007                 };
1008
1009                 debug@f65d4000 {
1010                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1011                         reg = <0 0xf65d4000 0 0x1000>;
1012                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1013                         clock-names = "apb_pclk";
1014                         cpu = <&cpu6>;
1015                 };
1016
1017                 debug@f65d6000 {
1018                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1019                         reg = <0 0xf65d6000 0 0x1000>;
1020                         clocks = <&sys_ctrl HI6220_DAPB_CLK>;
1021                         clock-names = "apb_pclk";
1022                         cpu = <&cpu7>;
1023                 };
1024         };
1025 };
1026
1027 #include "hi6220-coresight.dtsi"