arch/arm64/boot/dts/hisilicon/hi3660.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * dts file for Hisilicon Hi3660 SoC
   4  *
   5  * Copyright (C) 2016, Hisilicon Ltd.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/hi3660-clock.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         compatible = "hisilicon,hi3660";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         psci {
  19                 compatible = "arm,psci-0.2";
  20                 method = "smc";
  21         };
  22
  23         cpus {
  24                 #address-cells = <2>;
  25                 #size-cells = <0>;
  26
  27                 cpu-map {
  28                         cluster0 {
  29                                 core0 {
  30                                         cpu = <&cpu0>;
  31                                 };
  32                                 core1 {
  33                                         cpu = <&cpu1>;
  34                                 };
  35                                 core2 {
  36                                         cpu = <&cpu2>;
  37                                 };
  38                                 core3 {
  39                                         cpu = <&cpu3>;
  40                                 };
  41                         };
  42                         cluster1 {
  43                                 core0 {
  44                                         cpu = <&cpu4>;
  45                                 };
  46                                 core1 {
  47                                         cpu = <&cpu5>;
  48                                 };
  49                                 core2 {
  50                                         cpu = <&cpu6>;
  51                                 };
  52                                 core3 {
  53                                         cpu = <&cpu7>;
  54                                 };
  55                         };
  56                 };
  57
  58                 cpu0: cpu@0 {
  59                         compatible = "arm,cortex-a53";
  60                         device_type = "cpu";
  61                         reg = <0x0 0x0>;
  62                         enable-method = "psci";
  63                         next-level-cache = <&A53_L2>;
  64                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  65                         capacity-dmips-mhz = <592>;
  66                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
  67                         operating-points-v2 = <&cluster0_opp>;
  68                         #cooling-cells = <2>;
  69                         dynamic-power-coefficient = <110>;
  70                 };
  71
  72                 cpu1: cpu@1 {
  73                         compatible = "arm,cortex-a53";
  74                         device_type = "cpu";
  75                         reg = <0x0 0x1>;
  76                         enable-method = "psci";
  77                         next-level-cache = <&A53_L2>;
  78                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  79                         capacity-dmips-mhz = <592>;
  80                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
  81                         operating-points-v2 = <&cluster0_opp>;
  82                         #cooling-cells = <2>;
  83                 };
  84
  85                 cpu2: cpu@2 {
  86                         compatible = "arm,cortex-a53";
  87                         device_type = "cpu";
  88                         reg = <0x0 0x2>;
  89                         enable-method = "psci";
  90                         next-level-cache = <&A53_L2>;
  91                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
  92                         capacity-dmips-mhz = <592>;
  93                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
  94                         operating-points-v2 = <&cluster0_opp>;
  95                         #cooling-cells = <2>;
  96                 };
  97
  98                 cpu3: cpu@3 {
  99                         compatible = "arm,cortex-a53";
 100                         device_type = "cpu";
 101                         reg = <0x0 0x3>;
 102                         enable-method = "psci";
 103                         next-level-cache = <&A53_L2>;
 104                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
 105                         capacity-dmips-mhz = <592>;
 106                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>;
 107                         operating-points-v2 = <&cluster0_opp>;
 108                         #cooling-cells = <2>;
 109                 };
 110
 111                 cpu4: cpu@100 {
 112                         compatible = "arm,cortex-a73";
 113                         device_type = "cpu";
 114                         reg = <0x0 0x100>;
 115                         enable-method = "psci";
 116                         next-level-cache = <&A73_L2>;
 117                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 118                         capacity-dmips-mhz = <1024>;
 119                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 120                         operating-points-v2 = <&cluster1_opp>;
 121                         #cooling-cells = <2>;
 122                         dynamic-power-coefficient = <550>;
 123                 };
 124
 125                 cpu5: cpu@101 {
 126                         compatible = "arm,cortex-a73";
 127                         device_type = "cpu";
 128                         reg = <0x0 0x101>;
 129                         enable-method = "psci";
 130                         next-level-cache = <&A73_L2>;
 131                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 132                         capacity-dmips-mhz = <1024>;
 133                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 134                         operating-points-v2 = <&cluster1_opp>;
 135                         #cooling-cells = <2>;
 136                 };
 137
 138                 cpu6: cpu@102 {
 139                         compatible = "arm,cortex-a73";
 140                         device_type = "cpu";
 141                         reg = <0x0 0x102>;
 142                         enable-method = "psci";
 143                         next-level-cache = <&A73_L2>;
 144                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 145                         capacity-dmips-mhz = <1024>;
 146                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 147                         operating-points-v2 = <&cluster1_opp>;
 148                         #cooling-cells = <2>;
 149                 };
 150
 151                 cpu7: cpu@103 {
 152                         compatible = "arm,cortex-a73";
 153                         device_type = "cpu";
 154                         reg = <0x0 0x103>;
 155                         enable-method = "psci";
 156                         next-level-cache = <&A73_L2>;
 157                         cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>;
 158                         capacity-dmips-mhz = <1024>;
 159                         clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>;
 160                         operating-points-v2 = <&cluster1_opp>;
 161                         #cooling-cells = <2>;
 162                 };
 163
 164                 idle-states {
 165                         entry-method = "psci";
 166
 167                         CPU_SLEEP_0: cpu-sleep-0 {
 168                                 compatible = "arm,idle-state";
 169                                 local-timer-stop;
 170                                 arm,psci-suspend-param = <0x0010000>;
 171                                 entry-latency-us = <400>;
 172                                 exit-latency-us = <650>;
 173                                 min-residency-us = <1500>;
 174                         };
 175                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 176                                 compatible = "arm,idle-state";
 177                                 local-timer-stop;
 178                                 arm,psci-suspend-param = <0x1010000>;
 179                                 entry-latency-us = <500>;
 180                                 exit-latency-us = <1600>;
 181                                 min-residency-us = <3500>;
 182                         };
 183
 184
 185                         CPU_SLEEP_1: cpu-sleep-1 {
 186                                 compatible = "arm,idle-state";
 187                                 local-timer-stop;
 188                                 arm,psci-suspend-param = <0x0010000>;
 189                                 entry-latency-us = <400>;
 190                                 exit-latency-us = <550>;
 191                                 min-residency-us = <1500>;
 192                         };
 193
 194                         CLUSTER_SLEEP_1: cluster-sleep-1 {
 195                                 compatible = "arm,idle-state";
 196                                 local-timer-stop;
 197                                 arm,psci-suspend-param = <0x1010000>;
 198                                 entry-latency-us = <800>;
 199                                 exit-latency-us = <2900>;
 200                                 min-residency-us = <3500>;
 201                         };
 202                 };
 203
 204                 A53_L2: l2-cache0 {
 205                         compatible = "cache";
 206                 };
 207
 208                 A73_L2: l2-cache1 {
 209                         compatible = "cache";
 210                 };
 211         };
 212
 213         cluster0_opp: opp_table0 {
 214                 compatible = "operating-points-v2";
 215                 opp-shared;
 216
 217                 opp00 {
 218                         opp-hz = /bits/ 64 <533000000>;
 219                         opp-microvolt = <700000>;
 220                         clock-latency-ns = <300000>;
 221                 };
 222
 223                 opp01 {
 224                         opp-hz = /bits/ 64 <999000000>;
 225                         opp-microvolt = <800000>;
 226                         clock-latency-ns = <300000>;
 227                 };
 228
 229                 opp02 {
 230                         opp-hz = /bits/ 64 <1402000000>;
 231                         opp-microvolt = <900000>;
 232                         clock-latency-ns = <300000>;
 233                 };
 234
 235                 opp03 {
 236                         opp-hz = /bits/ 64 <1709000000>;
 237                         opp-microvolt = <1000000>;
 238                         clock-latency-ns = <300000>;
 239                 };
 240
 241                 opp04 {
 242                         opp-hz = /bits/ 64 <1844000000>;
 243                         opp-microvolt = <1100000>;
 244                         clock-latency-ns = <300000>;
 245                 };
 246         };
 247
 248         cluster1_opp: opp_table1 {
 249                 compatible = "operating-points-v2";
 250                 opp-shared;
 251
 252                 opp10 {
 253                         opp-hz = /bits/ 64 <903000000>;
 254                         opp-microvolt = <700000>;
 255                         clock-latency-ns = <300000>;
 256                 };
 257
 258                 opp11 {
 259                         opp-hz = /bits/ 64 <1421000000>;
 260                         opp-microvolt = <800000>;
 261                         clock-latency-ns = <300000>;
 262                 };
 263
 264                 opp12 {
 265                         opp-hz = /bits/ 64 <1805000000>;
 266                         opp-microvolt = <900000>;
 267                         clock-latency-ns = <300000>;
 268                 };
 269
 270                 opp13 {
 271                         opp-hz = /bits/ 64 <2112000000>;
 272                         opp-microvolt = <1000000>;
 273                         clock-latency-ns = <300000>;
 274                 };
 275
 276                 opp14 {
 277                         opp-hz = /bits/ 64 <2362000000>;
 278                         opp-microvolt = <1100000>;
 279                         clock-latency-ns = <300000>;
 280                 };
 281         };
 282
 283         gic: interrupt-controller@e82b0000 {
 284                 compatible = "arm,gic-400";
 285                 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
 286                       <0x0 0xe82b2000 0 0x2000>, /* GICC */
 287                       <0x0 0xe82b4000 0 0x2000>, /* GICH */
 288                       <0x0 0xe82b6000 0 0x2000>; /* GICV */
 289                 #address-cells = <0>;
 290                 #interrupt-cells = <3>;
 291                 interrupt-controller;
 292                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
 293                                          IRQ_TYPE_LEVEL_HIGH)>;
 294         };
 295
 296         a53-pmu {
 297                 compatible = "arm,cortex-a53-pmu";
 298                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 299                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 300                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 301                              <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 302                 interrupt-affinity = <&cpu0>,
 303                                      <&cpu1>,
 304                                      <&cpu2>,
 305                                      <&cpu3>;
 306         };
 307
 308         a73-pmu {
 309                 compatible = "arm,cortex-a73-pmu";
 310                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 312                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 313                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 314                 interrupt-affinity = <&cpu4>,
 315                                      <&cpu5>,
 316                                      <&cpu6>,
 317                                      <&cpu7>;
 318         };
 319
 320         timer {
 321                 compatible = "arm,armv8-timer";
 322                 interrupt-parent = <&gic>;
 323                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
 324                                           IRQ_TYPE_LEVEL_LOW)>,
 325                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
 326                                           IRQ_TYPE_LEVEL_LOW)>,
 327                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
 328                                           IRQ_TYPE_LEVEL_LOW)>,
 329                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
 330                                           IRQ_TYPE_LEVEL_LOW)>;
 331         };
 332
 333         soc {
 334                 compatible = "simple-bus";
 335                 #address-cells = <2>;
 336                 #size-cells = <2>;
 337                 ranges;
 338
 339                 crg_ctrl: crg_ctrl@fff35000 {
 340                         compatible = "hisilicon,hi3660-crgctrl", "syscon";
 341                         reg = <0x0 0xfff35000 0x0 0x1000>;
 342                         #clock-cells = <1>;
 343                 };
 344
 345                 crg_rst: crg_rst_controller {
 346                         compatible = "hisilicon,hi3660-reset";
 347                         #reset-cells = <2>;
 348                         hisi,rst-syscon = <&crg_ctrl>;
 349                 };
 350
 351
 352                 pctrl: pctrl@e8a09000 {
 353                         compatible = "hisilicon,hi3660-pctrl", "syscon";
 354                         reg = <0x0 0xe8a09000 0x0 0x2000>;
 355                         #clock-cells = <1>;
 356                 };
 357
 358                 pmuctrl: crg_ctrl@fff34000 {
 359                         compatible = "hisilicon,hi3660-pmuctrl", "syscon";
 360                         reg = <0x0 0xfff34000 0x0 0x1000>;
 361                         #clock-cells = <1>;
 362                 };
 363
 364                 sctrl: sctrl@fff0a000 {
 365                         compatible = "hisilicon,hi3660-sctrl", "syscon";
 366                         reg = <0x0 0xfff0a000 0x0 0x1000>;
 367                         #clock-cells = <1>;
 368                 };
 369
 370                 iomcu: iomcu@ffd7e000 {
 371                         compatible = "hisilicon,hi3660-iomcu", "syscon";
 372                         reg = <0x0 0xffd7e000 0x0 0x1000>;
 373                         #clock-cells = <1>;
 374
 375                 };
 376
 377                 iomcu_rst: reset {
 378                         compatible = "hisilicon,hi3660-reset";
 379                         hisi,rst-syscon = <&iomcu>;
 380                         #reset-cells = <2>;
 381                 };
 382
 383                 mailbox: mailbox@e896b000 {
 384                         compatible = "hisilicon,hi3660-mbox";
 385                         reg = <0x0 0xe896b000 0x0 0x1000>;
 386                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 387                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
 388                         #mbox-cells = <3>;
 389                 };
 390
 391                 stub_clock: stub_clock@e896b500 {
 392                         compatible = "hisilicon,hi3660-stub-clk";
 393                         reg = <0x0 0xe896b500 0x0 0x0100>;
 394                         #clock-cells = <1>;
 395                         mboxes = <&mailbox 13 3 0>;
 396                 };
 397
 398                 dual_timer0: timer@fff14000 {
 399                         compatible = "arm,sp804", "arm,primecell";
 400                         reg = <0x0 0xfff14000 0x0 0x1000>;
 401                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 402                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 403                         clocks = <&crg_ctrl HI3660_OSC32K>,
 404                                  <&crg_ctrl HI3660_OSC32K>,
 405                                  <&crg_ctrl HI3660_OSC32K>;
 406                         clock-names = "timer1", "timer2", "apb_pclk";
 407                 };
 408
 409                 i2c0: i2c@ffd71000 {
 410                         compatible = "snps,designware-i2c";
 411                         reg = <0x0 0xffd71000 0x0 0x1000>;
 412                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         clock-frequency = <400000>;
 416                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
 417                         resets = <&iomcu_rst 0x20 3>;
 418                         pinctrl-names = "default";
 419                         pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
 420                         status = "disabled";
 421                 };
 422
 423                 i2c1: i2c@ffd72000 {
 424                         compatible = "snps,designware-i2c";
 425                         reg = <0x0 0xffd72000 0x0 0x1000>;
 426                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         clock-frequency = <400000>;
 430                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
 431                         resets = <&iomcu_rst 0x20 4>;
 432                         pinctrl-names = "default";
 433                         pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
 434                         status = "disabled";
 435                 };
 436
 437                 i2c3: i2c@fdf0c000 {
 438                         compatible = "snps,designware-i2c";
 439                         reg = <0x0 0xfdf0c000 0x0 0x1000>;
 440                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 441                         #address-cells = <1>;
 442                         #size-cells = <0>;
 443                         clock-frequency = <400000>;
 444                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
 445                         resets = <&crg_rst 0x78 7>;
 446                         pinctrl-names = "default";
 447                         pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
 448                         status = "disabled";
 449                 };
 450
 451                 i2c7: i2c@fdf0b000 {
 452                         compatible = "snps,designware-i2c";
 453                         reg = <0x0 0xfdf0b000 0x0 0x1000>;
 454                         interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         clock-frequency = <400000>;
 458                         clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
 459                         resets = <&crg_rst 0x60 14>;
 460                         pinctrl-names = "default";
 461                         pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
 462                         status = "disabled";
 463                 };
 464
 465                 uart0: serial@fdf02000 {
 466                         compatible = "arm,pl011", "arm,primecell";
 467                         reg = <0x0 0xfdf02000 0x0 0x1000>;
 468                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 469                         clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
 470                                  <&crg_ctrl HI3660_PCLK>;
 471                         clock-names = "uartclk", "apb_pclk";
 472                         pinctrl-names = "default";
 473                         pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
 474                         status = "disabled";
 475                 };
 476
 477                 uart1: serial@fdf00000 {
 478                         compatible = "arm,pl011", "arm,primecell";
 479                         reg = <0x0 0xfdf00000 0x0 0x1000>;
 480                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 481                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
 482                                  <&crg_ctrl HI3660_CLK_GATE_UART1>;
 483                         clock-names = "uartclk", "apb_pclk";
 484                         pinctrl-names = "default";
 485                         pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
 486                         status = "disabled";
 487                 };
 488
 489                 uart2: serial@fdf03000 {
 490                         compatible = "arm,pl011", "arm,primecell";
 491                         reg = <0x0 0xfdf03000 0x0 0x1000>;
 492                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 493                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
 494                                  <&crg_ctrl HI3660_PCLK>;
 495                         clock-names = "uartclk", "apb_pclk";
 496                         pinctrl-names = "default";
 497                         pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
 498                         status = "disabled";
 499                 };
 500
 501                 uart3: serial@ffd74000 {
 502                         compatible = "arm,pl011", "arm,primecell";
 503                         reg = <0x0 0xffd74000 0x0 0x1000>;
 504                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 505                         clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
 506                                  <&crg_ctrl HI3660_PCLK>;
 507                         clock-names = "uartclk", "apb_pclk";
 508                         pinctrl-names = "default";
 509                         pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
 510                         status = "disabled";
 511                 };
 512
 513                 uart4: serial@fdf01000 {
 514                         compatible = "arm,pl011", "arm,primecell";
 515                         reg = <0x0 0xfdf01000 0x0 0x1000>;
 516                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
 518                                  <&crg_ctrl HI3660_CLK_GATE_UART4>;
 519                         clock-names = "uartclk", "apb_pclk";
 520                         pinctrl-names = "default";
 521                         pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
 522                         status = "disabled";
 523                 };
 524
 525                 uart5: serial@fdf05000 {
 526                         compatible = "arm,pl011", "arm,primecell";
 527                         reg = <0x0 0xfdf05000 0x0 0x1000>;
 528                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
 530                                  <&crg_ctrl HI3660_CLK_GATE_UART5>;
 531                         clock-names = "uartclk", "apb_pclk";
 532                         pinctrl-names = "default";
 533                         pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
 534                         status = "disabled";
 535                 };
 536
 537                 uart6: serial@fff32000 {
 538                         compatible = "arm,pl011", "arm,primecell";
 539                         reg = <0x0 0xfff32000 0x0 0x1000>;
 540                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&crg_ctrl HI3660_CLK_UART6>,
 542                                  <&crg_ctrl HI3660_PCLK>;
 543                         clock-names = "uartclk", "apb_pclk";
 544                         pinctrl-names = "default";
 545                         pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
 546                         status = "disabled";
 547                 };
 548
 549                 dma0: dma@fdf30000 {
 550                         compatible = "hisilicon,k3-dma-1.0";
 551                         reg = <0x0 0xfdf30000 0x0 0x1000>;
 552                         #dma-cells = <1>;
 553                         dma-channels = <16>;
 554                         dma-requests = <32>;
 555                         dma-min-chan = <1>;
 556                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;
 558                         dma-no-cci;
 559                         dma-type = "hi3660_dma";
 560                 };
 561
 562                 rtc0: rtc@fff04000 {
 563                         compatible = "arm,pl031", "arm,primecell";
 564                         reg = <0x0 0Xfff04000 0x0 0x1000>;
 565                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&crg_ctrl HI3660_PCLK>;
 567                         clock-names = "apb_pclk";
 568                 };
 569
 570                 gpio0: gpio@e8a0b000 {
 571                         compatible = "arm,pl061", "arm,primecell";
 572                         reg = <0 0xe8a0b000 0 0x1000>;
 573                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 574                         gpio-controller;
 575                         #gpio-cells = <2>;
 576                         gpio-ranges = <&pmx0 1 0 7>;
 577                         interrupt-controller;
 578                         #interrupt-cells = <2>;
 579                         clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
 580                         clock-names = "apb_pclk";
 581                 };
 582
 583                 gpio1: gpio@e8a0c000 {
 584                         compatible = "arm,pl061", "arm,primecell";
 585                         reg = <0 0xe8a0c000 0 0x1000>;
 586                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 587                         gpio-controller;
 588                         #gpio-cells = <2>;
 589                         gpio-ranges = <&pmx0 1 7 7>;
 590                         interrupt-controller;
 591                         #interrupt-cells = <2>;
 592                         clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
 593                         clock-names = "apb_pclk";
 594                 };
 595
 596                 gpio2: gpio@e8a0d000 {
 597                         compatible = "arm,pl061", "arm,primecell";
 598                         reg = <0 0xe8a0d000 0 0x1000>;
 599                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 600                         gpio-controller;
 601                         #gpio-cells = <2>;
 602                         gpio-ranges = <&pmx0 0 14 8>;
 603                         interrupt-controller;
 604                         #interrupt-cells = <2>;
 605                         clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
 606                         clock-names = "apb_pclk";
 607                 };
 608
 609                 gpio3: gpio@e8a0e000 {
 610                         compatible = "arm,pl061", "arm,primecell";
 611                         reg = <0 0xe8a0e000 0 0x1000>;
 612                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 613                         gpio-controller;
 614                         #gpio-cells = <2>;
 615                         gpio-ranges = <&pmx0 0 22 8>;
 616                         interrupt-controller;
 617                         #interrupt-cells = <2>;
 618                         clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
 619                         clock-names = "apb_pclk";
 620                 };
 621
 622                 gpio4: gpio@e8a0f000 {
 623                         compatible = "arm,pl061", "arm,primecell";
 624                         reg = <0 0xe8a0f000 0 0x1000>;
 625                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 626                         gpio-controller;
 627                         #gpio-cells = <2>;
 628                         gpio-ranges = <&pmx0 0 30 8>;
 629                         interrupt-controller;
 630                         #interrupt-cells = <2>;
 631                         clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
 632                         clock-names = "apb_pclk";
 633                 };
 634
 635                 gpio5: gpio@e8a10000 {
 636                         compatible = "arm,pl061", "arm,primecell";
 637                         reg = <0 0xe8a10000 0 0x1000>;
 638                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 639                         gpio-controller;
 640                         #gpio-cells = <2>;
 641                         gpio-ranges = <&pmx0 0 38 8>;
 642                         interrupt-controller;
 643                         #interrupt-cells = <2>;
 644                         clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
 645                         clock-names = "apb_pclk";
 646                 };
 647
 648                 gpio6: gpio@e8a11000 {
 649                         compatible = "arm,pl061", "arm,primecell";
 650                         reg = <0 0xe8a11000 0 0x1000>;
 651                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 652                         gpio-controller;
 653                         #gpio-cells = <2>;
 654                         gpio-ranges = <&pmx0 0 46 8>;
 655                         interrupt-controller;
 656                         #interrupt-cells = <2>;
 657                         clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
 658                         clock-names = "apb_pclk";
 659                 };
 660
 661                 gpio7: gpio@e8a12000 {
 662                         compatible = "arm,pl061", "arm,primecell";
 663                         reg = <0 0xe8a12000 0 0x1000>;
 664                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 665                         gpio-controller;
 666                         #gpio-cells = <2>;
 667                         gpio-ranges = <&pmx0 0 54 8>;
 668                         interrupt-controller;
 669                         #interrupt-cells = <2>;
 670                         clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
 671                         clock-names = "apb_pclk";
 672                 };
 673
 674                 gpio8: gpio@e8a13000 {
 675                         compatible = "arm,pl061", "arm,primecell";
 676                         reg = <0 0xe8a13000 0 0x1000>;
 677                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 678                         gpio-controller;
 679                         #gpio-cells = <2>;
 680                         gpio-ranges = <&pmx0 0 62 8>;
 681                         interrupt-controller;
 682                         #interrupt-cells = <2>;
 683                         clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
 684                         clock-names = "apb_pclk";
 685                 };
 686
 687                 gpio9: gpio@e8a14000 {
 688                         compatible = "arm,pl061", "arm,primecell";
 689                         reg = <0 0xe8a14000 0 0x1000>;
 690                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 691                         gpio-controller;
 692                         #gpio-cells = <2>;
 693                         gpio-ranges = <&pmx0 0 70 8>;
 694                         interrupt-controller;
 695                         #interrupt-cells = <2>;
 696                         clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
 697                         clock-names = "apb_pclk";
 698                 };
 699
 700                 gpio10: gpio@e8a15000 {
 701                         compatible = "arm,pl061", "arm,primecell";
 702                         reg = <0 0xe8a15000 0 0x1000>;
 703                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 704                         gpio-controller;
 705                         #gpio-cells = <2>;
 706                         gpio-ranges = <&pmx0 0 78 8>;
 707                         interrupt-controller;
 708                         #interrupt-cells = <2>;
 709                         clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
 710                         clock-names = "apb_pclk";
 711                 };
 712
 713                 gpio11: gpio@e8a16000 {
 714                         compatible = "arm,pl061", "arm,primecell";
 715                         reg = <0 0xe8a16000 0 0x1000>;
 716                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 717                         gpio-controller;
 718                         #gpio-cells = <2>;
 719                         gpio-ranges = <&pmx0 0 86 8>;
 720                         interrupt-controller;
 721                         #interrupt-cells = <2>;
 722                         clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
 723                         clock-names = "apb_pclk";
 724                 };
 725
 726                 gpio12: gpio@e8a17000 {
 727                         compatible = "arm,pl061", "arm,primecell";
 728                         reg = <0 0xe8a17000 0 0x1000>;
 729                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 730                         gpio-controller;
 731                         #gpio-cells = <2>;
 732                         gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
 733                         interrupt-controller;
 734                         #interrupt-cells = <2>;
 735                         clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
 736                         clock-names = "apb_pclk";
 737                 };
 738
 739                 gpio13: gpio@e8a18000 {
 740                         compatible = "arm,pl061", "arm,primecell";
 741                         reg = <0 0xe8a18000 0 0x1000>;
 742                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 743                         gpio-controller;
 744                         #gpio-cells = <2>;
 745                         gpio-ranges = <&pmx0 0 102 8>;
 746                         interrupt-controller;
 747                         #interrupt-cells = <2>;
 748                         clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
 749                         clock-names = "apb_pclk";
 750                 };
 751
 752                 gpio14: gpio@e8a19000 {
 753                         compatible = "arm,pl061", "arm,primecell";
 754                         reg = <0 0xe8a19000 0 0x1000>;
 755                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 756                         gpio-controller;
 757                         #gpio-cells = <2>;
 758                         gpio-ranges = <&pmx0 0 110 8>;
 759                         interrupt-controller;
 760                         #interrupt-cells = <2>;
 761                         clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
 762                         clock-names = "apb_pclk";
 763                 };
 764
 765                 gpio15: gpio@e8a1a000 {
 766                         compatible = "arm,pl061", "arm,primecell";
 767                         reg = <0 0xe8a1a000 0 0x1000>;
 768                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 769                         gpio-controller;
 770                         #gpio-cells = <2>;
 771                         gpio-ranges = <&pmx0 0 118 6>;
 772                         interrupt-controller;
 773                         #interrupt-cells = <2>;
 774                         clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
 775                         clock-names = "apb_pclk";
 776                 };
 777
 778                 gpio16: gpio@e8a1b000 {
 779                         compatible = "arm,pl061", "arm,primecell";
 780                         reg = <0 0xe8a1b000 0 0x1000>;
 781                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 782                         gpio-controller;
 783                         #gpio-cells = <2>;
 784                         interrupt-controller;
 785                         #interrupt-cells = <2>;
 786                         clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
 787                         clock-names = "apb_pclk";
 788                 };
 789
 790                 gpio17: gpio@e8a1c000 {
 791                         compatible = "arm,pl061", "arm,primecell";
 792                         reg = <0 0xe8a1c000 0 0x1000>;
 793                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 794                         gpio-controller;
 795                         #gpio-cells = <2>;
 796                         interrupt-controller;
 797                         #interrupt-cells = <2>;
 798                         clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
 799                         clock-names = "apb_pclk";
 800                 };
 801
 802                 gpio18: gpio@ff3b4000 {
 803                         compatible = "arm,pl061", "arm,primecell";
 804                         reg = <0 0xff3b4000 0 0x1000>;
 805                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 806                         gpio-controller;
 807                         #gpio-cells = <2>;
 808                         gpio-ranges = <&pmx2 0 0 8>;
 809                         interrupt-controller;
 810                         #interrupt-cells = <2>;
 811                         clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
 812                         clock-names = "apb_pclk";
 813                 };
 814
 815                 gpio19: gpio@ff3b5000 {
 816                         compatible = "arm,pl061", "arm,primecell";
 817                         reg = <0 0xff3b5000 0 0x1000>;
 818                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 819                         gpio-controller;
 820                         #gpio-cells = <2>;
 821                         gpio-ranges = <&pmx2 0 8 4>;
 822                         interrupt-controller;
 823                         #interrupt-cells = <2>;
 824                         clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
 825                         clock-names = "apb_pclk";
 826                 };
 827
 828                 gpio20: gpio@e8a1f000 {
 829                         compatible = "arm,pl061", "arm,primecell";
 830                         reg = <0 0xe8a1f000 0 0x1000>;
 831                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 832                         gpio-controller;
 833                         #gpio-cells = <2>;
 834                         gpio-ranges = <&pmx1 0 0 6>;
 835                         interrupt-controller;
 836                         #interrupt-cells = <2>;
 837                         clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
 838                         clock-names = "apb_pclk";
 839                 };
 840
 841                 gpio21: gpio@e8a20000 {
 842                         compatible = "arm,pl061", "arm,primecell";
 843                         reg = <0 0xe8a20000 0 0x1000>;
 844                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 845                         gpio-controller;
 846                         #gpio-cells = <2>;
 847                         interrupt-controller;
 848                         #interrupt-cells = <2>;
 849                         gpio-ranges = <&pmx3 0 0 6>;
 850                         clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
 851                         clock-names = "apb_pclk";
 852                 };
 853
 854                 gpio22: gpio@fff0b000 {
 855                         compatible = "arm,pl061", "arm,primecell";
 856                         reg = <0 0xfff0b000 0 0x1000>;
 857                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 858                         gpio-controller;
 859                         #gpio-cells = <2>;
 860                         /* GPIO176 */
 861                         gpio-ranges = <&pmx4 2 0 6>;
 862                         interrupt-controller;
 863                         #interrupt-cells = <2>;
 864                         clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
 865                         clock-names = "apb_pclk";
 866                 };
 867
 868                 gpio23: gpio@fff0c000 {
 869                         compatible = "arm,pl061", "arm,primecell";
 870                         reg = <0 0xfff0c000 0 0x1000>;
 871                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 872                         gpio-controller;
 873                         #gpio-cells = <2>;
 874                         /* GPIO184 */
 875                         gpio-ranges = <&pmx4 0 6 7>;
 876                         interrupt-controller;
 877                         #interrupt-cells = <2>;
 878                         clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
 879                         clock-names = "apb_pclk";
 880                 };
 881
 882                 gpio24: gpio@fff0d000 {
 883                         compatible = "arm,pl061", "arm,primecell";
 884                         reg = <0 0xfff0d000 0 0x1000>;
 885                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 886                         gpio-controller;
 887                         #gpio-cells = <2>;
 888                         /* GPIO192 */
 889                         gpio-ranges = <&pmx4 0 13 8>;
 890                         interrupt-controller;
 891                         #interrupt-cells = <2>;
 892                         clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
 893                         clock-names = "apb_pclk";
 894                 };
 895
 896                 gpio25: gpio@fff0e000 {
 897                         compatible = "arm,pl061", "arm,primecell";
 898                         reg = <0 0xfff0e000 0 0x1000>;
 899                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 900                         gpio-controller;
 901                         #gpio-cells = <2>;
 902                         /* GPIO200 */
 903                         gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
 904                         interrupt-controller;
 905                         #interrupt-cells = <2>;
 906                         clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
 907                         clock-names = "apb_pclk";
 908                 };
 909
 910                 gpio26: gpio@fff0f000 {
 911                         compatible = "arm,pl061", "arm,primecell";
 912                         reg = <0 0xfff0f000 0 0x1000>;
 913                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 914                         gpio-controller;
 915                         #gpio-cells = <2>;
 916                         /* GPIO208 */
 917                         gpio-ranges = <&pmx4 0 28 8>;
 918                         interrupt-controller;
 919                         #interrupt-cells = <2>;
 920                         clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
 921                         clock-names = "apb_pclk";
 922                 };
 923
 924                 gpio27: gpio@fff10000 {
 925                         compatible = "arm,pl061", "arm,primecell";
 926                         reg = <0 0xfff10000 0 0x1000>;
 927                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 928                         gpio-controller;
 929                         #gpio-cells = <2>;
 930                         /* GPIO216 */
 931                         gpio-ranges = <&pmx4 0 36 6>;
 932                         interrupt-controller;
 933                         #interrupt-cells = <2>;
 934                         clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
 935                         clock-names = "apb_pclk";
 936                 };
 937
 938                 gpio28: gpio@fff1d000 {
 939                         compatible = "arm,pl061", "arm,primecell";
 940                         reg = <0 0xfff1d000 0 0x1000>;
 941                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 942                         gpio-controller;
 943                         #gpio-cells = <2>;
 944                         interrupt-controller;
 945                         #interrupt-cells = <2>;
 946                         clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
 947                         clock-names = "apb_pclk";
 948                 };
 949
 950                 spi2: spi@ffd68000 {
 951                         compatible = "arm,pl022", "arm,primecell";
 952                         reg = <0x0 0xffd68000 0x0 0x1000>;
 953                         #address-cells = <1>;
 954                         #size-cells = <0>;
 955                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 956                         clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
 957                         clock-names = "apb_pclk";
 958                         pinctrl-names = "default";
 959                         pinctrl-0 = <&spi2_pmx_func>;
 960                         num-cs = <1>;
 961                         cs-gpios = <&gpio27 2 0>;
 962                         status = "disabled";
 963                 };
 964
 965                 spi3: spi@ff3b3000 {
 966                         compatible = "arm,pl022", "arm,primecell";
 967                         reg = <0x0 0xff3b3000 0x0 0x1000>;
 968                         #address-cells = <1>;
 969                         #size-cells = <0>;
 970                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
 971                         clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
 972                         clock-names = "apb_pclk";
 973                         pinctrl-names = "default";
 974                         pinctrl-0 = <&spi3_pmx_func>;
 975                         num-cs = <1>;
 976                         cs-gpios = <&gpio18 5 0>;
 977                         status = "disabled";
 978                 };
 979
 980                 pcie@f4000000 {
 981                         compatible = "hisilicon,kirin960-pcie";
 982                         reg = <0x0 0xf4000000 0x0 0x1000>,
 983                               <0x0 0xff3fe000 0x0 0x1000>,
 984                               <0x0 0xf3f20000 0x0 0x40000>,
 985                               <0x0 0xf5000000 0x0 0x2000>;
 986                         reg-names = "dbi", "apb", "phy", "config";
 987                         bus-range = <0x0  0x1>;
 988                         #address-cells = <3>;
 989                         #size-cells = <2>;
 990                         device_type = "pci";
 991                         ranges = <0x02000000 0x0 0x00000000
 992                                   0x0 0xf6000000
 993                                   0x0 0x02000000>;
 994                         num-lanes = <1>;
 995                         #interrupt-cells = <1>;
 996                         interrupts = <0 283 4>;
 997                         interrupt-names = "msi";
 998                         interrupt-map-mask = <0xf800 0 0 7>;
 999                         interrupt-map = <0x0 0 0 1
1000                                          &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
1001                                         <0x0 0 0 2
1002                                          &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
1003                                         <0x0 0 0 3
1004                                          &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
1005                                         <0x0 0 0 4
1006                                          &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
1007                         clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
1008                                  <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
1009                                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
1010                                  <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
1011                                  <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
1012                         clock-names = "pcie_phy_ref", "pcie_aux",
1013                                       "pcie_apb_phy", "pcie_apb_sys",
1014                                       "pcie_aclk";
1015                         reset-gpios = <&gpio11 1 0 >;
1016                 };
1017
1018                 /* UFS */
1019                 ufs: ufs@ff3b0000 {
1020                         compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
1021                         /* 0: HCI standard */
1022                         /* 1: UFS SYS CTRL */
1023                         reg = <0x0 0xff3b0000 0x0 0x1000>,
1024                                 <0x0 0xff3b1000 0x0 0x1000>;
1025                         interrupt-parent = <&gic>;
1026                         interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
1027                         clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
1028                                 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
1029                         clock-names = "ref_clk", "phy_clk";
1030                         freq-table-hz = <0 0>, <0 0>;
1031                         /* offset: 0x84; bit: 12 */
1032                         resets = <&crg_rst 0x84 12>;
1033                         reset-names = "rst";
1034                 };
1035
1036                 /* SD */
1037                 dwmmc1: dwmmc1@ff37f000 {
1038                         compatible = "hisilicon,hi3660-dw-mshc";
1039                         reg = <0x0 0xff37f000 0x0 0x1000>;
1040                         #address-cells = <1>;
1041                         #size-cells = <0>;
1042                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1043                         clocks = <&crg_ctrl HI3660_CLK_GATE_SD>,
1044                                 <&crg_ctrl HI3660_HCLK_GATE_SD>;
1045                         clock-names = "ciu", "biu";
1046                         clock-frequency = <3200000>;
1047                         resets = <&crg_rst 0x94 18>;
1048                         reset-names = "reset";
1049                         hisilicon,peripheral-syscon = <&sctrl>;
1050                         card-detect-delay = <200>;
1051                         status = "disabled";
1052                 };
1053
1054                 /* SDIO */
1055                 dwmmc2: dwmmc2@ff3ff000 {
1056                         compatible = "hisilicon,hi3660-dw-mshc";
1057                         reg = <0x0 0xff3ff000 0x0 0x1000>;
1058                         #address-cells = <0x1>;
1059                         #size-cells = <0x0>;
1060                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
1061                         clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>,
1062                                  <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;
1063                         clock-names = "ciu", "biu";
1064                         resets = <&crg_rst 0x94 20>;
1065                         reset-names = "reset";
1066                         card-detect-delay = <200>;
1067                         status = "disabled";
1068                 };
1069
1070                 watchdog0: watchdog@e8a06000 {
1071                         compatible = "arm,sp805-wdt", "arm,primecell";
1072                         reg = <0x0 0xe8a06000 0x0 0x1000>;
1073                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1074                         clocks = <&crg_ctrl HI3660_OSC32K>;
1075                         clock-names = "apb_pclk";
1076                 };
1077
1078                 watchdog1: watchdog@e8a07000 {
1079                         compatible = "arm,sp805-wdt", "arm,primecell";
1080                         reg = <0x0 0xe8a07000 0x0 0x1000>;
1081                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1082                         clocks = <&crg_ctrl HI3660_OSC32K>;
1083                         clock-names = "apb_pclk";
1084                 };
1085
1086                 tsensor: tsensor@fff30000 {
1087                         compatible = "hisilicon,hi3660-tsensor";
1088                         reg = <0x0 0xfff30000 0x0 0x1000>;
1089                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1090                         #thermal-sensor-cells = <1>;
1091                 };
1092
1093                 thermal-zones {
1094
1095                         cls0: cls0 {
1096                                 polling-delay = <1000>;
1097                                 polling-delay-passive = <100>;
1098                                 sustainable-power = <4500>;
1099
1100                                 /* sensor ID */
1101                                 thermal-sensors = <&tsensor 1>;
1102
1103                                 trips {
1104                                         threshold: trip-point@0 {
1105                                                 temperature = <65000>;
1106                                                 hysteresis = <1000>;
1107                                                 type = "passive";
1108                                         };
1109
1110                                         target: trip-point@1 {
1111                                                 temperature = <75000>;
1112                                                 hysteresis = <1000>;
1113                                                 type = "passive";
1114                                         };
1115                                 };
1116
1117                                 cooling-maps {
1118                                         map0 {
1119                                                 trip = <&target>;
1120                                                 contribution = <1024>;
1121                                                 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1122                                                                  <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1123                                                                  <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1124                                                                  <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1125                                         };
1126                                         map1 {
1127                                                 trip = <&target>;
1128                                                 contribution = <512>;
1129                                                 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1130                                                                  <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1131                                                                  <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1132                                                                  <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1133                                         };
1134                                 };
1135                         };
1136                 };
1137         };
1138 };