arch/arm64/boot/dts/freescale/imx8qxp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP
   5  *      Dong Aisheng <aisheng.dong@nxp.com>
   6  */
   7
   8 #include <dt-bindings/clock/imx8-clock.h>
   9 #include <dt-bindings/firmware/imx/rsrc.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
  13
  14 / {
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 mmc0 = &usdhc1;
  21                 mmc1 = &usdhc2;
  22                 mmc2 = &usdhc3;
  23                 serial0 = &adma_lpuart0;
  24         };
  25
  26         cpus {
  27                 #address-cells = <2>;
  28                 #size-cells = <0>;
  29
  30                 /* We have 1 clusters with 4 Cortex-A35 cores */
  31                 A35_0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a35";
  34                         reg = <0x0 0x0>;
  35                         enable-method = "psci";
  36                         next-level-cache = <&A35_L2>;
  37                 };
  38
  39                 A35_1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a35";
  42                         reg = <0x0 0x1>;
  43                         enable-method = "psci";
  44                         next-level-cache = <&A35_L2>;
  45                 };
  46
  47                 A35_2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a35";
  50                         reg = <0x0 0x2>;
  51                         enable-method = "psci";
  52                         next-level-cache = <&A35_L2>;
  53                 };
  54
  55                 A35_3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a35";
  58                         reg = <0x0 0x3>;
  59                         enable-method = "psci";
  60                         next-level-cache = <&A35_L2>;
  61                 };
  62
  63                 A35_L2: l2-cache0 {
  64                         compatible = "cache";
  65                 };
  66         };
  67
  68         gic: interrupt-controller@51a00000 {
  69                 compatible = "arm,gic-v3";
  70                 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
  71                       <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
  72                 #interrupt-cells = <3>;
  73                 interrupt-controller;
  74                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  75         };
  76
  77         pmu {
  78                 compatible = "arm,armv8-pmuv3";
  79                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  80         };
  81
  82         psci {
  83                 compatible = "arm,psci-1.0";
  84                 method = "smc";
  85         };
  86
  87         scu {
  88                 compatible = "fsl,imx-scu";
  89                 mbox-names = "tx0", "tx1", "tx2", "tx3",
  90                              "rx0", "rx1", "rx2", "rx3";
  91                 mboxes = <&lsio_mu1 0 0
  92                           &lsio_mu1 0 1
  93                           &lsio_mu1 0 2
  94                           &lsio_mu1 0 3
  95                           &lsio_mu1 1 0
  96                           &lsio_mu1 1 1
  97                           &lsio_mu1 1 2
  98                           &lsio_mu1 1 3>;
  99
 100                 clk: clock-controller {
 101                         compatible = "fsl,imx8qxp-clk";
 102                         #clock-cells = <1>;
 103                         clocks = <&xtal32k &xtal24m>;
 104                         clock-names = "xtal_32KHz", "xtal_24Mhz";
 105                 };
 106
 107                 iomuxc: pinctrl {
 108                         compatible = "fsl,imx8qxp-iomuxc";
 109                 };
 110
 111                 pd: imx8qx-pd {
 112                         compatible = "fsl,imx8qxp-scu-pd";
 113                         #power-domain-cells = <1>;
 114                 };
 115
 116                 rtc: rtc {
 117                         compatible = "fsl,imx8qxp-sc-rtc";
 118                 };
 119         };
 120
 121         timer {
 122                 compatible = "arm,armv8-timer";
 123                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 124                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 125                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 126                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 127         };
 128
 129         xtal32k: clock-xtal32k {
 130                 compatible = "fixed-clock";
 131                 #clock-cells = <0>;
 132                 clock-frequency = <32768>;
 133                 clock-output-names = "xtal_32KHz";
 134         };
 135
 136         xtal24m: clock-xtal24m {
 137                 compatible = "fixed-clock";
 138                 #clock-cells = <0>;
 139                 clock-frequency = <24000000>;
 140                 clock-output-names = "xtal_24MHz";
 141         };
 142
 143         adma_subsys: bus@59000000 {
 144                 compatible = "simple-bus";
 145                 #address-cells = <1>;
 146                 #size-cells = <1>;
 147                 ranges = <0x59000000 0x0 0x59000000 0x2000000>;
 148
 149                 adma_lpcg: clock-controller@59000000 {
 150                         compatible = "fsl,imx8qxp-lpcg-adma";
 151                         reg = <0x59000000 0x2000000>;
 152                         #clock-cells = <1>;
 153                 };
 154
 155                 adma_lpuart0: serial@5a060000 {
 156                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 157                         reg = <0x5a060000 0x1000>;
 158                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 159                         interrupt-parent = <&gic>;
 160                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
 161                         clock-names = "ipg";
 162                         power-domains = <&pd IMX_SC_R_UART_0>;
 163                         status = "disabled";
 164                 };
 165
 166                 adma_i2c0: i2c@5a800000 {
 167                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 168                         reg = <0x5a800000 0x4000>;
 169                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 170                         interrupt-parent = <&gic>;
 171                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
 172                         clock-names = "per";
 173                         assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
 174                         assigned-clock-rates = <24000000>;
 175                         power-domains = <&pd IMX_SC_R_I2C_0>;
 176                         status = "disabled";
 177                 };
 178
 179                 adma_i2c1: i2c@5a810000 {
 180                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 181                         reg = <0x5a810000 0x4000>;
 182                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 183                         interrupt-parent = <&gic>;
 184                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
 185                         clock-names = "per";
 186                         assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
 187                         assigned-clock-rates = <24000000>;
 188                         power-domains = <&pd IMX_SC_R_I2C_1>;
 189                         status = "disabled";
 190                 };
 191
 192                 adma_i2c2: i2c@5a820000 {
 193                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 194                         reg = <0x5a820000 0x4000>;
 195                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 196                         interrupt-parent = <&gic>;
 197                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
 198                         clock-names = "per";
 199                         assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
 200                         assigned-clock-rates = <24000000>;
 201                         power-domains = <&pd IMX_SC_R_I2C_2>;
 202                         status = "disabled";
 203                 };
 204
 205                 adma_i2c3: i2c@5a830000 {
 206                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 207                         reg = <0x5a830000 0x4000>;
 208                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 209                         interrupt-parent = <&gic>;
 210                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
 211                         clock-names = "per";
 212                         assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
 213                         assigned-clock-rates = <24000000>;
 214                         power-domains = <&pd IMX_SC_R_I2C_3>;
 215                         status = "disabled";
 216                 };
 217         };
 218
 219         conn_subsys: bus@5b000000 {
 220                 compatible = "simple-bus";
 221                 #address-cells = <1>;
 222                 #size-cells = <1>;
 223                 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
 224
 225                 conn_lpcg: clock-controller@5b200000 {
 226                         compatible = "fsl,imx8qxp-lpcg-conn";
 227                         reg = <0x5b200000 0xb0000>;
 228                         #clock-cells = <1>;
 229                 };
 230
 231                 usdhc1: mmc@5b010000 {
 232                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 233                         interrupt-parent = <&gic>;
 234                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 235                         reg = <0x5b010000 0x10000>;
 236                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
 237                                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
 238                                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
 239                         clock-names = "ipg", "per", "ahb";
 240                         assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
 241                         assigned-clock-rates = <200000000>;
 242                         power-domains = <&pd IMX_SC_R_SDHC_0>;
 243                         status = "disabled";
 244                 };
 245
 246                 usdhc2: mmc@5b020000 {
 247                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 248                         interrupt-parent = <&gic>;
 249                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 250                         reg = <0x5b020000 0x10000>;
 251                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
 252                                  <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
 253                                  <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
 254                         clock-names = "ipg", "per", "ahb";
 255                         assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
 256                         assigned-clock-rates = <200000000>;
 257                         power-domains = <&pd IMX_SC_R_SDHC_1>;
 258                         fsl,tuning-start-tap = <20>;
 259                         fsl,tuning-step= <2>;
 260                         status = "disabled";
 261                 };
 262
 263                 usdhc3: mmc@5b030000 {
 264                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 265                         interrupt-parent = <&gic>;
 266                         interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 267                         reg = <0x5b030000 0x10000>;
 268                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
 269                                  <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
 270                                  <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
 271                         clock-names = "ipg", "per", "ahb";
 272                         assigned-clocks = <&clk IMX_CONN_SDHC2_CLK>;
 273                         assigned-clock-rates = <200000000>;
 274                         power-domains = <&pd IMX_SC_R_SDHC_2>;
 275                         status = "disabled";
 276                 };
 277
 278                 fec1: ethernet@5b040000 {
 279                         compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
 280                         reg = <0x5b040000 0x10000>;
 281                         interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 282                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 284                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
 285                         clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
 286                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
 287                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
 288                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
 289                         clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 290                         fsl,num-tx-queues=<3>;
 291                         fsl,num-rx-queues=<3>;
 292                         power-domains = <&pd IMX_SC_R_ENET_0>;
 293                         status = "disabled";
 294                 };
 295
 296                 fec2: ethernet@5b050000 {
 297                         compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
 298                         reg = <0x5b050000 0x10000>;
 299                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 300                                         <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 301                                         <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 302                                         <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
 304                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
 305                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
 306                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
 307                         clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 308                         fsl,num-tx-queues=<3>;
 309                         fsl,num-rx-queues=<3>;
 310                         power-domains = <&pd IMX_SC_R_ENET_1>;
 311                         status = "disabled";
 312                 };
 313         };
 314
 315         lsio_subsys: bus@5d000000 {
 316                 compatible = "simple-bus";
 317                 #address-cells = <1>;
 318                 #size-cells = <1>;
 319                 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
 320
 321                 lsio_lpcg: clock-controller@5d400000 {
 322                         compatible = "fsl,imx8qxp-lpcg-lsio";
 323                         reg = <0x5d400000 0x400000>;
 324                         #clock-cells = <1>;
 325                 };
 326
 327                 lsio_mu0: mailbox@5d1b0000 {
 328                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 329                         reg = <0x5d1b0000 0x10000>;
 330                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 331                         #mbox-cells = <0>;
 332                         status = "disabled";
 333                 };
 334
 335                 lsio_mu1: mailbox@5d1c0000 {
 336                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 337                         reg = <0x5d1c0000 0x10000>;
 338                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 339                         #mbox-cells = <2>;
 340                 };
 341
 342                 lsio_mu3: mailbox@5d1e0000 {
 343                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 344                         reg = <0x5d1e0000 0x10000>;
 345                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 346                         #mbox-cells = <0>;
 347                         status = "disabled";
 348                 };
 349
 350                 lsio_mu4: mailbox@5d1f0000 {
 351                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 352                         reg = <0x5d1f0000 0x10000>;
 353                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 354                         #mbox-cells = <0>;
 355                         status = "disabled";
 356                 };
 357
 358                 lsio_gpio0: gpio@5d080000 {
 359                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 360                         reg = <0x5d080000 0x10000>;
 361                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 362                         gpio-controller;
 363                         #gpio-cells = <2>;
 364                         interrupt-controller;
 365                         #interrupt-cells = <2>;
 366                         power-domains = <&pd IMX_SC_R_GPIO_0>;
 367                 };
 368
 369                 lsio_gpio1: gpio@5d090000 {
 370                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 371                         reg = <0x5d090000 0x10000>;
 372                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 373                         gpio-controller;
 374                         #gpio-cells = <2>;
 375                         interrupt-controller;
 376                         #interrupt-cells = <2>;
 377                         power-domains = <&pd IMX_SC_R_GPIO_1>;
 378                 };
 379
 380                 lsio_gpio2: gpio@5d0a0000 {
 381                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 382                         reg = <0x5d0a0000 0x10000>;
 383                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 384                         gpio-controller;
 385                         #gpio-cells = <2>;
 386                         interrupt-controller;
 387                         #interrupt-cells = <2>;
 388                         power-domains = <&pd IMX_SC_R_GPIO_2>;
 389                 };
 390
 391                 lsio_gpio3: gpio@5d0b0000 {
 392                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 393                         reg = <0x5d0b0000 0x10000>;
 394                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 395                         gpio-controller;
 396                         #gpio-cells = <2>;
 397                         interrupt-controller;
 398                         #interrupt-cells = <2>;
 399                         power-domains = <&pd IMX_SC_R_GPIO_3>;
 400                 };
 401
 402                 lsio_gpio4: gpio@5d0c0000 {
 403                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 404                         reg = <0x5d0c0000 0x10000>;
 405                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 406                         gpio-controller;
 407                         #gpio-cells = <2>;
 408                         interrupt-controller;
 409                         #interrupt-cells = <2>;
 410                         power-domains = <&pd IMX_SC_R_GPIO_4>;
 411                 };
 412
 413                 lsio_gpio5: gpio@5d0d0000 {
 414                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 415                         reg = <0x5d0d0000 0x10000>;
 416                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 417                         gpio-controller;
 418                         #gpio-cells = <2>;
 419                         interrupt-controller;
 420                         #interrupt-cells = <2>;
 421                         power-domains = <&pd IMX_SC_R_GPIO_5>;
 422                 };
 423
 424                 lsio_gpio6: gpio@5d0e0000 {
 425                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 426                         reg = <0x5d0e0000 0x10000>;
 427                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 428                         gpio-controller;
 429                         #gpio-cells = <2>;
 430                         interrupt-controller;
 431                         #interrupt-cells = <2>;
 432                         power-domains = <&pd IMX_SC_R_GPIO_6>;
 433                 };
 434
 435                 lsio_gpio7: gpio@5d0f0000 {
 436                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 437                         reg = <0x5d0f0000 0x10000>;
 438                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 439                         gpio-controller;
 440                         #gpio-cells = <2>;
 441                         interrupt-controller;
 442                         #interrupt-cells = <2>;
 443                         power-domains = <&pd IMX_SC_R_GPIO_7>;
 444                 };
 445         };
 446 };