arch/arm64/boot/dts/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include "imx8mq-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gpc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 spi0 = &ecspi1;
  37                 spi1 = &ecspi2;
  38                 spi2 = &ecspi3;
  39         };
  40
  41         ckil: clock-ckil {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <32768>;
  45                 clock-output-names = "ckil";
  46         };
  47
  48         osc_25m: clock-osc-25m {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <25000000>;
  52                 clock-output-names = "osc_25m";
  53         };
  54
  55         osc_27m: clock-osc-27m {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <27000000>;
  59                 clock-output-names = "osc_27m";
  60         };
  61
  62         clk_ext1: clock-ext1 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <133000000>;
  66                 clock-output-names = "clk_ext1";
  67         };
  68
  69         clk_ext2: clock-ext2 {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <133000000>;
  73                 clock-output-names = "clk_ext2";
  74         };
  75
  76         clk_ext3: clock-ext3 {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <133000000>;
  80                 clock-output-names = "clk_ext3";
  81         };
  82
  83         clk_ext4: clock-ext4 {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency= <133000000>;
  87                 clock-output-names = "clk_ext4";
  88         };
  89
  90         cpus {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 A53_0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x0>;
  98                         clock-latency = <61036>; /* two CLK32 periods */
  99                         clocks = <&clk IMX8MQ_CLK_ARM>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                         nvmem-cells = <&cpu_speed_grade>;
 105                         nvmem-cell-names = "speed_grade";
 106                 };
 107
 108                 A53_1: cpu@1 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x1>;
 112                         clock-latency = <61036>; /* two CLK32 periods */
 113                         clocks = <&clk IMX8MQ_CLK_ARM>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&A53_L2>;
 116                         operating-points-v2 = <&a53_opp_table>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_2: cpu@2 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x2>;
 124                         clock-latency = <61036>; /* two CLK32 periods */
 125                         clocks = <&clk IMX8MQ_CLK_ARM>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&A53_L2>;
 128                         operating-points-v2 = <&a53_opp_table>;
 129                         #cooling-cells = <2>;
 130                 };
 131
 132                 A53_3: cpu@3 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53";
 135                         reg = <0x3>;
 136                         clock-latency = <61036>; /* two CLK32 periods */
 137                         clocks = <&clk IMX8MQ_CLK_ARM>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&A53_L2>;
 140                         operating-points-v2 = <&a53_opp_table>;
 141                         #cooling-cells = <2>;
 142                 };
 143
 144                 A53_L2: l2-cache0 {
 145                         compatible = "cache";
 146                 };
 147         };
 148
 149         a53_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151                 opp-shared;
 152
 153                 opp-800000000 {
 154                         opp-hz = /bits/ 64 <800000000>;
 155                         opp-microvolt = <900000>;
 156                         /* Industrial only */
 157                         opp-supported-hw = <0xf>, <0x4>;
 158                         clock-latency-ns = <150000>;
 159                         opp-suspend;
 160                 };
 161
 162                 opp-1000000000 {
 163                         opp-hz = /bits/ 64 <1000000000>;
 164                         opp-microvolt = <900000>;
 165                         /* Consumer only */
 166                         opp-supported-hw = <0xe>, <0x3>;
 167                         clock-latency-ns = <150000>;
 168                         opp-suspend;
 169                 };
 170
 171                 opp-1300000000 {
 172                         opp-hz = /bits/ 64 <1300000000>;
 173                         opp-microvolt = <1000000>;
 174                         opp-supported-hw = <0xc>, <0x4>;
 175                         clock-latency-ns = <150000>;
 176                         opp-suspend;
 177                 };
 178
 179                 opp-1500000000 {
 180                         opp-hz = /bits/ 64 <1500000000>;
 181                         opp-microvolt = <1000000>;
 182                         opp-supported-hw = <0x8>, <0x3>;
 183                         clock-latency-ns = <150000>;
 184                         opp-suspend;
 185                 };
 186         };
 187
 188         pmu {
 189                 compatible = "arm,cortex-a53-pmu";
 190                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 191                 interrupt-parent = <&gic>;
 192                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 193         };
 194
 195         psci {
 196                 compatible = "arm,psci-1.0";
 197                 method = "smc";
 198         };
 199
 200         thermal-zones {
 201                 cpu-thermal {
 202                         polling-delay-passive = <250>;
 203                         polling-delay = <2000>;
 204                         thermal-sensors = <&tmu 0>;
 205
 206                         trips {
 207                                 cpu_alert: cpu-alert {
 208                                         temperature = <80000>;
 209                                         hysteresis = <2000>;
 210                                         type = "passive";
 211                                 };
 212
 213                                 cpu-crit {
 214                                         temperature = <90000>;
 215                                         hysteresis = <2000>;
 216                                         type = "critical";
 217                                 };
 218                         };
 219
 220                         cooling-maps {
 221                                 map0 {
 222                                         trip = <&cpu_alert>;
 223                                         cooling-device =
 224                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 225                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 226                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 227                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 228                                 };
 229                         };
 230                 };
 231
 232                 gpu-thermal {
 233                         polling-delay-passive = <250>;
 234                         polling-delay = <2000>;
 235                         thermal-sensors = <&tmu 1>;
 236
 237                         trips {
 238                                 gpu-crit {
 239                                         temperature = <90000>;
 240                                         hysteresis = <2000>;
 241                                         type = "critical";
 242                                 };
 243                         };
 244                 };
 245
 246                 vpu-thermal {
 247                         polling-delay-passive = <250>;
 248                         polling-delay = <2000>;
 249                         thermal-sensors = <&tmu 2>;
 250
 251                         trips {
 252                                 vpu-crit {
 253                                         temperature = <90000>;
 254                                         hysteresis = <2000>;
 255                                         type = "critical";
 256                                 };
 257                         };
 258                 };
 259         };
 260
 261         timer {
 262                 compatible = "arm,armv8-timer";
 263                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 264                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 265                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 266                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 267                 interrupt-parent = <&gic>;
 268                 arm,no-tick-in-suspend;
 269         };
 270
 271         soc@0 {
 272                 compatible = "simple-bus";
 273                 #address-cells = <1>;
 274                 #size-cells = <1>;
 275                 ranges = <0x0 0x0 0x0 0x3e000000>;
 276                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 277
 278                 bus@30000000 { /* AIPS1 */
 279                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 280                         #address-cells = <1>;
 281                         #size-cells = <1>;
 282                         ranges = <0x30000000 0x30000000 0x400000>;
 283
 284                         gpio1: gpio@30200000 {
 285                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 286                                 reg = <0x30200000 0x10000>;
 287                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 288                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 289                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 290                                 gpio-controller;
 291                                 #gpio-cells = <2>;
 292                                 interrupt-controller;
 293                                 #interrupt-cells = <2>;
 294                                 gpio-ranges = <&iomuxc 0 10 30>;
 295                         };
 296
 297                         gpio2: gpio@30210000 {
 298                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 299                                 reg = <0x30210000 0x10000>;
 300                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 301                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 302                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 303                                 gpio-controller;
 304                                 #gpio-cells = <2>;
 305                                 interrupt-controller;
 306                                 #interrupt-cells = <2>;
 307                                 gpio-ranges = <&iomuxc 0 40 21>;
 308                         };
 309
 310                         gpio3: gpio@30220000 {
 311                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 312                                 reg = <0x30220000 0x10000>;
 313                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 314                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 315                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 316                                 gpio-controller;
 317                                 #gpio-cells = <2>;
 318                                 interrupt-controller;
 319                                 #interrupt-cells = <2>;
 320                                 gpio-ranges = <&iomuxc 0 61 26>;
 321                         };
 322
 323                         gpio4: gpio@30230000 {
 324                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 325                                 reg = <0x30230000 0x10000>;
 326                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 327                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 328                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 329                                 gpio-controller;
 330                                 #gpio-cells = <2>;
 331                                 interrupt-controller;
 332                                 #interrupt-cells = <2>;
 333                                 gpio-ranges = <&iomuxc 0 87 32>;
 334                         };
 335
 336                         gpio5: gpio@30240000 {
 337                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 338                                 reg = <0x30240000 0x10000>;
 339                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 340                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 341                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 342                                 gpio-controller;
 343                                 #gpio-cells = <2>;
 344                                 interrupt-controller;
 345                                 #interrupt-cells = <2>;
 346                                 gpio-ranges = <&iomuxc 0 119 30>;
 347                         };
 348
 349                         tmu: tmu@30260000 {
 350                                 compatible = "fsl,imx8mq-tmu";
 351                                 reg = <0x30260000 0x10000>;
 352                                 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 353                                 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
 354                                 little-endian;
 355                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 356                                 fsl,tmu-calibration = <0x00000000 0x00000023
 357                                                        0x00000001 0x00000029
 358                                                        0x00000002 0x0000002f
 359                                                        0x00000003 0x00000035
 360                                                        0x00000004 0x0000003d
 361                                                        0x00000005 0x00000043
 362                                                        0x00000006 0x0000004b
 363                                                        0x00000007 0x00000051
 364                                                        0x00000008 0x00000057
 365                                                        0x00000009 0x0000005f
 366                                                        0x0000000a 0x00000067
 367                                                        0x0000000b 0x0000006f
 368
 369                                                        0x00010000 0x0000001b
 370                                                        0x00010001 0x00000023
 371                                                        0x00010002 0x0000002b
 372                                                        0x00010003 0x00000033
 373                                                        0x00010004 0x0000003b
 374                                                        0x00010005 0x00000043
 375                                                        0x00010006 0x0000004b
 376                                                        0x00010007 0x00000055
 377                                                        0x00010008 0x0000005d
 378                                                        0x00010009 0x00000067
 379                                                        0x0001000a 0x00000070
 380
 381                                                        0x00020000 0x00000017
 382                                                        0x00020001 0x00000023
 383                                                        0x00020002 0x0000002d
 384                                                        0x00020003 0x00000037
 385                                                        0x00020004 0x00000041
 386                                                        0x00020005 0x0000004b
 387                                                        0x00020006 0x00000057
 388                                                        0x00020007 0x00000063
 389                                                        0x00020008 0x0000006f
 390
 391                                                        0x00030000 0x00000015
 392                                                        0x00030001 0x00000021
 393                                                        0x00030002 0x0000002d
 394                                                        0x00030003 0x00000039
 395                                                        0x00030004 0x00000045
 396                                                        0x00030005 0x00000053
 397                                                        0x00030006 0x0000005f
 398                                                        0x00030007 0x00000071>;
 399                                 #thermal-sensor-cells =  <1>;
 400                         };
 401
 402                         wdog1: watchdog@30280000 {
 403                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 404                                 reg = <0x30280000 0x10000>;
 405                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 406                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 407                                 status = "disabled";
 408                         };
 409
 410                         wdog2: watchdog@30290000 {
 411                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 412                                 reg = <0x30290000 0x10000>;
 413                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 414                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 415                                 status = "disabled";
 416                         };
 417
 418                         wdog3: watchdog@302a0000 {
 419                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 420                                 reg = <0x302a0000 0x10000>;
 421                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 422                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 423                                 status = "disabled";
 424                         };
 425
 426                         sdma2: sdma@302c0000 {
 427                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 428                                 reg = <0x302c0000 0x10000>;
 429                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 430                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 431                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 432                                 clock-names = "ipg", "ahb";
 433                                 #dma-cells = <3>;
 434                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 435                         };
 436
 437                         iomuxc: iomuxc@30330000 {
 438                                 compatible = "fsl,imx8mq-iomuxc";
 439                                 reg = <0x30330000 0x10000>;
 440                         };
 441
 442                         iomuxc_gpr: syscon@30340000 {
 443                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
 444                                              "syscon", "simple-mfd";
 445                                 reg = <0x30340000 0x10000>;
 446
 447                                 mux: mux-controller {
 448                                         compatible = "mmio-mux";
 449                                         #mux-control-cells = <1>;
 450                                         mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
 451                                 };
 452                         };
 453
 454                         ocotp: ocotp-ctrl@30350000 {
 455                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 456                                 reg = <0x30350000 0x10000>;
 457                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 458                                 #address-cells = <1>;
 459                                 #size-cells = <1>;
 460
 461                                 cpu_speed_grade: speed-grade@10 {
 462                                         reg = <0x10 4>;
 463                                 };
 464                         };
 465
 466                         anatop: syscon@30360000 {
 467                                 compatible = "fsl,imx8mq-anatop", "syscon";
 468                                 reg = <0x30360000 0x10000>;
 469                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 470                         };
 471
 472                         snvs: snvs@30370000 {
 473                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 474                                 reg = <0x30370000 0x10000>;
 475
 476                                 snvs_rtc: snvs-rtc-lp{
 477                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 478                                         regmap =<&snvs>;
 479                                         offset = <0x34>;
 480                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 481                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 482                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 483                                         clock-names = "snvs-rtc";
 484                                 };
 485
 486                                 snvs_pwrkey: snvs-powerkey {
 487                                         compatible = "fsl,sec-v4.0-pwrkey";
 488                                         regmap = <&snvs>;
 489                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 490                                         linux,keycode = <KEY_POWER>;
 491                                         wakeup-source;
 492                                         status = "disabled";
 493                                 };
 494                         };
 495
 496                         clk: clock-controller@30380000 {
 497                                 compatible = "fsl,imx8mq-ccm";
 498                                 reg = <0x30380000 0x10000>;
 499                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 500                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 501                                 #clock-cells = <1>;
 502                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 503                                          <&clk_ext1>, <&clk_ext2>,
 504                                          <&clk_ext3>, <&clk_ext4>;
 505                                 clock-names = "ckil", "osc_25m", "osc_27m",
 506                                               "clk_ext1", "clk_ext2",
 507                                               "clk_ext3", "clk_ext4";
 508                         };
 509
 510                         src: reset-controller@30390000 {
 511                                 compatible = "fsl,imx8mq-src", "syscon";
 512                                 reg = <0x30390000 0x10000>;
 513                                 #reset-cells = <1>;
 514                         };
 515
 516                         gpc: gpc@303a0000 {
 517                                 compatible = "fsl,imx8mq-gpc";
 518                                 reg = <0x303a0000 0x10000>;
 519                                 interrupt-parent = <&gic>;
 520                                 interrupt-controller;
 521                                 #interrupt-cells = <3>;
 522
 523                                 pgc {
 524                                         #address-cells = <1>;
 525                                         #size-cells = <0>;
 526
 527                                         pgc_mipi: power-domain@0 {
 528                                                 #power-domain-cells = <0>;
 529                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 530                                         };
 531
 532                                         /*
 533                                          * As per comment in ATF source code:
 534                                          *
 535                                          * PCIE1 and PCIE2 share the
 536                                          * same reset signal, if we
 537                                          * power down PCIE2, PCIE1
 538                                          * will be held in reset too.
 539                                          *
 540                                          * So instead of creating two
 541                                          * separate power domains for
 542                                          * PCIE1 and PCIE2 we create a
 543                                          * link between both and use
 544                                          * it as a shared PCIE power
 545                                          * domain.
 546                                          */
 547                                         pgc_pcie: power-domain@1 {
 548                                                 #power-domain-cells = <0>;
 549                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 550                                                 power-domains = <&pgc_pcie2>;
 551                                         };
 552
 553                                         pgc_otg1: power-domain@2 {
 554                                                 #power-domain-cells = <0>;
 555                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 556                                         };
 557
 558                                         pgc_otg2: power-domain@3 {
 559                                                 #power-domain-cells = <0>;
 560                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 561                                         };
 562
 563                                         pgc_ddr1: power-domain@4 {
 564                                                 #power-domain-cells = <0>;
 565                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 566                                         };
 567
 568                                         pgc_gpu: power-domain@5 {
 569                                                 #power-domain-cells = <0>;
 570                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 571                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 572                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 573                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 574                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 575                                         };
 576
 577                                         pgc_vpu: power-domain@6 {
 578                                                 #power-domain-cells = <0>;
 579                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 580                                         };
 581
 582                                         pgc_disp: power-domain@7 {
 583                                                 #power-domain-cells = <0>;
 584                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 585                                         };
 586
 587                                         pgc_mipi_csi1: power-domain@8 {
 588                                                 #power-domain-cells = <0>;
 589                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 590                                         };
 591
 592                                         pgc_mipi_csi2: power-domain@9 {
 593                                                 #power-domain-cells = <0>;
 594                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 595                                         };
 596
 597                                         pgc_pcie2: power-domain@a {
 598                                                 #power-domain-cells = <0>;
 599                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 600                                         };
 601                                 };
 602                         };
 603                 };
 604
 605                 bus@30400000 { /* AIPS2 */
 606                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 607                         #address-cells = <1>;
 608                         #size-cells = <1>;
 609                         ranges = <0x30400000 0x30400000 0x400000>;
 610
 611                         pwm1: pwm@30660000 {
 612                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 613                                 reg = <0x30660000 0x10000>;
 614                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 615                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 616                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 617                                 clock-names = "ipg", "per";
 618                                 #pwm-cells = <2>;
 619                                 status = "disabled";
 620                         };
 621
 622                         pwm2: pwm@30670000 {
 623                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 624                                 reg = <0x30670000 0x10000>;
 625                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 626                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 627                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 628                                 clock-names = "ipg", "per";
 629                                 #pwm-cells = <2>;
 630                                 status = "disabled";
 631                         };
 632
 633                         pwm3: pwm@30680000 {
 634                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 635                                 reg = <0x30680000 0x10000>;
 636                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 637                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 638                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 639                                 clock-names = "ipg", "per";
 640                                 #pwm-cells = <2>;
 641                                 status = "disabled";
 642                         };
 643
 644                         pwm4: pwm@30690000 {
 645                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 646                                 reg = <0x30690000 0x10000>;
 647                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 648                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 649                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 650                                 clock-names = "ipg", "per";
 651                                 #pwm-cells = <2>;
 652                                 status = "disabled";
 653                         };
 654                 };
 655
 656                 bus@30800000 { /* AIPS3 */
 657                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 658                         #address-cells = <1>;
 659                         #size-cells = <1>;
 660                         ranges = <0x30800000 0x30800000 0x400000>,
 661                                  <0x08000000 0x08000000 0x10000000>;
 662
 663                         ecspi1: spi@30820000 {
 664                                 #address-cells = <1>;
 665                                 #size-cells = <0>;
 666                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 667                                 reg = <0x30820000 0x10000>;
 668                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 669                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 670                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 671                                 clock-names = "ipg", "per";
 672                                 status = "disabled";
 673                         };
 674
 675                         ecspi2: spi@30830000 {
 676                                 #address-cells = <1>;
 677                                 #size-cells = <0>;
 678                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 679                                 reg = <0x30830000 0x10000>;
 680                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 681                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 682                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 683                                 clock-names = "ipg", "per";
 684                                 status = "disabled";
 685                         };
 686
 687                         ecspi3: spi@30840000 {
 688                                 #address-cells = <1>;
 689                                 #size-cells = <0>;
 690                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 691                                 reg = <0x30840000 0x10000>;
 692                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 693                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 694                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 695                                 clock-names = "ipg", "per";
 696                                 status = "disabled";
 697                         };
 698
 699                         uart1: serial@30860000 {
 700                                 compatible = "fsl,imx8mq-uart",
 701                                              "fsl,imx6q-uart";
 702                                 reg = <0x30860000 0x10000>;
 703                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 704                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 705                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 706                                 clock-names = "ipg", "per";
 707                                 status = "disabled";
 708                         };
 709
 710                         uart3: serial@30880000 {
 711                                 compatible = "fsl,imx8mq-uart",
 712                                              "fsl,imx6q-uart";
 713                                 reg = <0x30880000 0x10000>;
 714                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 715                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 716                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 717                                 clock-names = "ipg", "per";
 718                                 status = "disabled";
 719                         };
 720
 721                         uart2: serial@30890000 {
 722                                 compatible = "fsl,imx8mq-uart",
 723                                              "fsl,imx6q-uart";
 724                                 reg = <0x30890000 0x10000>;
 725                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 726                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 727                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 728                                 clock-names = "ipg", "per";
 729                                 status = "disabled";
 730                         };
 731
 732                         sai2: sai@308b0000 {
 733                                 #sound-dai-cells = <0>;
 734                                 compatible = "fsl,imx8mq-sai";
 735                                 reg = <0x308b0000 0x10000>;
 736                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 737                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 738                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 739                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 740                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 741                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 742                                 dma-names = "rx", "tx";
 743                                 status = "disabled";
 744                         };
 745
 746                         dphy: dphy@30a00300 {
 747                                 compatible = "fsl,imx8mq-mipi-dphy";
 748                                 reg = <0x30a00300 0x100>;
 749                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 750                                 clock-names = "phy_ref";
 751                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 752                                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 753                                 assigned-clock-rates = <24000000>;
 754                                 #phy-cells = <0>;
 755                                 power-domains = <&pgc_mipi>;
 756                                 status = "disabled";
 757                         };
 758
 759                         i2c1: i2c@30a20000 {
 760                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 761                                 reg = <0x30a20000 0x10000>;
 762                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 763                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766                                 status = "disabled";
 767                         };
 768
 769                         i2c2: i2c@30a30000 {
 770                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 771                                 reg = <0x30a30000 0x10000>;
 772                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 773                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 774                                 #address-cells = <1>;
 775                                 #size-cells = <0>;
 776                                 status = "disabled";
 777                         };
 778
 779                         i2c3: i2c@30a40000 {
 780                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 781                                 reg = <0x30a40000 0x10000>;
 782                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 784                                 #address-cells = <1>;
 785                                 #size-cells = <0>;
 786                                 status = "disabled";
 787                         };
 788
 789                         i2c4: i2c@30a50000 {
 790                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 791                                 reg = <0x30a50000 0x10000>;
 792                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 793                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 794                                 #address-cells = <1>;
 795                                 #size-cells = <0>;
 796                                 status = "disabled";
 797                         };
 798
 799                         uart4: serial@30a60000 {
 800                                 compatible = "fsl,imx8mq-uart",
 801                                              "fsl,imx6q-uart";
 802                                 reg = <0x30a60000 0x10000>;
 803                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 804                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
 805                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
 806                                 clock-names = "ipg", "per";
 807                                 status = "disabled";
 808                         };
 809
 810                         usdhc1: mmc@30b40000 {
 811                                 compatible = "fsl,imx8mq-usdhc",
 812                                              "fsl,imx7d-usdhc";
 813                                 reg = <0x30b40000 0x10000>;
 814                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 815                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 816                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 817                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 818                                 clock-names = "ipg", "ahb", "per";
 819                                 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
 820                                 assigned-clock-rates = <400000000>;
 821                                 fsl,tuning-start-tap = <20>;
 822                                 fsl,tuning-step = <2>;
 823                                 bus-width = <4>;
 824                                 status = "disabled";
 825                         };
 826
 827                         usdhc2: mmc@30b50000 {
 828                                 compatible = "fsl,imx8mq-usdhc",
 829                                              "fsl,imx7d-usdhc";
 830                                 reg = <0x30b50000 0x10000>;
 831                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 832                                 clocks = <&clk IMX8MQ_CLK_DUMMY>,
 833                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 834                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 835                                 clock-names = "ipg", "ahb", "per";
 836                                 fsl,tuning-start-tap = <20>;
 837                                 fsl,tuning-step = <2>;
 838                                 bus-width = <4>;
 839                                 status = "disabled";
 840                         };
 841
 842                         qspi0: spi@30bb0000 {
 843                                 #address-cells = <1>;
 844                                 #size-cells = <0>;
 845                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
 846                                 reg = <0x30bb0000 0x10000>,
 847                                       <0x08000000 0x10000000>;
 848                                 reg-names = "QuadSPI", "QuadSPI-memory";
 849                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 850                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
 851                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
 852                                 clock-names = "qspi_en", "qspi";
 853                                 status = "disabled";
 854                         };
 855
 856                         sdma1: sdma@30bd0000 {
 857                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 858                                 reg = <0x30bd0000 0x10000>;
 859                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 860                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
 861                                          <&clk IMX8MQ_CLK_AHB>;
 862                                 clock-names = "ipg", "ahb";
 863                                 #dma-cells = <3>;
 864                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 865                         };
 866
 867                         fec1: ethernet@30be0000 {
 868                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
 869                                 reg = <0x30be0000 0x10000>;
 870                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 871                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 872                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 873                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
 874                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
 875                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
 876                                          <&clk IMX8MQ_CLK_ENET_REF>,
 877                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
 878                                 clock-names = "ipg", "ahb", "ptp",
 879                                               "enet_clk_ref", "enet_out";
 880                                 fsl,num-tx-queues = <3>;
 881                                 fsl,num-rx-queues = <3>;
 882                                 status = "disabled";
 883                         };
 884                 };
 885
 886                 bus@32c00000 { /* AIPS4 */
 887                         compatible = "fsl,imx8mq-aips-bus", "simple-bus";
 888                         #address-cells = <1>;
 889                         #size-cells = <1>;
 890                         ranges = <0x32c00000 0x32c00000 0x400000>;
 891
 892                         irqsteer: interrupt-controller@32e2d000 {
 893                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
 894                                 reg = <0x32e2d000 0x1000>;
 895                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 896                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
 897                                 clock-names = "ipg";
 898                                 fsl,channel = <0>;
 899                                 fsl,num-irqs = <64>;
 900                                 interrupt-controller;
 901                                 #interrupt-cells = <1>;
 902                         };
 903                 };
 904
 905                 gpu: gpu@38000000 {
 906                         compatible = "vivante,gc";
 907                         reg = <0x38000000 0x40000>;
 908                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 909                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 910                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 911                                  <&clk IMX8MQ_CLK_GPU_AXI>,
 912                                  <&clk IMX8MQ_CLK_GPU_AHB>;
 913                         clock-names = "core", "shader", "bus", "reg";
 914                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
 915                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
 916                                           <&clk IMX8MQ_CLK_GPU_AXI>,
 917                                           <&clk IMX8MQ_CLK_GPU_AHB>,
 918                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
 919                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
 920                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 921                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 922                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
 923                                                  <&clk IMX8MQ_GPU_PLL>;
 924                         assigned-clock-rates = <800000000>, <800000000>,
 925                                                <800000000>, <800000000>, <0>;
 926                         power-domains = <&pgc_gpu>;
 927                 };
 928
 929                 usb_dwc3_0: usb@38100000 {
 930                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
 931                         reg = <0x38100000 0x10000>;
 932                         clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
 933                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
 934                                  <&clk IMX8MQ_CLK_32K>;
 935                         clock-names = "bus_early", "ref", "suspend";
 936                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 937                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
 938                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
 939                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
 940                         assigned-clock-rates = <500000000>, <100000000>;
 941                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 942                         phys = <&usb3_phy0>, <&usb3_phy0>;
 943                         phy-names = "usb2-phy", "usb3-phy";
 944                         power-domains = <&pgc_otg1>;
 945                         usb3-resume-missing-cas;
 946                         status = "disabled";
 947                 };
 948
 949                 usb3_phy0: usb-phy@381f0040 {
 950                         compatible = "fsl,imx8mq-usb-phy";
 951                         reg = <0x381f0040 0x40>;
 952                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
 953                         clock-names = "phy";
 954                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
 955                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
 956                         assigned-clock-rates = <100000000>;
 957                         #phy-cells = <0>;
 958                         status = "disabled";
 959                 };
 960
 961                 usb_dwc3_1: usb@38200000 {
 962                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
 963                         reg = <0x38200000 0x10000>;
 964                         clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
 965                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
 966                                  <&clk IMX8MQ_CLK_32K>;
 967                         clock-names = "bus_early", "ref", "suspend";
 968                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
 969                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
 970                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
 971                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
 972                         assigned-clock-rates = <500000000>, <100000000>;
 973                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 974                         phys = <&usb3_phy1>, <&usb3_phy1>;
 975                         phy-names = "usb2-phy", "usb3-phy";
 976                         power-domains = <&pgc_otg2>;
 977                         usb3-resume-missing-cas;
 978                         status = "disabled";
 979                 };
 980
 981                 usb3_phy1: usb-phy@382f0040 {
 982                         compatible = "fsl,imx8mq-usb-phy";
 983                         reg = <0x382f0040 0x40>;
 984                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
 985                         clock-names = "phy";
 986                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
 987                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
 988                         assigned-clock-rates = <100000000>;
 989                         #phy-cells = <0>;
 990                         status = "disabled";
 991                 };
 992
 993                 pcie0: pcie@33800000 {
 994                         compatible = "fsl,imx8mq-pcie";
 995                         reg = <0x33800000 0x400000>,
 996                               <0x1ff00000 0x80000>;
 997                         reg-names = "dbi", "config";
 998                         #address-cells = <3>;
 999                         #size-cells = <2>;
1000                         device_type = "pci";
1001                         bus-range = <0x00 0xff>;
1002                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1003                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1004                         num-lanes = <1>;
1005                         num-viewport = <4>;
1006                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1007                         interrupt-names = "msi";
1008                         #interrupt-cells = <1>;
1009                         interrupt-map-mask = <0 0 0 0x7>;
1010                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1011                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1012                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1013                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1014                         fsl,max-link-speed = <2>;
1015                         power-domains = <&pgc_pcie>;
1016                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1017                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1018                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1019                         reset-names = "pciephy", "apps", "turnoff";
1020                         status = "disabled";
1021                 };
1022
1023                 pcie1: pcie@33c00000 {
1024                         compatible = "fsl,imx8mq-pcie";
1025                         reg = <0x33c00000 0x400000>,
1026                               <0x27f00000 0x80000>;
1027                         reg-names = "dbi", "config";
1028                         #address-cells = <3>;
1029                         #size-cells = <2>;
1030                         device_type = "pci";
1031                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1032                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1033                         num-lanes = <1>;
1034                         num-viewport = <4>;
1035                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1036                         interrupt-names = "msi";
1037                         #interrupt-cells = <1>;
1038                         interrupt-map-mask = <0 0 0 0x7>;
1039                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1040                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1041                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1042                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1043                         fsl,max-link-speed = <2>;
1044                         power-domains = <&pgc_pcie>;
1045                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1046                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1047                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1048                         reset-names = "pciephy", "apps", "turnoff";
1049                         status = "disabled";
1050                 };
1051
1052                 gic: interrupt-controller@38800000 {
1053                         compatible = "arm,gic-v3";
1054                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1055                               <0x38880000 0xc0000>,     /* GICR */
1056                               <0x31000000 0x2000>,      /* GICC */
1057                               <0x31010000 0x2000>,      /* GICV */
1058                               <0x31020000 0x2000>;      /* GICH */
1059                         #interrupt-cells = <3>;
1060                         interrupt-controller;
1061                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1062                         interrupt-parent = <&gic>;
1063                 };
1064
1065                 ddr-pmu@3d800000 {
1066                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1067                         reg = <0x3d800000 0x400000>;
1068                         interrupt-parent = <&gic>;
1069                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1070                 };
1071         };
1072 };