arch/arm64/boot/dts/freescale/imx8mm.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <dt-bindings/clock/imx8mm-clock.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/input/input.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 #include "imx8mm-pinfunc.h"
  13
  14 / {
  15         compatible = "fsl,imx8mm";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 ethernet0 = &fec1;
  22                 i2c0 = &i2c1;
  23                 i2c1 = &i2c2;
  24                 i2c2 = &i2c3;
  25                 i2c3 = &i2c4;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 spi0 = &ecspi1;
  31                 spi1 = &ecspi2;
  32                 spi2 = &ecspi3;
  33                 mmc0 = &usdhc1;
  34                 mmc1 = &usdhc2;
  35                 mmc2 = &usdhc3;
  36                 gpio0 = &gpio1;
  37                 gpio1 = &gpio2;
  38                 gpio2 = &gpio3;
  39                 gpio3 = &gpio4;
  40                 gpio4 = &gpio5;
  41         };
  42
  43         cpus {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 idle-states {
  48                         entry-method = "psci";
  49
  50                         cpu_pd_wait: cpu-pd-wait {
  51                                 compatible = "arm,idle-state";
  52                                 arm,psci-suspend-param = <0x0010033>;
  53                                 local-timer-stop;
  54                                 entry-latency-us = <1000>;
  55                                 exit-latency-us = <700>;
  56                                 min-residency-us = <2700>;
  57                         };
  58                 };
  59
  60                 A53_0: cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         reg = <0x0>;
  64                         clock-latency = <61036>; /* two CLK32 periods */
  65                         clocks = <&clk IMX8MM_CLK_ARM>;
  66                         enable-method = "psci";
  67                         next-level-cache = <&A53_L2>;
  68                         operating-points-v2 = <&a53_opp_table>;
  69                         nvmem-cells = <&cpu_speed_grade>;
  70                         nvmem-cell-names = "speed_grade";
  71                         cpu-idle-states = <&cpu_pd_wait>;
  72                 };
  73
  74                 A53_1: cpu@1 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a53";
  77                         reg = <0x1>;
  78                         clock-latency = <61036>; /* two CLK32 periods */
  79                         clocks = <&clk IMX8MM_CLK_ARM>;
  80                         enable-method = "psci";
  81                         next-level-cache = <&A53_L2>;
  82                         operating-points-v2 = <&a53_opp_table>;
  83                         cpu-idle-states = <&cpu_pd_wait>;
  84                 };
  85
  86                 A53_2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53";
  89                         reg = <0x2>;
  90                         clock-latency = <61036>; /* two CLK32 periods */
  91                         clocks = <&clk IMX8MM_CLK_ARM>;
  92                         enable-method = "psci";
  93                         next-level-cache = <&A53_L2>;
  94                         operating-points-v2 = <&a53_opp_table>;
  95                         cpu-idle-states = <&cpu_pd_wait>;
  96                 };
  97
  98                 A53_3: cpu@3 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a53";
 101                         reg = <0x3>;
 102                         clock-latency = <61036>; /* two CLK32 periods */
 103                         clocks = <&clk IMX8MM_CLK_ARM>;
 104                         enable-method = "psci";
 105                         next-level-cache = <&A53_L2>;
 106                         operating-points-v2 = <&a53_opp_table>;
 107                         cpu-idle-states = <&cpu_pd_wait>;
 108                 };
 109
 110                 A53_L2: l2-cache0 {
 111                         compatible = "cache";
 112                 };
 113         };
 114
 115         a53_opp_table: opp-table {
 116                 compatible = "operating-points-v2";
 117                 opp-shared;
 118
 119                 opp-1200000000 {
 120                         opp-hz = /bits/ 64 <1200000000>;
 121                         opp-microvolt = <850000>;
 122                         opp-supported-hw = <0xe>, <0x7>;
 123                         clock-latency-ns = <150000>;
 124                         opp-suspend;
 125                 };
 126
 127                 opp-1600000000 {
 128                         opp-hz = /bits/ 64 <1600000000>;
 129                         opp-microvolt = <900000>;
 130                         opp-supported-hw = <0xc>, <0x7>;
 131                         clock-latency-ns = <150000>;
 132                         opp-suspend;
 133                 };
 134
 135                 opp-1800000000 {
 136                         opp-hz = /bits/ 64 <1800000000>;
 137                         opp-microvolt = <1000000>;
 138                         opp-supported-hw = <0x8>, <0x3>;
 139                         clock-latency-ns = <150000>;
 140                         opp-suspend;
 141                 };
 142         };
 143
 144         memory@40000000 {
 145                 device_type = "memory";
 146                 reg = <0x0 0x40000000 0 0x80000000>;
 147         };
 148
 149         osc_32k: clock-osc-32k {
 150                 compatible = "fixed-clock";
 151                 #clock-cells = <0>;
 152                 clock-frequency = <32768>;
 153                 clock-output-names = "osc_32k";
 154         };
 155
 156         osc_24m: clock-osc-24m {
 157                 compatible = "fixed-clock";
 158                 #clock-cells = <0>;
 159                 clock-frequency = <24000000>;
 160                 clock-output-names = "osc_24m";
 161         };
 162
 163         clk_ext1: clock-ext1 {
 164                 compatible = "fixed-clock";
 165                 #clock-cells = <0>;
 166                 clock-frequency = <133000000>;
 167                 clock-output-names = "clk_ext1";
 168         };
 169
 170         clk_ext2: clock-ext2 {
 171                 compatible = "fixed-clock";
 172                 #clock-cells = <0>;
 173                 clock-frequency = <133000000>;
 174                 clock-output-names = "clk_ext2";
 175         };
 176
 177         clk_ext3: clock-ext3 {
 178                 compatible = "fixed-clock";
 179                 #clock-cells = <0>;
 180                 clock-frequency = <133000000>;
 181                 clock-output-names = "clk_ext3";
 182         };
 183
 184         clk_ext4: clock-ext4 {
 185                 compatible = "fixed-clock";
 186                 #clock-cells = <0>;
 187                 clock-frequency= <133000000>;
 188                 clock-output-names = "clk_ext4";
 189         };
 190
 191         psci {
 192                 compatible = "arm,psci-1.0";
 193                 method = "smc";
 194         };
 195
 196         pmu {
 197                 compatible = "arm,armv8-pmuv3";
 198                 interrupts = <GIC_PPI 7
 199                              (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
 200                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 201         };
 202
 203         timer {
 204                 compatible = "arm,armv8-timer";
 205                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
 206                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
 207                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
 208                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
 209                 clock-frequency = <8000000>;
 210                 arm,no-tick-in-suspend;
 211         };
 212
 213         usbphynop1: usbphynop1 {
 214                 compatible = "usb-nop-xceiv";
 215                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 216                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 217                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 218                 clock-names = "main_clk";
 219         };
 220
 221         usbphynop2: usbphynop2 {
 222                 compatible = "usb-nop-xceiv";
 223                 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 224                 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
 225                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
 226                 clock-names = "main_clk";
 227         };
 228
 229         soc@0 {
 230                 compatible = "simple-bus";
 231                 #address-cells = <1>;
 232                 #size-cells = <1>;
 233                 ranges = <0x0 0x0 0x0 0x3e000000>;
 234
 235                 aips1: bus@30000000 {
 236                         compatible = "fsl,aips-bus", "simple-bus";
 237                         #address-cells = <1>;
 238                         #size-cells = <1>;
 239                         ranges = <0x30000000 0x30000000 0x400000>;
 240
 241                         sai1: sai@30010000 {
 242                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 243                                 reg = <0x30010000 0x10000>;
 244                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 245                                 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
 246                                          <&clk IMX8MM_CLK_SAI1_ROOT>,
 247                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 248                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 249                                 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
 250                                 dma-names = "rx", "tx";
 251                                 status = "disabled";
 252                         };
 253
 254                         sai2: sai@30020000 {
 255                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 256                                 reg = <0x30020000 0x10000>;
 257                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 258                                 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
 259                                         <&clk IMX8MM_CLK_SAI2_ROOT>,
 260                                         <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 261                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 262                                 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
 263                                 dma-names = "rx", "tx";
 264                                 status = "disabled";
 265                         };
 266
 267                         sai3: sai@30030000 {
 268                                 #sound-dai-cells = <0>;
 269                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 270                                 reg = <0x30030000 0x10000>;
 271                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 272                                 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
 273                                          <&clk IMX8MM_CLK_SAI3_ROOT>,
 274                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 275                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 276                                 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
 277                                 dma-names = "rx", "tx";
 278                                 status = "disabled";
 279                         };
 280
 281                         sai5: sai@30050000 {
 282                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 283                                 reg = <0x30050000 0x10000>;
 284                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 285                                 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
 286                                          <&clk IMX8MM_CLK_SAI5_ROOT>,
 287                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 288                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 289                                 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
 290                                 dma-names = "rx", "tx";
 291                                 status = "disabled";
 292                         };
 293
 294                         sai6: sai@30060000 {
 295                                 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
 296                                 reg = <0x30060000 0x10000>;
 297                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 298                                 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
 299                                          <&clk IMX8MM_CLK_SAI6_ROOT>,
 300                                          <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
 301                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 302                                 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
 303                                 dma-names = "rx", "tx";
 304                                 status = "disabled";
 305                         };
 306
 307                         gpio1: gpio@30200000 {
 308                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 309                                 reg = <0x30200000 0x10000>;
 310                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 311                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 312                                 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
 313                                 gpio-controller;
 314                                 #gpio-cells = <2>;
 315                                 interrupt-controller;
 316                                 #interrupt-cells = <2>;
 317                                 gpio-ranges = <&iomuxc 0 10 30>;
 318                         };
 319
 320                         gpio2: gpio@30210000 {
 321                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 322                                 reg = <0x30210000 0x10000>;
 323                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 324                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 325                                 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
 326                                 gpio-controller;
 327                                 #gpio-cells = <2>;
 328                                 interrupt-controller;
 329                                 #interrupt-cells = <2>;
 330                                 gpio-ranges = <&iomuxc 0 40 21>;
 331                         };
 332
 333                         gpio3: gpio@30220000 {
 334                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 335                                 reg = <0x30220000 0x10000>;
 336                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 337                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 338                                 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
 339                                 gpio-controller;
 340                                 #gpio-cells = <2>;
 341                                 interrupt-controller;
 342                                 #interrupt-cells = <2>;
 343                                 gpio-ranges = <&iomuxc 0 61 26>;
 344                         };
 345
 346                         gpio4: gpio@30230000 {
 347                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 348                                 reg = <0x30230000 0x10000>;
 349                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 350                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 351                                 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
 352                                 gpio-controller;
 353                                 #gpio-cells = <2>;
 354                                 interrupt-controller;
 355                                 #interrupt-cells = <2>;
 356                                 gpio-ranges = <&iomuxc 0 87 32>;
 357                         };
 358
 359                         gpio5: gpio@30240000 {
 360                                 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
 361                                 reg = <0x30240000 0x10000>;
 362                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 363                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 364                                 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
 365                                 gpio-controller;
 366                                 #gpio-cells = <2>;
 367                                 interrupt-controller;
 368                                 #interrupt-cells = <2>;
 369                                 gpio-ranges = <&iomuxc 0 119 30>;
 370                         };
 371
 372                         wdog1: watchdog@30280000 {
 373                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 374                                 reg = <0x30280000 0x10000>;
 375                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 376                                 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
 377                                 status = "disabled";
 378                         };
 379
 380                         wdog2: watchdog@30290000 {
 381                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 382                                 reg = <0x30290000 0x10000>;
 383                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 384                                 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
 385                                 status = "disabled";
 386                         };
 387
 388                         wdog3: watchdog@302a0000 {
 389                                 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
 390                                 reg = <0x302a0000 0x10000>;
 391                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 392                                 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
 393                                 status = "disabled";
 394                         };
 395
 396                         sdma2: dma-controller@302c0000 {
 397                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 398                                 reg = <0x302c0000 0x10000>;
 399                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 400                                 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
 401                                          <&clk IMX8MM_CLK_SDMA2_ROOT>;
 402                                 clock-names = "ipg", "ahb";
 403                                 #dma-cells = <3>;
 404                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 405                         };
 406
 407                         sdma3: dma-controller@302b0000 {
 408                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 409                                 reg = <0x302b0000 0x10000>;
 410                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 411                                 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
 412                                  <&clk IMX8MM_CLK_SDMA3_ROOT>;
 413                                 clock-names = "ipg", "ahb";
 414                                 #dma-cells = <3>;
 415                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 416                         };
 417
 418                         iomuxc: pinctrl@30330000 {
 419                                 compatible = "fsl,imx8mm-iomuxc";
 420                                 reg = <0x30330000 0x10000>;
 421                         };
 422
 423                         gpr: iomuxc-gpr@30340000 {
 424                                 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
 425                                 reg = <0x30340000 0x10000>;
 426                         };
 427
 428                         ocotp: ocotp-ctrl@30350000 {
 429                                 compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
 430                                 reg = <0x30350000 0x10000>;
 431                                 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
 432                                 /* For nvmem subnodes */
 433                                 #address-cells = <1>;
 434                                 #size-cells = <1>;
 435
 436                                 cpu_speed_grade: speed-grade@10 {
 437                                         reg = <0x10 4>;
 438                                 };
 439                         };
 440
 441                         anatop: anatop@30360000 {
 442                                 compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
 443                                 reg = <0x30360000 0x10000>;
 444                         };
 445
 446                         snvs: snvs@30370000 {
 447                                 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
 448                                 reg = <0x30370000 0x10000>;
 449
 450                                 snvs_rtc: snvs-rtc-lp {
 451                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 452                                         regmap = <&snvs>;
 453                                         offset = <0x34>;
 454                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 455                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 456                                         clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
 457                                         clock-names = "snvs-rtc";
 458                                 };
 459
 460                                 snvs_pwrkey: snvs-powerkey {
 461                                         compatible = "fsl,sec-v4.0-pwrkey";
 462                                         regmap = <&snvs>;
 463                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 464                                         linux,keycode = <KEY_POWER>;
 465                                         wakeup-source;
 466                                         status = "disabled";
 467                                 };
 468                         };
 469
 470                         clk: clock-controller@30380000 {
 471                                 compatible = "fsl,imx8mm-ccm";
 472                                 reg = <0x30380000 0x10000>;
 473                                 #clock-cells = <1>;
 474                                 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
 475                                          <&clk_ext3>, <&clk_ext4>;
 476                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
 477                                               "clk_ext3", "clk_ext4";
 478                                 assigned-clocks = <&clk IMX8MM_CLK_NOC>,
 479                                                 <&clk IMX8MM_CLK_AUDIO_AHB>,
 480                                                 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
 481                                                 <&clk IMX8MM_SYS_PLL3>,
 482                                                 <&clk IMX8MM_VIDEO_PLL1>;
 483                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
 484                                                          <&clk IMX8MM_SYS_PLL1_800M>;
 485                                 assigned-clock-rates = <0>,
 486                                                         <400000000>,
 487                                                         <400000000>,
 488                                                         <750000000>,
 489                                                         <594000000>;
 490                         };
 491
 492                         src: reset-controller@30390000 {
 493                                 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
 494                                 reg = <0x30390000 0x10000>;
 495                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 496                                 #reset-cells = <1>;
 497                         };
 498                 };
 499
 500                 aips2: bus@30400000 {
 501                         compatible = "fsl,aips-bus", "simple-bus";
 502                         #address-cells = <1>;
 503                         #size-cells = <1>;
 504                         ranges = <0x30400000 0x30400000 0x400000>;
 505
 506                         pwm1: pwm@30660000 {
 507                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 508                                 reg = <0x30660000 0x10000>;
 509                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 510                                 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
 511                                         <&clk IMX8MM_CLK_PWM1_ROOT>;
 512                                 clock-names = "ipg", "per";
 513                                 #pwm-cells = <2>;
 514                                 status = "disabled";
 515                         };
 516
 517                         pwm2: pwm@30670000 {
 518                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 519                                 reg = <0x30670000 0x10000>;
 520                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 521                                 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
 522                                          <&clk IMX8MM_CLK_PWM2_ROOT>;
 523                                 clock-names = "ipg", "per";
 524                                 #pwm-cells = <2>;
 525                                 status = "disabled";
 526                         };
 527
 528                         pwm3: pwm@30680000 {
 529                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 530                                 reg = <0x30680000 0x10000>;
 531                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 532                                 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
 533                                          <&clk IMX8MM_CLK_PWM3_ROOT>;
 534                                 clock-names = "ipg", "per";
 535                                 #pwm-cells = <2>;
 536                                 status = "disabled";
 537                         };
 538
 539                         pwm4: pwm@30690000 {
 540                                 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
 541                                 reg = <0x30690000 0x10000>;
 542                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 543                                 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
 544                                          <&clk IMX8MM_CLK_PWM4_ROOT>;
 545                                 clock-names = "ipg", "per";
 546                                 #pwm-cells = <2>;
 547                                 status = "disabled";
 548                         };
 549
 550                         system_counter: timer@306a0000 {
 551                                 compatible = "nxp,sysctr-timer";
 552                                 reg = <0x306a0000 0x20000>;
 553                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 554                                 clocks = <&osc_24m>;
 555                                 clock-names = "per";
 556                         };
 557                 };
 558
 559                 aips3: bus@30800000 {
 560                         compatible = "fsl,aips-bus", "simple-bus";
 561                         #address-cells = <1>;
 562                         #size-cells = <1>;
 563                         ranges = <0x30800000 0x30800000 0x400000>;
 564
 565                         ecspi1: spi@30820000 {
 566                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 567                                 #address-cells = <1>;
 568                                 #size-cells = <0>;
 569                                 reg = <0x30820000 0x10000>;
 570                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 571                                 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
 572                                          <&clk IMX8MM_CLK_ECSPI1_ROOT>;
 573                                 clock-names = "ipg", "per";
 574                                 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
 575                                 dma-names = "rx", "tx";
 576                                 status = "disabled";
 577                         };
 578
 579                         ecspi2: spi@30830000 {
 580                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 581                                 #address-cells = <1>;
 582                                 #size-cells = <0>;
 583                                 reg = <0x30830000 0x10000>;
 584                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 585                                 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
 586                                          <&clk IMX8MM_CLK_ECSPI2_ROOT>;
 587                                 clock-names = "ipg", "per";
 588                                 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
 589                                 dma-names = "rx", "tx";
 590                                 status = "disabled";
 591                         };
 592
 593                         ecspi3: spi@30840000 {
 594                                 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
 595                                 #address-cells = <1>;
 596                                 #size-cells = <0>;
 597                                 reg = <0x30840000 0x10000>;
 598                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 599                                 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
 600                                          <&clk IMX8MM_CLK_ECSPI3_ROOT>;
 601                                 clock-names = "ipg", "per";
 602                                 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
 603                                 dma-names = "rx", "tx";
 604                                 status = "disabled";
 605                         };
 606
 607                         uart1: serial@30860000 {
 608                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 609                                 reg = <0x30860000 0x10000>;
 610                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 611                                 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
 612                                          <&clk IMX8MM_CLK_UART1_ROOT>;
 613                                 clock-names = "ipg", "per";
 614                                 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
 615                                 dma-names = "rx", "tx";
 616                                 status = "disabled";
 617                         };
 618
 619                         uart3: serial@30880000 {
 620                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 621                                 reg = <0x30880000 0x10000>;
 622                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 623                                 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
 624                                          <&clk IMX8MM_CLK_UART3_ROOT>;
 625                                 clock-names = "ipg", "per";
 626                                 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
 627                                 dma-names = "rx", "tx";
 628                                 status = "disabled";
 629                         };
 630
 631                         uart2: serial@30890000 {
 632                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 633                                 reg = <0x30890000 0x10000>;
 634                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 635                                 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
 636                                          <&clk IMX8MM_CLK_UART2_ROOT>;
 637                                 clock-names = "ipg", "per";
 638                                 status = "disabled";
 639                         };
 640
 641                         i2c1: i2c@30a20000 {
 642                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 643                                 #address-cells = <1>;
 644                                 #size-cells = <0>;
 645                                 reg = <0x30a20000 0x10000>;
 646                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 647                                 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
 648                                 status = "disabled";
 649                         };
 650
 651                         i2c2: i2c@30a30000 {
 652                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 653                                 #address-cells = <1>;
 654                                 #size-cells = <0>;
 655                                 reg = <0x30a30000 0x10000>;
 656                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 657                                 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
 658                                 status = "disabled";
 659                         };
 660
 661                         i2c3: i2c@30a40000 {
 662                                 #address-cells = <1>;
 663                                 #size-cells = <0>;
 664                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 665                                 reg = <0x30a40000 0x10000>;
 666                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 667                                 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
 668                                 status = "disabled";
 669                         };
 670
 671                         i2c4: i2c@30a50000 {
 672                                 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
 673                                 #address-cells = <1>;
 674                                 #size-cells = <0>;
 675                                 reg = <0x30a50000 0x10000>;
 676                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 677                                 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
 678                                 status = "disabled";
 679                         };
 680
 681                         uart4: serial@30a60000 {
 682                                 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
 683                                 reg = <0x30a60000 0x10000>;
 684                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 685                                 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
 686                                          <&clk IMX8MM_CLK_UART4_ROOT>;
 687                                 clock-names = "ipg", "per";
 688                                 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
 689                                 dma-names = "rx", "tx";
 690                                 status = "disabled";
 691                         };
 692
 693                         usdhc1: mmc@30b40000 {
 694                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 695                                 reg = <0x30b40000 0x10000>;
 696                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 697                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 698                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 699                                          <&clk IMX8MM_CLK_USDHC1_ROOT>;
 700                                 clock-names = "ipg", "ahb", "per";
 701                                 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
 702                                 assigned-clock-rates = <400000000>;
 703                                 fsl,tuning-start-tap = <20>;
 704                                 fsl,tuning-step= <2>;
 705                                 bus-width = <4>;
 706                                 status = "disabled";
 707                         };
 708
 709                         usdhc2: mmc@30b50000 {
 710                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 711                                 reg = <0x30b50000 0x10000>;
 712                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 713                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 714                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 715                                          <&clk IMX8MM_CLK_USDHC2_ROOT>;
 716                                 clock-names = "ipg", "ahb", "per";
 717                                 fsl,tuning-start-tap = <20>;
 718                                 fsl,tuning-step= <2>;
 719                                 bus-width = <4>;
 720                                 status = "disabled";
 721                         };
 722
 723                         usdhc3: mmc@30b60000 {
 724                                 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 725                                 reg = <0x30b60000 0x10000>;
 726                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 727                                 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
 728                                          <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
 729                                          <&clk IMX8MM_CLK_USDHC3_ROOT>;
 730                                 clock-names = "ipg", "ahb", "per";
 731                                 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
 732                                 assigned-clock-rates = <400000000>;
 733                                 fsl,tuning-start-tap = <20>;
 734                                 fsl,tuning-step= <2>;
 735                                 bus-width = <4>;
 736                                 status = "disabled";
 737                         };
 738
 739                         sdma1: dma-controller@30bd0000 {
 740                                 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
 741                                 reg = <0x30bd0000 0x10000>;
 742                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 743                                 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
 744                                          <&clk IMX8MM_CLK_SDMA1_ROOT>;
 745                                 clock-names = "ipg", "ahb";
 746                                 #dma-cells = <3>;
 747                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 748                         };
 749
 750                         fec1: ethernet@30be0000 {
 751                                 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
 752                                 reg = <0x30be0000 0x10000>;
 753                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 754                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 755                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 756                                 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
 757                                          <&clk IMX8MM_CLK_ENET1_ROOT>,
 758                                          <&clk IMX8MM_CLK_ENET_TIMER>,
 759                                          <&clk IMX8MM_CLK_ENET_REF>,
 760                                          <&clk IMX8MM_CLK_ENET_PHY_REF>;
 761                                 clock-names = "ipg", "ahb", "ptp",
 762                                               "enet_clk_ref", "enet_out";
 763                                 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
 764                                                   <&clk IMX8MM_CLK_ENET_TIMER>,
 765                                                   <&clk IMX8MM_CLK_ENET_REF>,
 766                                                   <&clk IMX8MM_CLK_ENET_TIMER>;
 767                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
 768                                                          <&clk IMX8MM_SYS_PLL2_100M>,
 769                                                          <&clk IMX8MM_SYS_PLL2_125M>;
 770                                 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
 771                                 fsl,num-tx-queues = <3>;
 772                                 fsl,num-rx-queues = <3>;
 773                                 status = "disabled";
 774                         };
 775
 776                 };
 777
 778                 aips4: bus@32c00000 {
 779                         compatible = "fsl,aips-bus", "simple-bus";
 780                         #address-cells = <1>;
 781                         #size-cells = <1>;
 782                         ranges = <0x32c00000 0x32c00000 0x400000>;
 783
 784                         usbotg1: usb@32e40000 {
 785                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 786                                 reg = <0x32e40000 0x200>;
 787                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 788                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 789                                 clock-names = "usb1_ctrl_root_clk";
 790                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
 791                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 792                                 fsl,usbphy = <&usbphynop1>;
 793                                 fsl,usbmisc = <&usbmisc1 0>;
 794                                 status = "disabled";
 795                         };
 796
 797                         usbmisc1: usbmisc@32e40200 {
 798                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 799                                 #index-cells = <1>;
 800                                 reg = <0x32e40200 0x200>;
 801                         };
 802
 803                         usbotg2: usb@32e50000 {
 804                                 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 805                                 reg = <0x32e50000 0x200>;
 806                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
 808                                 clock-names = "usb1_ctrl_root_clk";
 809                                 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
 810                                 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
 811                                 fsl,usbphy = <&usbphynop2>;
 812                                 fsl,usbmisc = <&usbmisc2 0>;
 813                                 status = "disabled";
 814                         };
 815
 816                         usbmisc2: usbmisc@32e50200 {
 817                                 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
 818                                 #index-cells = <1>;
 819                                 reg = <0x32e50200 0x200>;
 820                         };
 821
 822                 };
 823
 824                 dma_apbh: dma-controller@33000000 {
 825                         compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
 826                         reg = <0x33000000 0x2000>;
 827                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 828                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 829                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 830                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 831                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 832                         #dma-cells = <1>;
 833                         dma-channels = <4>;
 834                         clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 835                 };
 836
 837                 gpmi: nand-controller@33002000{
 838                         compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
 839                         #address-cells = <1>;
 840                         #size-cells = <1>;
 841                         reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
 842                         reg-names = "gpmi-nand", "bch";
 843                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 844                         interrupt-names = "bch";
 845                         clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
 846                                  <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
 847                         clock-names = "gpmi_io", "gpmi_bch_apb";
 848                         dmas = <&dma_apbh 0>;
 849                         dma-names = "rx-tx";
 850                         status = "disabled";
 851                 };
 852
 853                 gic: interrupt-controller@38800000 {
 854                         compatible = "arm,gic-v3";
 855                         reg = <0x38800000 0x10000>, /* GIC Dist */
 856                               <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
 857                         #interrupt-cells = <3>;
 858                         interrupt-controller;
 859                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 860                 };
 861
 862                 ddr-pmu@3d800000 {
 863                         compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
 864                         reg = <0x3d800000 0x400000>;
 865                         interrupt-parent = <&gic>;
 866                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 867                 };
 868         };
 869 };