1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /memreserve/ 0x80000000 0x00010000;
13 compatible = "fsl,lx2160a";
14 interrupt-parent = <&gic>;
22 // 8 clusters having 2 Cortex-A72 cores each
25 compatible = "arm,cortex-a72";
26 enable-method = "psci";
28 clocks = <&clockgen 1 0>;
29 d-cache-size = <0x8000>;
30 d-cache-line-size = <64>;
32 i-cache-size = <0xC000>;
33 i-cache-line-size = <64>;
35 next-level-cache = <&cluster0_l2>;
40 compatible = "arm,cortex-a72";
41 enable-method = "psci";
43 clocks = <&clockgen 1 0>;
44 d-cache-size = <0x8000>;
45 d-cache-line-size = <64>;
47 i-cache-size = <0xC000>;
48 i-cache-line-size = <64>;
50 next-level-cache = <&cluster0_l2>;
55 compatible = "arm,cortex-a72";
56 enable-method = "psci";
58 clocks = <&clockgen 1 1>;
59 d-cache-size = <0x8000>;
60 d-cache-line-size = <64>;
62 i-cache-size = <0xC000>;
63 i-cache-line-size = <64>;
65 next-level-cache = <&cluster1_l2>;
70 compatible = "arm,cortex-a72";
71 enable-method = "psci";
73 clocks = <&clockgen 1 1>;
74 d-cache-size = <0x8000>;
75 d-cache-line-size = <64>;
77 i-cache-size = <0xC000>;
78 i-cache-line-size = <64>;
80 next-level-cache = <&cluster1_l2>;
85 compatible = "arm,cortex-a72";
86 enable-method = "psci";
88 clocks = <&clockgen 1 2>;
89 d-cache-size = <0x8000>;
90 d-cache-line-size = <64>;
92 i-cache-size = <0xC000>;
93 i-cache-line-size = <64>;
95 next-level-cache = <&cluster2_l2>;
100 compatible = "arm,cortex-a72";
101 enable-method = "psci";
103 clocks = <&clockgen 1 2>;
104 d-cache-size = <0x8000>;
105 d-cache-line-size = <64>;
106 d-cache-sets = <128>;
107 i-cache-size = <0xC000>;
108 i-cache-line-size = <64>;
109 i-cache-sets = <192>;
110 next-level-cache = <&cluster2_l2>;
115 compatible = "arm,cortex-a72";
116 enable-method = "psci";
118 clocks = <&clockgen 1 3>;
119 d-cache-size = <0x8000>;
120 d-cache-line-size = <64>;
121 d-cache-sets = <128>;
122 i-cache-size = <0xC000>;
123 i-cache-line-size = <64>;
124 i-cache-sets = <192>;
125 next-level-cache = <&cluster3_l2>;
130 compatible = "arm,cortex-a72";
131 enable-method = "psci";
133 clocks = <&clockgen 1 3>;
134 d-cache-size = <0x8000>;
135 d-cache-line-size = <64>;
136 d-cache-sets = <128>;
137 i-cache-size = <0xC000>;
138 i-cache-line-size = <64>;
139 i-cache-sets = <192>;
140 next-level-cache = <&cluster3_l2>;
145 compatible = "arm,cortex-a72";
146 enable-method = "psci";
148 clocks = <&clockgen 1 4>;
149 d-cache-size = <0x8000>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <128>;
152 i-cache-size = <0xC000>;
153 i-cache-line-size = <64>;
154 i-cache-sets = <192>;
155 next-level-cache = <&cluster4_l2>;
160 compatible = "arm,cortex-a72";
161 enable-method = "psci";
163 clocks = <&clockgen 1 4>;
164 d-cache-size = <0x8000>;
165 d-cache-line-size = <64>;
166 d-cache-sets = <128>;
167 i-cache-size = <0xC000>;
168 i-cache-line-size = <64>;
169 i-cache-sets = <192>;
170 next-level-cache = <&cluster4_l2>;
175 compatible = "arm,cortex-a72";
176 enable-method = "psci";
178 clocks = <&clockgen 1 5>;
179 d-cache-size = <0x8000>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <128>;
182 i-cache-size = <0xC000>;
183 i-cache-line-size = <64>;
184 i-cache-sets = <192>;
185 next-level-cache = <&cluster5_l2>;
190 compatible = "arm,cortex-a72";
191 enable-method = "psci";
193 clocks = <&clockgen 1 5>;
194 d-cache-size = <0x8000>;
195 d-cache-line-size = <64>;
196 d-cache-sets = <128>;
197 i-cache-size = <0xC000>;
198 i-cache-line-size = <64>;
199 i-cache-sets = <192>;
200 next-level-cache = <&cluster5_l2>;
205 compatible = "arm,cortex-a72";
206 enable-method = "psci";
208 clocks = <&clockgen 1 6>;
209 d-cache-size = <0x8000>;
210 d-cache-line-size = <64>;
211 d-cache-sets = <128>;
212 i-cache-size = <0xC000>;
213 i-cache-line-size = <64>;
214 i-cache-sets = <192>;
215 next-level-cache = <&cluster6_l2>;
220 compatible = "arm,cortex-a72";
221 enable-method = "psci";
223 clocks = <&clockgen 1 6>;
224 d-cache-size = <0x8000>;
225 d-cache-line-size = <64>;
226 d-cache-sets = <128>;
227 i-cache-size = <0xC000>;
228 i-cache-line-size = <64>;
229 i-cache-sets = <192>;
230 next-level-cache = <&cluster6_l2>;
235 compatible = "arm,cortex-a72";
236 enable-method = "psci";
238 clocks = <&clockgen 1 7>;
239 d-cache-size = <0x8000>;
240 d-cache-line-size = <64>;
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000>;
243 i-cache-line-size = <64>;
244 i-cache-sets = <192>;
245 next-level-cache = <&cluster7_l2>;
250 compatible = "arm,cortex-a72";
251 enable-method = "psci";
253 clocks = <&clockgen 1 7>;
254 d-cache-size = <0x8000>;
255 d-cache-line-size = <64>;
256 d-cache-sets = <128>;
257 i-cache-size = <0xC000>;
258 i-cache-line-size = <64>;
259 i-cache-sets = <192>;
260 next-level-cache = <&cluster7_l2>;
263 cluster0_l2: l2-cache0 {
264 compatible = "cache";
265 cache-size = <0x100000>;
266 cache-line-size = <64>;
271 cluster1_l2: l2-cache1 {
272 compatible = "cache";
273 cache-size = <0x100000>;
274 cache-line-size = <64>;
279 cluster2_l2: l2-cache2 {
280 compatible = "cache";
281 cache-size = <0x100000>;
282 cache-line-size = <64>;
287 cluster3_l2: l2-cache3 {
288 compatible = "cache";
289 cache-size = <0x100000>;
290 cache-line-size = <64>;
295 cluster4_l2: l2-cache4 {
296 compatible = "cache";
297 cache-size = <0x100000>;
298 cache-line-size = <64>;
303 cluster5_l2: l2-cache5 {
304 compatible = "cache";
305 cache-size = <0x100000>;
306 cache-line-size = <64>;
311 cluster6_l2: l2-cache6 {
312 compatible = "cache";
313 cache-size = <0x100000>;
314 cache-line-size = <64>;
319 cluster7_l2: l2-cache7 {
320 compatible = "cache";
321 cache-size = <0x100000>;
322 cache-line-size = <64>;
328 gic: interrupt-controller@6000000 {
329 compatible = "arm,gic-v3";
330 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
331 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
333 <0x0 0x0c0c0000 0 0x2000>, // GICC
334 <0x0 0x0c0d0000 0 0x1000>, // GICH
335 <0x0 0x0c0e0000 0 0x20000>; // GICV
336 #interrupt-cells = <3>;
337 #address-cells = <2>;
340 interrupt-controller;
341 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
343 its: gic-its@6020000 {
344 compatible = "arm,gic-v3-its";
346 reg = <0x0 0x6020000 0 0x20000>;
351 compatible = "arm,armv8-timer";
352 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
359 compatible = "arm,cortex-a72-pmu";
360 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
364 compatible = "arm,psci-0.2";
369 // DRAM space - 1, size : 2 GB DRAM
370 device_type = "memory";
371 reg = <0x00000000 0x80000000 0 0x80000000>;
374 ddr1: memory-controller@1080000 {
375 compatible = "fsl,qoriq-memory-controller";
376 reg = <0x0 0x1080000 0x0 0x1000>;
377 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
381 ddr2: memory-controller@1090000 {
382 compatible = "fsl,qoriq-memory-controller";
383 reg = <0x0 0x1090000 0x0 0x1000>;
384 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
388 // One clock unit-sysclk node which bootloader require during DT fix-up
390 compatible = "fixed-clock";
392 clock-frequency = <100000000>; // fixed up by bootloader
393 clock-output-names = "sysclk";
397 compatible = "simple-bus";
398 #address-cells = <2>;
401 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
403 crypto: crypto@8000000 {
404 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
406 #address-cells = <1>;
408 ranges = <0x0 0x00 0x8000000 0x100000>;
409 reg = <0x00 0x8000000 0x0 0x100000>;
410 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
415 compatible = "fsl,sec-v5.0-job-ring",
416 "fsl,sec-v4.0-job-ring";
417 reg = <0x10000 0x10000>;
418 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
422 compatible = "fsl,sec-v5.0-job-ring",
423 "fsl,sec-v4.0-job-ring";
424 reg = <0x20000 0x10000>;
425 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
429 compatible = "fsl,sec-v5.0-job-ring",
430 "fsl,sec-v4.0-job-ring";
431 reg = <0x30000 0x10000>;
432 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
436 compatible = "fsl,sec-v5.0-job-ring",
437 "fsl,sec-v4.0-job-ring";
438 reg = <0x40000 0x10000>;
439 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
443 clockgen: clock-controller@1300000 {
444 compatible = "fsl,lx2160a-clockgen";
445 reg = <0 0x1300000 0 0xa0000>;
450 dcfg: syscon@1e00000 {
451 compatible = "fsl,lx2160a-dcfg", "syscon";
452 reg = <0x0 0x1e00000 0x0 0x10000>;
457 compatible = "fsl,vf610-i2c";
458 #address-cells = <1>;
460 reg = <0x0 0x2000000 0x0 0x10000>;
461 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&clockgen 4 7>;
464 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
469 compatible = "fsl,vf610-i2c";
470 #address-cells = <1>;
472 reg = <0x0 0x2010000 0x0 0x10000>;
473 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clockgen 4 7>;
480 compatible = "fsl,vf610-i2c";
481 #address-cells = <1>;
483 reg = <0x0 0x2020000 0x0 0x10000>;
484 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&clockgen 4 7>;
491 compatible = "fsl,vf610-i2c";
492 #address-cells = <1>;
494 reg = <0x0 0x2030000 0x0 0x10000>;
495 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&clockgen 4 7>;
502 compatible = "fsl,vf610-i2c";
503 #address-cells = <1>;
505 reg = <0x0 0x2040000 0x0 0x10000>;
506 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&clockgen 4 7>;
509 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
514 compatible = "fsl,vf610-i2c";
515 #address-cells = <1>;
517 reg = <0x0 0x2050000 0x0 0x10000>;
518 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&clockgen 4 7>;
525 compatible = "fsl,vf610-i2c";
526 #address-cells = <1>;
528 reg = <0x0 0x2060000 0x0 0x10000>;
529 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&clockgen 4 7>;
536 compatible = "fsl,vf610-i2c";
537 #address-cells = <1>;
539 reg = <0x0 0x2070000 0x0 0x10000>;
540 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&clockgen 4 7>;
547 compatible = "nxp,lx2160a-fspi";
548 #address-cells = <1>;
550 reg = <0x0 0x20c0000 0x0 0x10000>,
551 <0x0 0x20000000 0x0 0x10000000>;
552 reg-names = "fspi_base", "fspi_mmap";
553 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
555 clock-names = "fspi_en", "fspi";
559 esdhc0: esdhc@2140000 {
560 compatible = "fsl,esdhc";
561 reg = <0x0 0x2140000 0x0 0x10000>;
562 interrupts = <0 28 0x4>; /* Level high type */
563 clocks = <&clockgen 4 1>;
564 voltage-ranges = <1800 1800 3300 3300>;
571 esdhc1: esdhc@2150000 {
572 compatible = "fsl,esdhc";
573 reg = <0x0 0x2150000 0x0 0x10000>;
574 interrupts = <0 63 0x4>; /* Level high type */
575 clocks = <&clockgen 4 1>;
576 voltage-ranges = <1800 1800 3300 3300>;
584 uart0: serial@21c0000 {
585 compatible = "arm,sbsa-uart","arm,pl011";
586 reg = <0x0 0x21c0000 0x0 0x1000>;
587 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
588 current-speed = <115200>;
592 uart1: serial@21d0000 {
593 compatible = "arm,sbsa-uart","arm,pl011";
594 reg = <0x0 0x21d0000 0x0 0x1000>;
595 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
596 current-speed = <115200>;
600 uart2: serial@21e0000 {
601 compatible = "arm,sbsa-uart","arm,pl011";
602 reg = <0x0 0x21e0000 0x0 0x1000>;
603 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
604 current-speed = <115200>;
608 uart3: serial@21f0000 {
609 compatible = "arm,sbsa-uart","arm,pl011";
610 reg = <0x0 0x21f0000 0x0 0x1000>;
611 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
612 current-speed = <115200>;
616 gpio0: gpio@2300000 {
617 compatible = "fsl,qoriq-gpio";
618 reg = <0x0 0x2300000 0x0 0x10000>;
619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
623 interrupt-controller;
624 #interrupt-cells = <2>;
627 gpio1: gpio@2310000 {
628 compatible = "fsl,qoriq-gpio";
629 reg = <0x0 0x2310000 0x0 0x10000>;
630 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
634 interrupt-controller;
635 #interrupt-cells = <2>;
638 gpio2: gpio@2320000 {
639 compatible = "fsl,qoriq-gpio";
640 reg = <0x0 0x2320000 0x0 0x10000>;
641 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
645 interrupt-controller;
646 #interrupt-cells = <2>;
649 gpio3: gpio@2330000 {
650 compatible = "fsl,qoriq-gpio";
651 reg = <0x0 0x2330000 0x0 0x10000>;
652 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
656 interrupt-controller;
657 #interrupt-cells = <2>;
661 compatible = "arm,sbsa-gwdt";
662 reg = <0x0 0x23a0000 0 0x1000>,
663 <0x0 0x2390000 0 0x1000>;
664 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
669 compatible = "snps,dwc3";
670 reg = <0x0 0x3100000 0x0 0x10000>;
671 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
673 snps,quirk-frame-length-adjustment = <0x20>;
674 snps,dis_rxdet_inp3_quirk;
675 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
680 compatible = "snps,dwc3";
681 reg = <0x0 0x3110000 0x0 0x10000>;
682 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
684 snps,quirk-frame-length-adjustment = <0x20>;
685 snps,dis_rxdet_inp3_quirk;
686 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
690 smmu: iommu@5000000 {
691 compatible = "arm,mmu-500";
692 reg = <0 0x5000000 0 0x800000>;
694 #global-interrupts = <14>;
695 // global secure fault
696 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
699 // global non-secure fault
700 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
701 // combined non-secure
702 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
703 // performance counter interrupts 0-9
704 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
714 // per context interrupt, 64 interrupts
715 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
782 fsl_mc: fsl-mc@80c000000 {
783 compatible = "fsl,qoriq-mc";
784 reg = <0x00000008 0x0c000000 0 0x40>,
785 <0x00000000 0x08340000 0 0x40000>;
787 /* iommu-map property is fixed up by u-boot */
788 iommu-map = <0 &smmu 0 0>;
790 #address-cells = <3>;
794 * Region type 0x0 - MC portals
795 * Region type 0x1 - QBMAN portals
797 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
798 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
801 * Define the maximum number of MACs present on the SoC.
804 #address-cells = <1>;
808 compatible = "fsl,qoriq-mc-dpmac";
813 compatible = "fsl,qoriq-mc-dpmac";
818 compatible = "fsl,qoriq-mc-dpmac";
823 compatible = "fsl,qoriq-mc-dpmac";
828 compatible = "fsl,qoriq-mc-dpmac";
833 compatible = "fsl,qoriq-mc-dpmac";
838 compatible = "fsl,qoriq-mc-dpmac";
843 compatible = "fsl,qoriq-mc-dpmac";
848 compatible = "fsl,qoriq-mc-dpmac";
853 compatible = "fsl,qoriq-mc-dpmac";
858 compatible = "fsl,qoriq-mc-dpmac";
863 compatible = "fsl,qoriq-mc-dpmac";
868 compatible = "fsl,qoriq-mc-dpmac";
873 compatible = "fsl,qoriq-mc-dpmac";
878 compatible = "fsl,qoriq-mc-dpmac";
883 compatible = "fsl,qoriq-mc-dpmac";
888 compatible = "fsl,qoriq-mc-dpmac";
893 compatible = "fsl,qoriq-mc-dpmac";