arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-2080A family SoC.
   3  *
   4  * Copyright 2016 Freescale Semiconductor, Inc.
   5  * Copyright 2017 NXP
   6  *
   7  * Abhimanyu Saini <abhimanyu.saini@nxp.com>
   8  *
   9  * This file is dual-licensed: you can use it either under the terms
  10  * of the GPLv2 or the X11 license, at your option. Note that this dual
  11  * licensing only applies to this file, and not this project as a
  12  * whole.
  13  *
  14  *  a) This library is free software; you can redistribute it and/or
  15  *     modify it under the terms of the GNU General Public License as
  16  *     published by the Free Software Foundation; either version 2 of the
  17  *     License, or (at your option) any later version.
  18  *
  19  *     This library is distributed in the hope that it will be useful,
  20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  *     GNU General Public License for more details.
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/thermal/thermal.h>
  49 #include <dt-bindings/interrupt-controller/arm-gic.h>
  50
  51 / {
  52         compatible = "fsl,ls2080a";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 crypto = &crypto;
  59                 serial0 = &serial0;
  60                 serial1 = &serial1;
  61         };
  62
  63         cpu: cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66         };
  67
  68         memory@80000000 {
  69                 device_type = "memory";
  70                 reg = <0x00000000 0x80000000 0 0x80000000>;
  71                       /* DRAM space - 1, size : 2 GB DRAM */
  72         };
  73
  74         sysclk: sysclk {
  75                 compatible = "fixed-clock";
  76                 #clock-cells = <0>;
  77                 clock-frequency = <100000000>;
  78                 clock-output-names = "sysclk";
  79         };
  80
  81         gic: interrupt-controller@6000000 {
  82                 compatible = "arm,gic-v3";
  83                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  84                         <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
  85                         <0x0 0x0c0c0000 0 0x2000>, /* GICC */
  86                         <0x0 0x0c0d0000 0 0x1000>, /* GICH */
  87                         <0x0 0x0c0e0000 0 0x20000>; /* GICV */
  88                 #interrupt-cells = <3>;
  89                 #address-cells = <2>;
  90                 #size-cells = <2>;
  91                 ranges;
  92                 interrupt-controller;
  93                 interrupts = <1 9 0x4>;
  94
  95                 its: gic-its@6020000 {
  96                         compatible = "arm,gic-v3-its";
  97                         msi-controller;
  98                         reg = <0x0 0x6020000 0 0x20000>;
  99                 };
 100         };
 101
 102         rstcr: syscon@1e60000 {
 103                 compatible = "fsl,ls2080a-rstcr", "syscon";
 104                 reg = <0x0 0x1e60000 0x0 0x4>;
 105         };
 106
 107         reboot {
 108                 compatible ="syscon-reboot";
 109                 regmap = <&rstcr>;
 110                 offset = <0x0>;
 111                 mask = <0x2>;
 112         };
 113
 114         thermal-zones {
 115                 cpu_thermal: cpu-thermal {
 116                         polling-delay-passive = <1000>;
 117                         polling-delay = <5000>;
 118
 119                         thermal-sensors = <&tmu 4>;
 120
 121                         trips {
 122                                 cpu_alert: cpu-alert {
 123                                         temperature = <75000>;
 124                                         hysteresis = <2000>;
 125                                         type = "passive";
 126                                 };
 127                                 cpu_crit: cpu-crit {
 128                                         temperature = <85000>;
 129                                         hysteresis = <2000>;
 130                                         type = "critical";
 131                                 };
 132                         };
 133
 134                         cooling-maps {
 135                                 map0 {
 136                                         trip = <&cpu_alert>;
 137                                         cooling-device =
 138                                                 <&cpu0 THERMAL_NO_LIMIT
 139                                                 THERMAL_NO_LIMIT>;
 140                                 };
 141                                 map1 {
 142                                         trip = <&cpu_alert>;
 143                                         cooling-device =
 144                                                 <&cpu2 THERMAL_NO_LIMIT
 145                                                 THERMAL_NO_LIMIT>;
 146                                 };
 147                                 map2 {
 148                                         trip = <&cpu_alert>;
 149                                         cooling-device =
 150                                                 <&cpu4 THERMAL_NO_LIMIT
 151                                                 THERMAL_NO_LIMIT>;
 152                                 };
 153                                 map3 {
 154                                         trip = <&cpu_alert>;
 155                                         cooling-device =
 156                                                 <&cpu6 THERMAL_NO_LIMIT
 157                                                 THERMAL_NO_LIMIT>;
 158                                 };
 159                         };
 160                 };
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv8-timer";
 165                 interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
 166                              <1 14 4>, /* Physical Non-Secure PPI, active-low */
 167                              <1 11 4>, /* Virtual PPI, active-low */
 168                              <1 10 4>; /* Hypervisor PPI, active-low */
 169                 fsl,erratum-a008585;
 170         };
 171
 172         pmu {
 173                 compatible = "arm,armv8-pmuv3";
 174                 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
 175         };
 176
 177         psci {
 178                 compatible = "arm,psci-0.2";
 179                 method = "smc";
 180         };
 181
 182         soc {
 183                 compatible = "simple-bus";
 184                 #address-cells = <2>;
 185                 #size-cells = <2>;
 186                 ranges;
 187
 188                 clockgen: clocking@1300000 {
 189                         compatible = "fsl,ls2080a-clockgen";
 190                         reg = <0 0x1300000 0 0xa0000>;
 191                         #clock-cells = <2>;
 192                         clocks = <&sysclk>;
 193                 };
 194
 195                 dcfg: dcfg@1e00000 {
 196                         compatible = "fsl,ls2080a-dcfg", "syscon";
 197                         reg = <0x0 0x1e00000 0x0 0x10000>;
 198                         little-endian;
 199                 };
 200
 201                 tmu: tmu@1f80000 {
 202                         compatible = "fsl,qoriq-tmu";
 203                         reg = <0x0 0x1f80000 0x0 0x10000>;
 204                         interrupts = <0 23 0x4>;
 205                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 206                         fsl,tmu-calibration = <0x00000000 0x00000026
 207                                                0x00000001 0x0000002d
 208                                                0x00000002 0x00000032
 209                                                0x00000003 0x00000039
 210                                                0x00000004 0x0000003f
 211                                                0x00000005 0x00000046
 212                                                0x00000006 0x0000004d
 213                                                0x00000007 0x00000054
 214                                                0x00000008 0x0000005a
 215                                                0x00000009 0x00000061
 216                                                0x0000000a 0x0000006a
 217                                                0x0000000b 0x00000071
 218
 219                                                0x00010000 0x00000025
 220                                                0x00010001 0x0000002c
 221                                                0x00010002 0x00000035
 222                                                0x00010003 0x0000003d
 223                                                0x00010004 0x00000045
 224                                                0x00010005 0x0000004e
 225                                                0x00010006 0x00000057
 226                                                0x00010007 0x00000061
 227                                                0x00010008 0x0000006b
 228                                                0x00010009 0x00000076
 229
 230                                                0x00020000 0x00000029
 231                                                0x00020001 0x00000033
 232                                                0x00020002 0x0000003d
 233                                                0x00020003 0x00000049
 234                                                0x00020004 0x00000056
 235                                                0x00020005 0x00000061
 236                                                0x00020006 0x0000006d
 237
 238                                                0x00030000 0x00000021
 239                                                0x00030001 0x0000002a
 240                                                0x00030002 0x0000003c
 241                                                0x00030003 0x0000004e>;
 242                         little-endian;
 243                         #thermal-sensor-cells = <1>;
 244                 };
 245
 246                 serial0: serial@21c0500 {
 247                         compatible = "fsl,ns16550", "ns16550a";
 248                         reg = <0x0 0x21c0500 0x0 0x100>;
 249                         clocks = <&clockgen 4 3>;
 250                         interrupts = <0 32 0x4>; /* Level high type */
 251                 };
 252
 253                 serial1: serial@21c0600 {
 254                         compatible = "fsl,ns16550", "ns16550a";
 255                         reg = <0x0 0x21c0600 0x0 0x100>;
 256                         clocks = <&clockgen 4 3>;
 257                         interrupts = <0 32 0x4>; /* Level high type */
 258                 };
 259
 260                 cluster1_core0_watchdog: wdt@c000000 {
 261                         compatible = "arm,sp805-wdt", "arm,primecell";
 262                         reg = <0x0 0xc000000 0x0 0x1000>;
 263                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 264                         clock-names = "apb_pclk", "wdog_clk";
 265                 };
 266
 267                 cluster1_core1_watchdog: wdt@c010000 {
 268                         compatible = "arm,sp805-wdt", "arm,primecell";
 269                         reg = <0x0 0xc010000 0x0 0x1000>;
 270                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 271                         clock-names = "apb_pclk", "wdog_clk";
 272                 };
 273
 274                 cluster2_core0_watchdog: wdt@c100000 {
 275                         compatible = "arm,sp805-wdt", "arm,primecell";
 276                         reg = <0x0 0xc100000 0x0 0x1000>;
 277                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 278                         clock-names = "apb_pclk", "wdog_clk";
 279                 };
 280
 281                 cluster2_core1_watchdog: wdt@c110000 {
 282                         compatible = "arm,sp805-wdt", "arm,primecell";
 283                         reg = <0x0 0xc110000 0x0 0x1000>;
 284                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 285                         clock-names = "apb_pclk", "wdog_clk";
 286                 };
 287
 288                 cluster3_core0_watchdog: wdt@c200000 {
 289                         compatible = "arm,sp805-wdt", "arm,primecell";
 290                         reg = <0x0 0xc200000 0x0 0x1000>;
 291                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 292                         clock-names = "apb_pclk", "wdog_clk";
 293                 };
 294
 295                 cluster3_core1_watchdog: wdt@c210000 {
 296                         compatible = "arm,sp805-wdt", "arm,primecell";
 297                         reg = <0x0 0xc210000 0x0 0x1000>;
 298                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 299                         clock-names = "apb_pclk", "wdog_clk";
 300                 };
 301
 302                 cluster4_core0_watchdog: wdt@c300000 {
 303                         compatible = "arm,sp805-wdt", "arm,primecell";
 304                         reg = <0x0 0xc300000 0x0 0x1000>;
 305                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 306                         clock-names = "apb_pclk", "wdog_clk";
 307                 };
 308
 309                 cluster4_core1_watchdog: wdt@c310000 {
 310                         compatible = "arm,sp805-wdt", "arm,primecell";
 311                         reg = <0x0 0xc310000 0x0 0x1000>;
 312                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 313                         clock-names = "apb_pclk", "wdog_clk";
 314                 };
 315
 316                 crypto: crypto@8000000 {
 317                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 318                         fsl,sec-era = <8>;
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         ranges = <0x0 0x00 0x8000000 0x100000>;
 322                         reg = <0x00 0x8000000 0x0 0x100000>;
 323                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 324                         dma-coherent;
 325
 326                         sec_jr0: jr@10000 {
 327                                 compatible = "fsl,sec-v5.0-job-ring",
 328                                              "fsl,sec-v4.0-job-ring";
 329                                 reg        = <0x10000 0x10000>;
 330                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 331                         };
 332
 333                         sec_jr1: jr@20000 {
 334                                 compatible = "fsl,sec-v5.0-job-ring",
 335                                              "fsl,sec-v4.0-job-ring";
 336                                 reg        = <0x20000 0x10000>;
 337                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 338                         };
 339
 340                         sec_jr2: jr@30000 {
 341                                 compatible = "fsl,sec-v5.0-job-ring",
 342                                              "fsl,sec-v4.0-job-ring";
 343                                 reg        = <0x30000 0x10000>;
 344                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 345                         };
 346
 347                         sec_jr3: jr@40000 {
 348                                 compatible = "fsl,sec-v5.0-job-ring",
 349                                              "fsl,sec-v4.0-job-ring";
 350                                 reg        = <0x40000 0x10000>;
 351                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 352                         };
 353                 };
 354
 355                 fsl_mc: fsl-mc@80c000000 {
 356                         compatible = "fsl,qoriq-mc";
 357                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 358                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 359                         msi-parent = <&its>;
 360                         #address-cells = <3>;
 361                         #size-cells = <1>;
 362
 363                         /*
 364                          * Region type 0x0 - MC portals
 365                          * Region type 0x1 - QBMAN portals
 366                          */
 367                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 368                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 369
 370                         /*
 371                          * Define the maximum number of MACs present on the SoC.
 372                          */
 373                         dpmacs {
 374                                 #address-cells = <1>;
 375                                 #size-cells = <0>;
 376
 377                                 dpmac1: dpmac@1 {
 378                                         compatible = "fsl,qoriq-mc-dpmac";
 379                                         reg = <0x1>;
 380                                 };
 381
 382                                 dpmac2: dpmac@2 {
 383                                         compatible = "fsl,qoriq-mc-dpmac";
 384                                         reg = <0x2>;
 385                                 };
 386
 387                                 dpmac3: dpmac@3 {
 388                                         compatible = "fsl,qoriq-mc-dpmac";
 389                                         reg = <0x3>;
 390                                 };
 391
 392                                 dpmac4: dpmac@4 {
 393                                         compatible = "fsl,qoriq-mc-dpmac";
 394                                         reg = <0x4>;
 395                                 };
 396
 397                                 dpmac5: dpmac@5 {
 398                                         compatible = "fsl,qoriq-mc-dpmac";
 399                                         reg = <0x5>;
 400                                 };
 401
 402                                 dpmac6: dpmac@6 {
 403                                         compatible = "fsl,qoriq-mc-dpmac";
 404                                         reg = <0x6>;
 405                                 };
 406
 407                                 dpmac7: dpmac@7 {
 408                                         compatible = "fsl,qoriq-mc-dpmac";
 409                                         reg = <0x7>;
 410                                 };
 411
 412                                 dpmac8: dpmac@8 {
 413                                         compatible = "fsl,qoriq-mc-dpmac";
 414                                         reg = <0x8>;
 415                                 };
 416
 417                                 dpmac9: dpmac@9 {
 418                                         compatible = "fsl,qoriq-mc-dpmac";
 419                                         reg = <0x9>;
 420                                 };
 421
 422                                 dpmac10: dpmac@a {
 423                                         compatible = "fsl,qoriq-mc-dpmac";
 424                                         reg = <0xa>;
 425                                 };
 426
 427                                 dpmac11: dpmac@b {
 428                                         compatible = "fsl,qoriq-mc-dpmac";
 429                                         reg = <0xb>;
 430                                 };
 431
 432                                 dpmac12: dpmac@c {
 433                                         compatible = "fsl,qoriq-mc-dpmac";
 434                                         reg = <0xc>;
 435                                 };
 436
 437                                 dpmac13: dpmac@d {
 438                                         compatible = "fsl,qoriq-mc-dpmac";
 439                                         reg = <0xd>;
 440                                 };
 441
 442                                 dpmac14: dpmac@e {
 443                                         compatible = "fsl,qoriq-mc-dpmac";
 444                                         reg = <0xe>;
 445                                 };
 446
 447                                 dpmac15: dpmac@f {
 448                                         compatible = "fsl,qoriq-mc-dpmac";
 449                                         reg = <0xf>;
 450                                 };
 451
 452                                 dpmac16: dpmac@10 {
 453                                         compatible = "fsl,qoriq-mc-dpmac";
 454                                         reg = <0x10>;
 455                                 };
 456                         };
 457                 };
 458
 459                 smmu: iommu@5000000 {
 460                         compatible = "arm,mmu-500";
 461                         reg = <0 0x5000000 0 0x800000>;
 462                         #global-interrupts = <12>;
 463                         interrupts = <0 13 4>, /* global secure fault */
 464                                      <0 14 4>, /* combined secure interrupt */
 465                                      <0 15 4>, /* global non-secure fault */
 466                                      <0 16 4>, /* combined non-secure interrupt */
 467                                 /* performance counter interrupts 0-7 */
 468                                      <0 211 4>, <0 212 4>,
 469                                      <0 213 4>, <0 214 4>,
 470                                      <0 215 4>, <0 216 4>,
 471                                      <0 217 4>, <0 218 4>,
 472                                 /* per context interrupt, 64 interrupts */
 473                                      <0 146 4>, <0 147 4>,
 474                                      <0 148 4>, <0 149 4>,
 475                                      <0 150 4>, <0 151 4>,
 476                                      <0 152 4>, <0 153 4>,
 477                                      <0 154 4>, <0 155 4>,
 478                                      <0 156 4>, <0 157 4>,
 479                                      <0 158 4>, <0 159 4>,
 480                                      <0 160 4>, <0 161 4>,
 481                                      <0 162 4>, <0 163 4>,
 482                                      <0 164 4>, <0 165 4>,
 483                                      <0 166 4>, <0 167 4>,
 484                                      <0 168 4>, <0 169 4>,
 485                                      <0 170 4>, <0 171 4>,
 486                                      <0 172 4>, <0 173 4>,
 487                                      <0 174 4>, <0 175 4>,
 488                                      <0 176 4>, <0 177 4>,
 489                                      <0 178 4>, <0 179 4>,
 490                                      <0 180 4>, <0 181 4>,
 491                                      <0 182 4>, <0 183 4>,
 492                                      <0 184 4>, <0 185 4>,
 493                                      <0 186 4>, <0 187 4>,
 494                                      <0 188 4>, <0 189 4>,
 495                                      <0 190 4>, <0 191 4>,
 496                                      <0 192 4>, <0 193 4>,
 497                                      <0 194 4>, <0 195 4>,
 498                                      <0 196 4>, <0 197 4>,
 499                                      <0 198 4>, <0 199 4>,
 500                                      <0 200 4>, <0 201 4>,
 501                                      <0 202 4>, <0 203 4>,
 502                                      <0 204 4>, <0 205 4>,
 503                                      <0 206 4>, <0 207 4>,
 504                                      <0 208 4>, <0 209 4>;
 505                         mmu-masters = <&fsl_mc 0x300 0>;
 506                 };
 507
 508                 dspi: dspi@2100000 {
 509                         status = "disabled";
 510                         compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         reg = <0x0 0x2100000 0x0 0x10000>;
 514                         interrupts = <0 26 0x4>; /* Level high type */
 515                         clocks = <&clockgen 4 3>;
 516                         clock-names = "dspi";
 517                         spi-num-chipselects = <5>;
 518                         bus-num = <0>;
 519                 };
 520
 521                 esdhc: esdhc@2140000 {
 522                         status = "disabled";
 523                         compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
 524                         reg = <0x0 0x2140000 0x0 0x10000>;
 525                         interrupts = <0 28 0x4>; /* Level high type */
 526                         clocks = <&clockgen 4 1>;
 527                         voltage-ranges = <1800 1800 3300 3300>;
 528                         sdhci,auto-cmd12;
 529                         little-endian;
 530                         bus-width = <4>;
 531                 };
 532
 533                 gpio0: gpio@2300000 {
 534                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 535                         reg = <0x0 0x2300000 0x0 0x10000>;
 536                         interrupts = <0 36 0x4>; /* Level high type */
 537                         gpio-controller;
 538                         little-endian;
 539                         #gpio-cells = <2>;
 540                         interrupt-controller;
 541                         #interrupt-cells = <2>;
 542                 };
 543
 544                 gpio1: gpio@2310000 {
 545                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 546                         reg = <0x0 0x2310000 0x0 0x10000>;
 547                         interrupts = <0 36 0x4>; /* Level high type */
 548                         gpio-controller;
 549                         little-endian;
 550                         #gpio-cells = <2>;
 551                         interrupt-controller;
 552                         #interrupt-cells = <2>;
 553                 };
 554
 555                 gpio2: gpio@2320000 {
 556                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 557                         reg = <0x0 0x2320000 0x0 0x10000>;
 558                         interrupts = <0 37 0x4>; /* Level high type */
 559                         gpio-controller;
 560                         little-endian;
 561                         #gpio-cells = <2>;
 562                         interrupt-controller;
 563                         #interrupt-cells = <2>;
 564                 };
 565
 566                 gpio3: gpio@2330000 {
 567                         compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
 568                         reg = <0x0 0x2330000 0x0 0x10000>;
 569                         interrupts = <0 37 0x4>; /* Level high type */
 570                         gpio-controller;
 571                         little-endian;
 572                         #gpio-cells = <2>;
 573                         interrupt-controller;
 574                         #interrupt-cells = <2>;
 575                 };
 576
 577                 i2c0: i2c@2000000 {
 578                         status = "disabled";
 579                         compatible = "fsl,vf610-i2c";
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         reg = <0x0 0x2000000 0x0 0x10000>;
 583                         interrupts = <0 34 0x4>; /* Level high type */
 584                         clock-names = "i2c";
 585                         clocks = <&clockgen 4 3>;
 586                 };
 587
 588                 i2c1: i2c@2010000 {
 589                         status = "disabled";
 590                         compatible = "fsl,vf610-i2c";
 591                         #address-cells = <1>;
 592                         #size-cells = <0>;
 593                         reg = <0x0 0x2010000 0x0 0x10000>;
 594                         interrupts = <0 34 0x4>; /* Level high type */
 595                         clock-names = "i2c";
 596                         clocks = <&clockgen 4 3>;
 597                 };
 598
 599                 i2c2: i2c@2020000 {
 600                         status = "disabled";
 601                         compatible = "fsl,vf610-i2c";
 602                         #address-cells = <1>;
 603                         #size-cells = <0>;
 604                         reg = <0x0 0x2020000 0x0 0x10000>;
 605                         interrupts = <0 35 0x4>; /* Level high type */
 606                         clock-names = "i2c";
 607                         clocks = <&clockgen 4 3>;
 608                 };
 609
 610                 i2c3: i2c@2030000 {
 611                         status = "disabled";
 612                         compatible = "fsl,vf610-i2c";
 613                         #address-cells = <1>;
 614                         #size-cells = <0>;
 615                         reg = <0x0 0x2030000 0x0 0x10000>;
 616                         interrupts = <0 35 0x4>; /* Level high type */
 617                         clock-names = "i2c";
 618                         clocks = <&clockgen 4 3>;
 619                 };
 620
 621                 ifc: ifc@2240000 {
 622                         compatible = "fsl,ifc", "simple-bus";
 623                         reg = <0x0 0x2240000 0x0 0x20000>;
 624                         interrupts = <0 21 0x4>; /* Level high type */
 625                         little-endian;
 626                         #address-cells = <2>;
 627                         #size-cells = <1>;
 628
 629                         ranges = <0 0 0x5 0x80000000 0x08000000
 630                                   2 0 0x5 0x30000000 0x00010000
 631                                   3 0 0x5 0x20000000 0x00010000>;
 632                 };
 633
 634                 qspi: quadspi@20c0000 {
 635                         status = "disabled";
 636                         compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                         reg = <0x0 0x20c0000 0x0 0x10000>,
 640                               <0x0 0x20000000 0x0 0x10000000>;
 641                         reg-names = "QuadSPI", "QuadSPI-memory";
 642                         interrupts = <0 25 0x4>; /* Level high type */
 643                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 644                         clock-names = "qspi_en", "qspi";
 645                 };
 646
 647                 pcie1: pcie@3400000 {
 648                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
 649                                      "snps,dw-pcie";
 650                         reg-names = "regs", "config";
 651                         interrupts = <0 108 0x4>; /* Level high type */
 652                         interrupt-names = "intr";
 653                         #address-cells = <3>;
 654                         #size-cells = <2>;
 655                         device_type = "pci";
 656                         dma-coherent;
 657                         num-lanes = <4>;
 658                         bus-range = <0x0 0xff>;
 659                         msi-parent = <&its>;
 660                         #interrupt-cells = <1>;
 661                         interrupt-map-mask = <0 0 0 7>;
 662                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
 663                                         <0000 0 0 2 &gic 0 0 0 110 4>,
 664                                         <0000 0 0 3 &gic 0 0 0 111 4>,
 665                                         <0000 0 0 4 &gic 0 0 0 112 4>;
 666                 };
 667
 668                 pcie2: pcie@3500000 {
 669                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
 670                                      "snps,dw-pcie";
 671                         reg-names = "regs", "config";
 672                         interrupts = <0 113 0x4>; /* Level high type */
 673                         interrupt-names = "intr";
 674                         #address-cells = <3>;
 675                         #size-cells = <2>;
 676                         device_type = "pci";
 677                         dma-coherent;
 678                         num-lanes = <4>;
 679                         bus-range = <0x0 0xff>;
 680                         msi-parent = <&its>;
 681                         #interrupt-cells = <1>;
 682                         interrupt-map-mask = <0 0 0 7>;
 683                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
 684                                         <0000 0 0 2 &gic 0 0 0 115 4>,
 685                                         <0000 0 0 3 &gic 0 0 0 116 4>,
 686                                         <0000 0 0 4 &gic 0 0 0 117 4>;
 687                 };
 688
 689                 pcie3: pcie@3600000 {
 690                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
 691                                      "snps,dw-pcie";
 692                         reg-names = "regs", "config";
 693                         interrupts = <0 118 0x4>; /* Level high type */
 694                         interrupt-names = "intr";
 695                         #address-cells = <3>;
 696                         #size-cells = <2>;
 697                         device_type = "pci";
 698                         dma-coherent;
 699                         num-lanes = <8>;
 700                         bus-range = <0x0 0xff>;
 701                         msi-parent = <&its>;
 702                         #interrupt-cells = <1>;
 703                         interrupt-map-mask = <0 0 0 7>;
 704                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
 705                                         <0000 0 0 2 &gic 0 0 0 120 4>,
 706                                         <0000 0 0 3 &gic 0 0 0 121 4>,
 707                                         <0000 0 0 4 &gic 0 0 0 122 4>;
 708                 };
 709
 710                 pcie4: pcie@3700000 {
 711                         compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
 712                                      "snps,dw-pcie";
 713                         reg-names = "regs", "config";
 714                         interrupts = <0 123 0x4>; /* Level high type */
 715                         interrupt-names = "intr";
 716                         #address-cells = <3>;
 717                         #size-cells = <2>;
 718                         device_type = "pci";
 719                         dma-coherent;
 720                         num-lanes = <4>;
 721                         bus-range = <0x0 0xff>;
 722                         msi-parent = <&its>;
 723                         #interrupt-cells = <1>;
 724                         interrupt-map-mask = <0 0 0 7>;
 725                         interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
 726                                         <0000 0 0 2 &gic 0 0 0 125 4>,
 727                                         <0000 0 0 3 &gic 0 0 0 126 4>,
 728                                         <0000 0 0 4 &gic 0 0 0 127 4>;
 729                 };
 730
 731                 sata0: sata@3200000 {
 732                         status = "disabled";
 733                         compatible = "fsl,ls2080a-ahci";
 734                         reg = <0x0 0x3200000 0x0 0x10000>;
 735                         interrupts = <0 133 0x4>; /* Level high type */
 736                         clocks = <&clockgen 4 3>;
 737                         dma-coherent;
 738                 };
 739
 740                 sata1: sata@3210000 {
 741                         status = "disabled";
 742                         compatible = "fsl,ls2080a-ahci";
 743                         reg = <0x0 0x3210000 0x0 0x10000>;
 744                         interrupts = <0 136 0x4>; /* Level high type */
 745                         clocks = <&clockgen 4 3>;
 746                         dma-coherent;
 747                 };
 748
 749                 usb0: usb3@3100000 {
 750                         status = "disabled";
 751                         compatible = "snps,dwc3";
 752                         reg = <0x0 0x3100000 0x0 0x10000>;
 753                         interrupts = <0 80 0x4>; /* Level high type */
 754                         dr_mode = "host";
 755                         snps,quirk-frame-length-adjustment = <0x20>;
 756                         snps,dis_rxdet_inp3_quirk;
 757                 };
 758
 759                 usb1: usb3@3110000 {
 760                         status = "disabled";
 761                         compatible = "snps,dwc3";
 762                         reg = <0x0 0x3110000 0x0 0x10000>;
 763                         interrupts = <0 81 0x4>; /* Level high type */
 764                         dr_mode = "host";
 765                         snps,quirk-frame-length-adjustment = <0x20>;
 766                         snps,dis_rxdet_inp3_quirk;
 767                 };
 768
 769                 ccn@4000000 {
 770                         compatible = "arm,ccn-504";
 771                         reg = <0x0 0x04000000 0x0 0x01000000>;
 772                         interrupts = <0 12 4>;
 773                 };
 774         };
 775
 776         ddr1: memory-controller@1080000 {
 777                 compatible = "fsl,qoriq-memory-controller";
 778                 reg = <0x0 0x1080000 0x0 0x1000>;
 779                 interrupts = <0 17 0x4>;
 780                 little-endian;
 781         };
 782
 783         ddr2: memory-controller@1090000 {
 784                 compatible = "fsl,qoriq-memory-controller";
 785                 reg = <0x0 0x1090000 0x0 0x1000>;
 786                 interrupts = <0 18 0x4>;
 787                 little-endian;
 788         };
 789
 790         firmware {
 791                 optee {
 792                         compatible = "linaro,optee-tz";
 793                         method = "smc";
 794                 };
 795         };
 796 };