arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

   1 /*
   2  * Device Tree Include file for NXP Layerscape-1088A family SoC.
   3  *
   4  * Copyright 2017 NXP
   5  *
   6  * Harninder Rai <harninder.rai@nxp.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPLv2 or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This library is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This library is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/thermal/thermal.h>
  48
  49 / {
  50         compatible = "fsl,ls1088a";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         cpus {
  56                 #address-cells = <1>;
  57                 #size-cells = <0>;
  58
  59                 /* We have 2 clusters having 4 Cortex-A53 cores each */
  60                 cpu0: cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         reg = <0x0>;
  64                         clocks = <&clockgen 1 0>;
  65                         #cooling-cells = <2>;
  66                 };
  67
  68                 cpu1: cpu@1 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a53";
  71                         reg = <0x1>;
  72                         clocks = <&clockgen 1 0>;
  73                 };
  74
  75                 cpu2: cpu@2 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53";
  78                         reg = <0x2>;
  79                         clocks = <&clockgen 1 0>;
  80                 };
  81
  82                 cpu3: cpu@3 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x3>;
  86                         clocks = <&clockgen 1 0>;
  87                 };
  88
  89                 cpu4: cpu@100 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53";
  92                         reg = <0x100>;
  93                         clocks = <&clockgen 1 1>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu5: cpu@101 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53";
 100                         reg = <0x101>;
 101                         clocks = <&clockgen 1 1>;
 102                 };
 103
 104                 cpu6: cpu@102 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a53";
 107                         reg = <0x102>;
 108                         clocks = <&clockgen 1 1>;
 109                 };
 110
 111                 cpu7: cpu@103 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53";
 114                         reg = <0x103>;
 115                         clocks = <&clockgen 1 1>;
 116                 };
 117         };
 118
 119         gic: interrupt-controller@6000000 {
 120                 compatible = "arm,gic-v3";
 121                 #interrupt-cells = <3>;
 122                 interrupt-controller;
 123                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 124                       <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 125                       <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 126                       <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 127                       <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 128                 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
 129         };
 130
 131         timer {
 132                 compatible = "arm,armv8-timer";
 133                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 134                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 135                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 136                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 137         };
 138
 139         sysclk: sysclk {
 140                 compatible = "fixed-clock";
 141                 #clock-cells = <0>;
 142                 clock-frequency = <100000000>;
 143                 clock-output-names = "sysclk";
 144         };
 145
 146         soc {
 147                 compatible = "simple-bus";
 148                 #address-cells = <2>;
 149                 #size-cells = <2>;
 150                 ranges;
 151
 152                 clockgen: clocking@1300000 {
 153                         compatible = "fsl,ls1088a-clockgen";
 154                         reg = <0 0x1300000 0 0xa0000>;
 155                         #clock-cells = <2>;
 156                         clocks = <&sysclk>;
 157                 };
 158
 159                 tmu: tmu@1f80000 {
 160                         compatible = "fsl,qoriq-tmu";
 161                         reg = <0x0 0x1f80000 0x0 0x10000>;
 162                         interrupts = <0 23 0x4>;
 163                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 164                         fsl,tmu-calibration =
 165                                 /* Calibration data group 1 */
 166                                 <0x00000000 0x00000026
 167                                 0x00000001 0x0000002d
 168                                 0x00000002 0x00000032
 169                                 0x00000003 0x00000039
 170                                 0x00000004 0x0000003f
 171                                 0x00000005 0x00000046
 172                                 0x00000006 0x0000004d
 173                                 0x00000007 0x00000054
 174                                 0x00000008 0x0000005a
 175                                 0x00000009 0x00000061
 176                                 0x0000000a 0x0000006a
 177                                 0x0000000b 0x00000071
 178                                 /* Calibration data group 2 */
 179                                 0x00010000 0x00000025
 180                                 0x00010001 0x0000002c
 181                                 0x00010002 0x00000035
 182                                 0x00010003 0x0000003d
 183                                 0x00010004 0x00000045
 184                                 0x00010005 0x0000004e
 185                                 0x00010006 0x00000057
 186                                 0x00010007 0x00000061
 187                                 0x00010008 0x0000006b
 188                                 0x00010009 0x00000076
 189                                 /* Calibration data group 3 */
 190                                 0x00020000 0x00000029
 191                                 0x00020001 0x00000033
 192                                 0x00020002 0x0000003d
 193                                 0x00020003 0x00000049
 194                                 0x00020004 0x00000056
 195                                 0x00020005 0x00000061
 196                                 0x00020006 0x0000006d
 197                                 /* Calibration data group 4 */
 198                                 0x00030000 0x00000021
 199                                 0x00030001 0x0000002a
 200                                 0x00030002 0x0000003c
 201                                 0x00030003 0x0000004e>;
 202                         little-endian;
 203                         #thermal-sensor-cells = <1>;
 204                 };
 205
 206                 thermal-zones {
 207                         cpu_thermal: cpu-thermal {
 208                                 polling-delay-passive = <1000>;
 209                                 polling-delay = <5000>;
 210                                 thermal-sensors = <&tmu 0>;
 211
 212                                 trips {
 213                                         cpu_alert: cpu-alert {
 214                                                 temperature = <85000>;
 215                                                 hysteresis = <2000>;
 216                                                 type = "passive";
 217                                         };
 218
 219                                         cpu_crit: cpu-crit {
 220                                                 temperature = <95000>;
 221                                                 hysteresis = <2000>;
 222                                                 type = "critical";
 223                                         };
 224                                 };
 225
 226                                 cooling-maps {
 227                                         map0 {
 228                                                 trip = <&cpu_alert>;
 229                                                 cooling-device =
 230                                                         <&cpu0 THERMAL_NO_LIMIT
 231                                                         THERMAL_NO_LIMIT>;
 232                                         };
 233
 234                                         map1 {
 235                                                 trip = <&cpu_alert>;
 236                                                 cooling-device =
 237                                                         <&cpu4 THERMAL_NO_LIMIT
 238                                                         THERMAL_NO_LIMIT>;
 239                                         };
 240                                 };
 241                         };
 242                 };
 243
 244                 duart0: serial@21c0500 {
 245                         compatible = "fsl,ns16550", "ns16550a";
 246                         reg = <0x0 0x21c0500 0x0 0x100>;
 247                         clocks = <&clockgen 4 3>;
 248                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 249                         status = "disabled";
 250                 };
 251
 252                 duart1: serial@21c0600 {
 253                         compatible = "fsl,ns16550", "ns16550a";
 254                         reg = <0x0 0x21c0600 0x0 0x100>;
 255                         clocks = <&clockgen 4 3>;
 256                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 257                         status = "disabled";
 258                 };
 259
 260                 gpio0: gpio@2300000 {
 261                         compatible = "fsl,qoriq-gpio";
 262                         reg = <0x0 0x2300000 0x0 0x10000>;
 263                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 264                         gpio-controller;
 265                         #gpio-cells = <2>;
 266                         interrupt-controller;
 267                         #interrupt-cells = <2>;
 268                 };
 269
 270                 gpio1: gpio@2310000 {
 271                         compatible = "fsl,qoriq-gpio";
 272                         reg = <0x0 0x2310000 0x0 0x10000>;
 273                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 274                         gpio-controller;
 275                         #gpio-cells = <2>;
 276                         interrupt-controller;
 277                         #interrupt-cells = <2>;
 278                 };
 279
 280                 gpio2: gpio@2320000 {
 281                         compatible = "fsl,qoriq-gpio";
 282                         reg = <0x0 0x2320000 0x0 0x10000>;
 283                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                 };
 289
 290                 gpio3: gpio@2330000 {
 291                         compatible = "fsl,qoriq-gpio";
 292                         reg = <0x0 0x2330000 0x0 0x10000>;
 293                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 294                         gpio-controller;
 295                         #gpio-cells = <2>;
 296                         interrupt-controller;
 297                         #interrupt-cells = <2>;
 298                 };
 299
 300                 ifc: ifc@2240000 {
 301                         compatible = "fsl,ifc", "simple-bus";
 302                         reg = <0x0 0x2240000 0x0 0x20000>;
 303                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 304                         little-endian;
 305                         #address-cells = <2>;
 306                         #size-cells = <1>;
 307                         status = "disabled";
 308                 };
 309
 310                 i2c0: i2c@2000000 {
 311                         compatible = "fsl,vf610-i2c";
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                         reg = <0x0 0x2000000 0x0 0x10000>;
 315                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 316                         clocks = <&clockgen 4 3>;
 317                         status = "disabled";
 318                 };
 319
 320                 i2c1: i2c@2010000 {
 321                         compatible = "fsl,vf610-i2c";
 322                         #address-cells = <1>;
 323                         #size-cells = <0>;
 324                         reg = <0x0 0x2010000 0x0 0x10000>;
 325                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 326                         clocks = <&clockgen 4 3>;
 327                         status = "disabled";
 328                 };
 329
 330                 i2c2: i2c@2020000 {
 331                         compatible = "fsl,vf610-i2c";
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                         reg = <0x0 0x2020000 0x0 0x10000>;
 335                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&clockgen 4 3>;
 337                         status = "disabled";
 338                 };
 339
 340                 i2c3: i2c@2030000 {
 341                         compatible = "fsl,vf610-i2c";
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         reg = <0x0 0x2030000 0x0 0x10000>;
 345                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&clockgen 4 3>;
 347                         status = "disabled";
 348                 };
 349
 350                 esdhc: esdhc@2140000 {
 351                         compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
 352                         reg = <0x0 0x2140000 0x0 0x10000>;
 353                         interrupts = <0 28 0x4>; /* Level high type */
 354                         clock-frequency = <0>;
 355                         voltage-ranges = <1800 1800 3300 3300>;
 356                         sdhci,auto-cmd12;
 357                         little-endian;
 358                         bus-width = <4>;
 359                         status = "disabled";
 360                 };
 361
 362                 sata: sata@3200000 {
 363                         compatible = "fsl,ls1088a-ahci";
 364                         reg = <0x0 0x3200000 0x0 0x10000>,
 365                                 <0x7 0x100520 0x0 0x4>;
 366                         reg-names = "ahci", "sata-ecc";
 367                         interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&clockgen 4 3>;
 369                         dma-coherent;
 370                         status = "disabled";
 371                 };
 372         };
 373
 374 };