arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1088A family SoC.
   4  *
   5  * Copyright 2017 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "fsl,ls1088a";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 crypto = &crypto;
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 /* We have 2 clusters having 4 Cortex-A53 cores each */
  28                 cpu0: cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         reg = <0x0>;
  32                         clocks = <&clockgen 1 0>;
  33                         cpu-idle-states = <&CPU_PH20>;
  34                         #cooling-cells = <2>;
  35                 };
  36
  37                 cpu1: cpu@1 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a53";
  40                         reg = <0x1>;
  41                         clocks = <&clockgen 1 0>;
  42                         cpu-idle-states = <&CPU_PH20>;
  43                         #cooling-cells = <2>;
  44                 };
  45
  46                 cpu2: cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a53";
  49                         reg = <0x2>;
  50                         clocks = <&clockgen 1 0>;
  51                         cpu-idle-states = <&CPU_PH20>;
  52                         #cooling-cells = <2>;
  53                 };
  54
  55                 cpu3: cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53";
  58                         reg = <0x3>;
  59                         clocks = <&clockgen 1 0>;
  60                         cpu-idle-states = <&CPU_PH20>;
  61                         #cooling-cells = <2>;
  62                 };
  63
  64                 cpu4: cpu@100 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a53";
  67                         reg = <0x100>;
  68                         clocks = <&clockgen 1 1>;
  69                         cpu-idle-states = <&CPU_PH20>;
  70                         #cooling-cells = <2>;
  71                 };
  72
  73                 cpu5: cpu@101 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53";
  76                         reg = <0x101>;
  77                         clocks = <&clockgen 1 1>;
  78                         cpu-idle-states = <&CPU_PH20>;
  79                         #cooling-cells = <2>;
  80                 };
  81
  82                 cpu6: cpu@102 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53";
  85                         reg = <0x102>;
  86                         clocks = <&clockgen 1 1>;
  87                         cpu-idle-states = <&CPU_PH20>;
  88                         #cooling-cells = <2>;
  89                 };
  90
  91                 cpu7: cpu@103 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53";
  94                         reg = <0x103>;
  95                         clocks = <&clockgen 1 1>;
  96                         cpu-idle-states = <&CPU_PH20>;
  97                         #cooling-cells = <2>;
  98                 };
  99
 100                 CPU_PH20: cpu-ph20 {
 101                         compatible = "arm,idle-state";
 102                         idle-state-name = "PH20";
 103                         arm,psci-suspend-param = <0x0>;
 104                         entry-latency-us = <1000>;
 105                         exit-latency-us = <1000>;
 106                         min-residency-us = <3000>;
 107                 };
 108         };
 109
 110         gic: interrupt-controller@6000000 {
 111                 compatible = "arm,gic-v3";
 112                 #interrupt-cells = <3>;
 113                 interrupt-controller;
 114                 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 115                       <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
 116                       <0x0 0x0c0c0000 0 0x2000>, /* GICC */
 117                       <0x0 0x0c0d0000 0 0x1000>, /* GICH */
 118                       <0x0 0x0c0e0000 0 0x20000>; /* GICV */
 119                 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
 120                 #address-cells = <2>;
 121                 #size-cells = <2>;
 122                 ranges;
 123
 124                 its: gic-its@6020000 {
 125                         compatible = "arm,gic-v3-its";
 126                         msi-controller;
 127                         reg = <0x0 0x6020000 0 0x20000>;
 128                 };
 129         };
 130
 131         thermal-zones {
 132                 cpu_thermal: cpu-thermal {
 133                         polling-delay-passive = <1000>;
 134                         polling-delay = <5000>;
 135                         thermal-sensors = <&tmu 0>;
 136
 137                         trips {
 138                                 cpu_alert: cpu-alert {
 139                                         temperature = <85000>;
 140                                         hysteresis = <2000>;
 141                                         type = "passive";
 142                                 };
 143
 144                                 cpu_crit: cpu-crit {
 145                                         temperature = <95000>;
 146                                         hysteresis = <2000>;
 147                                         type = "critical";
 148                                 };
 149                         };
 150
 151                         cooling-maps {
 152                                 map0 {
 153                                         trip = <&cpu_alert>;
 154                                         cooling-device =
 155                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 156                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 157                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 158                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 159                                                 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 160                                                 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 161                                                 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 162                                                 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 163                                 };
 164                         };
 165                 };
 166         };
 167
 168         timer {
 169                 compatible = "arm,armv8-timer";
 170                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
 171                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
 172                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
 173                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
 174         };
 175
 176         psci {
 177                 compatible = "arm,psci-0.2";
 178                 method = "smc";
 179         };
 180
 181         sysclk: sysclk {
 182                 compatible = "fixed-clock";
 183                 #clock-cells = <0>;
 184                 clock-frequency = <100000000>;
 185                 clock-output-names = "sysclk";
 186         };
 187
 188         soc {
 189                 compatible = "simple-bus";
 190                 #address-cells = <2>;
 191                 #size-cells = <2>;
 192                 ranges;
 193                 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
 194
 195                 clockgen: clocking@1300000 {
 196                         compatible = "fsl,ls1088a-clockgen";
 197                         reg = <0 0x1300000 0 0xa0000>;
 198                         #clock-cells = <2>;
 199                         clocks = <&sysclk>;
 200                 };
 201
 202                 dcfg: dcfg@1e00000 {
 203                         compatible = "fsl,ls1088a-dcfg", "syscon";
 204                         reg = <0x0 0x1e00000 0x0 0x10000>;
 205                         little-endian;
 206                 };
 207
 208                 tmu: tmu@1f80000 {
 209                         compatible = "fsl,qoriq-tmu";
 210                         reg = <0x0 0x1f80000 0x0 0x10000>;
 211                         interrupts = <0 23 0x4>;
 212                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 213                         fsl,tmu-calibration =
 214                                 /* Calibration data group 1 */
 215                                 <0x00000000 0x00000026
 216                                 0x00000001 0x0000002d
 217                                 0x00000002 0x00000032
 218                                 0x00000003 0x00000039
 219                                 0x00000004 0x0000003f
 220                                 0x00000005 0x00000046
 221                                 0x00000006 0x0000004d
 222                                 0x00000007 0x00000054
 223                                 0x00000008 0x0000005a
 224                                 0x00000009 0x00000061
 225                                 0x0000000a 0x0000006a
 226                                 0x0000000b 0x00000071
 227                                 /* Calibration data group 2 */
 228                                 0x00010000 0x00000025
 229                                 0x00010001 0x0000002c
 230                                 0x00010002 0x00000035
 231                                 0x00010003 0x0000003d
 232                                 0x00010004 0x00000045
 233                                 0x00010005 0x0000004e
 234                                 0x00010006 0x00000057
 235                                 0x00010007 0x00000061
 236                                 0x00010008 0x0000006b
 237                                 0x00010009 0x00000076
 238                                 /* Calibration data group 3 */
 239                                 0x00020000 0x00000029
 240                                 0x00020001 0x00000033
 241                                 0x00020002 0x0000003d
 242                                 0x00020003 0x00000049
 243                                 0x00020004 0x00000056
 244                                 0x00020005 0x00000061
 245                                 0x00020006 0x0000006d
 246                                 /* Calibration data group 4 */
 247                                 0x00030000 0x00000021
 248                                 0x00030001 0x0000002a
 249                                 0x00030002 0x0000003c
 250                                 0x00030003 0x0000004e>;
 251                         little-endian;
 252                         #thermal-sensor-cells = <1>;
 253                 };
 254
 255                 duart0: serial@21c0500 {
 256                         compatible = "fsl,ns16550", "ns16550a";
 257                         reg = <0x0 0x21c0500 0x0 0x100>;
 258                         clocks = <&clockgen 4 3>;
 259                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 260                         status = "disabled";
 261                 };
 262
 263                 duart1: serial@21c0600 {
 264                         compatible = "fsl,ns16550", "ns16550a";
 265                         reg = <0x0 0x21c0600 0x0 0x100>;
 266                         clocks = <&clockgen 4 3>;
 267                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 268                         status = "disabled";
 269                 };
 270
 271                 gpio0: gpio@2300000 {
 272                         compatible = "fsl,qoriq-gpio";
 273                         reg = <0x0 0x2300000 0x0 0x10000>;
 274                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 275                         gpio-controller;
 276                         #gpio-cells = <2>;
 277                         interrupt-controller;
 278                         #interrupt-cells = <2>;
 279                 };
 280
 281                 gpio1: gpio@2310000 {
 282                         compatible = "fsl,qoriq-gpio";
 283                         reg = <0x0 0x2310000 0x0 0x10000>;
 284                         interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 285                         gpio-controller;
 286                         #gpio-cells = <2>;
 287                         interrupt-controller;
 288                         #interrupt-cells = <2>;
 289                 };
 290
 291                 gpio2: gpio@2320000 {
 292                         compatible = "fsl,qoriq-gpio";
 293                         reg = <0x0 0x2320000 0x0 0x10000>;
 294                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 gpio3: gpio@2330000 {
 302                         compatible = "fsl,qoriq-gpio";
 303                         reg = <0x0 0x2330000 0x0 0x10000>;
 304                         interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 305                         gpio-controller;
 306                         #gpio-cells = <2>;
 307                         interrupt-controller;
 308                         #interrupt-cells = <2>;
 309                 };
 310
 311                 ifc: ifc@2240000 {
 312                         compatible = "fsl,ifc", "simple-bus";
 313                         reg = <0x0 0x2240000 0x0 0x20000>;
 314                         interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 315                         little-endian;
 316                         #address-cells = <2>;
 317                         #size-cells = <1>;
 318                         status = "disabled";
 319                 };
 320
 321                 i2c0: i2c@2000000 {
 322                         compatible = "fsl,vf610-i2c";
 323                         #address-cells = <1>;
 324                         #size-cells = <0>;
 325                         reg = <0x0 0x2000000 0x0 0x10000>;
 326                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 327                         clocks = <&clockgen 4 3>;
 328                         status = "disabled";
 329                 };
 330
 331                 i2c1: i2c@2010000 {
 332                         compatible = "fsl,vf610-i2c";
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         reg = <0x0 0x2010000 0x0 0x10000>;
 336                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 337                         clocks = <&clockgen 4 3>;
 338                         status = "disabled";
 339                 };
 340
 341                 i2c2: i2c@2020000 {
 342                         compatible = "fsl,vf610-i2c";
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         reg = <0x0 0x2020000 0x0 0x10000>;
 346                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 347                         clocks = <&clockgen 4 3>;
 348                         status = "disabled";
 349                 };
 350
 351                 i2c3: i2c@2030000 {
 352                         compatible = "fsl,vf610-i2c";
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         reg = <0x0 0x2030000 0x0 0x10000>;
 356                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 357                         clocks = <&clockgen 4 3>;
 358                         status = "disabled";
 359                 };
 360
 361                 esdhc: esdhc@2140000 {
 362                         compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
 363                         reg = <0x0 0x2140000 0x0 0x10000>;
 364                         interrupts = <0 28 0x4>; /* Level high type */
 365                         clock-frequency = <0>;
 366                         voltage-ranges = <1800 1800 3300 3300>;
 367                         sdhci,auto-cmd12;
 368                         little-endian;
 369                         bus-width = <4>;
 370                         status = "disabled";
 371                 };
 372
 373                 usb0: usb3@3100000 {
 374                         compatible = "snps,dwc3";
 375                         reg = <0x0 0x3100000 0x0 0x10000>;
 376                         interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 377                         dr_mode = "host";
 378                         snps,quirk-frame-length-adjustment = <0x20>;
 379                         snps,dis_rxdet_inp3_quirk;
 380                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 381                         status = "disabled";
 382                 };
 383
 384                 usb1: usb3@3110000 {
 385                         compatible = "snps,dwc3";
 386                         reg = <0x0 0x3110000 0x0 0x10000>;
 387                         interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 388                         dr_mode = "host";
 389                         snps,quirk-frame-length-adjustment = <0x20>;
 390                         snps,dis_rxdet_inp3_quirk;
 391                         status = "disabled";
 392                 };
 393
 394                 sata: sata@3200000 {
 395                         compatible = "fsl,ls1088a-ahci";
 396                         reg = <0x0 0x3200000 0x0 0x10000>,
 397                                 <0x7 0x100520 0x0 0x4>;
 398                         reg-names = "ahci", "sata-ecc";
 399                         interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
 400                         clocks = <&clockgen 4 3>;
 401                         dma-coherent;
 402                         status = "disabled";
 403                 };
 404
 405                 crypto: crypto@8000000 {
 406                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 407                         fsl,sec-era = <8>;
 408                         #address-cells = <1>;
 409                         #size-cells = <1>;
 410                         ranges = <0x0 0x00 0x8000000 0x100000>;
 411                         reg = <0x00 0x8000000 0x0 0x100000>;
 412                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 413                         dma-coherent;
 414
 415                         sec_jr0: jr@10000 {
 416                                 compatible = "fsl,sec-v5.0-job-ring",
 417                                              "fsl,sec-v4.0-job-ring";
 418                                 reg        = <0x10000 0x10000>;
 419                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 420                         };
 421
 422                         sec_jr1: jr@20000 {
 423                                 compatible = "fsl,sec-v5.0-job-ring",
 424                                              "fsl,sec-v4.0-job-ring";
 425                                 reg        = <0x20000 0x10000>;
 426                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 427                         };
 428
 429                         sec_jr2: jr@30000 {
 430                                 compatible = "fsl,sec-v5.0-job-ring",
 431                                              "fsl,sec-v4.0-job-ring";
 432                                 reg        = <0x30000 0x10000>;
 433                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 434                         };
 435
 436                         sec_jr3: jr@40000 {
 437                                 compatible = "fsl,sec-v5.0-job-ring",
 438                                              "fsl,sec-v4.0-job-ring";
 439                                 reg        = <0x40000 0x10000>;
 440                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 441                         };
 442                 };
 443
 444                 pcie@3400000 {
 445                         compatible = "fsl,ls1088a-pcie";
 446                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 447                                0x20 0x00000000 0x0 0x00002000>; /* configuration space */
 448                         reg-names = "regs", "config";
 449                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 450                         interrupt-names = "aer";
 451                         #address-cells = <3>;
 452                         #size-cells = <2>;
 453                         device_type = "pci";
 454                         dma-coherent;
 455                         num-lanes = <4>;
 456                         num-viewport = <256>;
 457                         bus-range = <0x0 0xff>;
 458                         ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000   /* downstream I/O */
 459                                   0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 460                         msi-parent = <&its>;
 461                         #interrupt-cells = <1>;
 462                         interrupt-map-mask = <0 0 0 7>;
 463                         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
 464                                         <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
 465                                         <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
 466                                         <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
 467                         status = "disabled";
 468                 };
 469
 470                 pcie@3500000 {
 471                         compatible = "fsl,ls1088a-pcie";
 472                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 473                                0x28 0x00000000 0x0 0x00002000>; /* configuration space */
 474                         reg-names = "regs", "config";
 475                         interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 476                         interrupt-names = "aer";
 477                         #address-cells = <3>;
 478                         #size-cells = <2>;
 479                         device_type = "pci";
 480                         dma-coherent;
 481                         num-lanes = <4>;
 482                         num-viewport = <6>;
 483                         bus-range = <0x0 0xff>;
 484                         ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000   /* downstream I/O */
 485                                   0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 486                         msi-parent = <&its>;
 487                         #interrupt-cells = <1>;
 488                         interrupt-map-mask = <0 0 0 7>;
 489                         interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
 490                                         <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
 491                                         <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
 492                                         <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
 493                         status = "disabled";
 494                 };
 495
 496                 pcie@3600000 {
 497                         compatible = "fsl,ls1088a-pcie";
 498                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 499                                0x30 0x00000000 0x0 0x00002000>; /* configuration space */
 500                         reg-names = "regs", "config";
 501                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 502                         interrupt-names = "aer";
 503                         #address-cells = <3>;
 504                         #size-cells = <2>;
 505                         device_type = "pci";
 506                         dma-coherent;
 507                         num-lanes = <8>;
 508                         num-viewport = <6>;
 509                         bus-range = <0x0 0xff>;
 510                         ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000   /* downstream I/O */
 511                                   0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 512                         msi-parent = <&its>;
 513                         #interrupt-cells = <1>;
 514                         interrupt-map-mask = <0 0 0 7>;
 515                         interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
 516                                         <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
 517                                         <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
 518                                         <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
 519                         status = "disabled";
 520                 };
 521
 522                 smmu: iommu@5000000 {
 523                         compatible = "arm,mmu-500";
 524                         reg = <0 0x5000000 0 0x800000>;
 525                         #iommu-cells = <1>;
 526                         stream-match-mask = <0x7C00>;
 527                         #global-interrupts = <12>;
 528                                      // global secure fault
 529                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 530                                      // combined secure
 531                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 532                                      // global non-secure fault
 533                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 534                                      // combined non-secure
 535                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 536                                      // performance counter interrupts 0-7
 537                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 538                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 539                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 540                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 542                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 543                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 544                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 545                                      // per context interrupt, 64 interrupts
 546                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 548                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 549                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 550                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 551                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 553                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 554                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 556                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 557                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 558                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 560                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 562                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 563                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 564                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 566                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 567                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 568                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 569                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 570                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 571                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 572                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 575                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 576                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 577                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 578                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 579                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 581                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 595                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 600                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 602                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 604                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 605                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 606                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 607                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 608                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 610                 };
 611
 612                 cluster1_core0_watchdog: wdt@c000000 {
 613                         compatible = "arm,sp805-wdt", "arm,primecell";
 614                         reg = <0x0 0xc000000 0x0 0x1000>;
 615                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 616                         clock-names = "apb_pclk", "wdog_clk";
 617                 };
 618
 619                 cluster1_core1_watchdog: wdt@c010000 {
 620                         compatible = "arm,sp805-wdt", "arm,primecell";
 621                         reg = <0x0 0xc010000 0x0 0x1000>;
 622                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 623                         clock-names = "apb_pclk", "wdog_clk";
 624                 };
 625
 626                 cluster1_core2_watchdog: wdt@c020000 {
 627                         compatible = "arm,sp805-wdt", "arm,primecell";
 628                         reg = <0x0 0xc020000 0x0 0x1000>;
 629                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 630                         clock-names = "apb_pclk", "wdog_clk";
 631                 };
 632
 633                 cluster1_core3_watchdog: wdt@c030000 {
 634                         compatible = "arm,sp805-wdt", "arm,primecell";
 635                         reg = <0x0 0xc030000 0x0 0x1000>;
 636                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 637                         clock-names = "apb_pclk", "wdog_clk";
 638                 };
 639
 640                 cluster2_core0_watchdog: wdt@c100000 {
 641                         compatible = "arm,sp805-wdt", "arm,primecell";
 642                         reg = <0x0 0xc100000 0x0 0x1000>;
 643                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 644                         clock-names = "apb_pclk", "wdog_clk";
 645                 };
 646
 647                 cluster2_core1_watchdog: wdt@c110000 {
 648                         compatible = "arm,sp805-wdt", "arm,primecell";
 649                         reg = <0x0 0xc110000 0x0 0x1000>;
 650                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 651                         clock-names = "apb_pclk", "wdog_clk";
 652                 };
 653
 654                 cluster2_core2_watchdog: wdt@c120000 {
 655                         compatible = "arm,sp805-wdt", "arm,primecell";
 656                         reg = <0x0 0xc120000 0x0 0x1000>;
 657                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 658                         clock-names = "apb_pclk", "wdog_clk";
 659                 };
 660
 661                 cluster2_core3_watchdog: wdt@c130000 {
 662                         compatible = "arm,sp805-wdt", "arm,primecell";
 663                         reg = <0x0 0xc130000 0x0 0x1000>;
 664                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 665                         clock-names = "apb_pclk", "wdog_clk";
 666                 };
 667
 668                 fsl_mc: fsl-mc@80c000000 {
 669                         compatible = "fsl,qoriq-mc";
 670                         reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
 671                               <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
 672                         msi-parent = <&its>;
 673                         iommu-map = <0 &smmu 0 0>;      /* This is fixed-up by u-boot */
 674                         dma-coherent;
 675                         #address-cells = <3>;
 676                         #size-cells = <1>;
 677
 678                         /*
 679                          * Region type 0x0 - MC portals
 680                          * Region type 0x1 - QBMAN portals
 681                          */
 682                         ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
 683                                   0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
 684
 685                         dpmacs {
 686                                 #address-cells = <1>;
 687                                 #size-cells = <0>;
 688
 689                                 dpmac1: dpmac@1 {
 690                                         compatible = "fsl,qoriq-mc-dpmac";
 691                                         reg = <1>;
 692                                 };
 693
 694                                 dpmac2: dpmac@2 {
 695                                         compatible = "fsl,qoriq-mc-dpmac";
 696                                         reg = <2>;
 697                                 };
 698
 699                                 dpmac3: dpmac@3 {
 700                                         compatible = "fsl,qoriq-mc-dpmac";
 701                                         reg = <3>;
 702                                 };
 703
 704                                 dpmac4: dpmac@4 {
 705                                         compatible = "fsl,qoriq-mc-dpmac";
 706                                         reg = <4>;
 707                                 };
 708
 709                                 dpmac5: dpmac@5 {
 710                                         compatible = "fsl,qoriq-mc-dpmac";
 711                                         reg = <5>;
 712                                 };
 713
 714                                 dpmac6: dpmac@6 {
 715                                         compatible = "fsl,qoriq-mc-dpmac";
 716                                         reg = <6>;
 717                                 };
 718
 719                                 dpmac7: dpmac@7 {
 720                                         compatible = "fsl,qoriq-mc-dpmac";
 721                                         reg = <7>;
 722                                 };
 723
 724                                 dpmac8: dpmac@8 {
 725                                         compatible = "fsl,qoriq-mc-dpmac";
 726                                         reg = <8>;
 727                                 };
 728
 729                                 dpmac9: dpmac@9 {
 730                                         compatible = "fsl,qoriq-mc-dpmac";
 731                                         reg = <9>;
 732                                 };
 733
 734                                 dpmac10: dpmac@a {
 735                                         compatible = "fsl,qoriq-mc-dpmac";
 736                                         reg = <0xa>;
 737                                 };
 738                         };
 739                 };
 740         };
 741
 742         firmware {
 743                 optee {
 744                         compatible = "linaro,optee-tz";
 745                         method = "smc";
 746                 };
 747         };
 748 };