arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
   3  *
   4  * Copyright 2016, Freescale Semiconductor, Inc.
   5  *
   6  * Mingkai Hu <mingkai.hu@nxp.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPLv2 or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This library is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This library is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 / {
  51         compatible = "fsl,ls1046a";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 crypto = &crypto;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a72";
  67                         reg = <0x0>;
  68                         clocks = <&clockgen 1 0>;
  69                         next-level-cache = <&l2>;
  70                         cpu-idle-states = <&CPU_PH20>;
  71                         #cooling-cells = <2>;
  72                 };
  73
  74                 cpu1: cpu@1 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a72";
  77                         reg = <0x1>;
  78                         clocks = <&clockgen 1 0>;
  79                         next-level-cache = <&l2>;
  80                         cpu-idle-states = <&CPU_PH20>;
  81                 };
  82
  83                 cpu2: cpu@2 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a72";
  86                         reg = <0x2>;
  87                         clocks = <&clockgen 1 0>;
  88                         next-level-cache = <&l2>;
  89                         cpu-idle-states = <&CPU_PH20>;
  90                 };
  91
  92                 cpu3: cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a72";
  95                         reg = <0x3>;
  96                         clocks = <&clockgen 1 0>;
  97                         next-level-cache = <&l2>;
  98                         cpu-idle-states = <&CPU_PH20>;
  99                 };
 100
 101                 l2: l2-cache {
 102                         compatible = "cache";
 103                 };
 104         };
 105
 106         idle-states {
 107                 /*
 108                  * PSCI node is not added default, U-boot will add missing
 109                  * parts if it determines to use PSCI.
 110                  */
 111                 entry-method = "arm,psci";
 112
 113                 CPU_PH20: cpu-ph20 {
 114                         compatible = "arm,idle-state";
 115                         idle-state-name = "PH20";
 116                         arm,psci-suspend-param = <0x00010000>;
 117                         entry-latency-us = <1000>;
 118                         exit-latency-us = <1000>;
 119                         min-residency-us = <3000>;
 120                 };
 121         };
 122
 123         memory@80000000 {
 124                 device_type = "memory";
 125         };
 126
 127         sysclk: sysclk {
 128                 compatible = "fixed-clock";
 129                 #clock-cells = <0>;
 130                 clock-frequency = <100000000>;
 131                 clock-output-names = "sysclk";
 132         };
 133
 134         reboot {
 135                 compatible ="syscon-reboot";
 136                 regmap = <&dcfg>;
 137                 offset = <0xb0>;
 138                 mask = <0x02>;
 139         };
 140
 141         timer {
 142                 compatible = "arm,armv8-timer";
 143                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
 144                                           IRQ_TYPE_LEVEL_LOW)>,
 145                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
 146                                           IRQ_TYPE_LEVEL_LOW)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
 148                                           IRQ_TYPE_LEVEL_LOW)>,
 149                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
 150                                           IRQ_TYPE_LEVEL_LOW)>;
 151         };
 152
 153         pmu {
 154                 compatible = "arm,cortex-a72-pmu";
 155                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 157                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 159                 interrupt-affinity = <&cpu0>,
 160                                      <&cpu1>,
 161                                      <&cpu2>,
 162                                      <&cpu3>;
 163         };
 164
 165         gic: interrupt-controller@1400000 {
 166                 compatible = "arm,gic-400";
 167                 #interrupt-cells = <3>;
 168                 interrupt-controller;
 169                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
 170                       <0x0 0x1420000 0 0x20000>, /* GICC */
 171                       <0x0 0x1440000 0 0x20000>, /* GICH */
 172                       <0x0 0x1460000 0 0x20000>; /* GICV */
 173                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 174                                          IRQ_TYPE_LEVEL_LOW)>;
 175         };
 176
 177         soc {
 178                 compatible = "simple-bus";
 179                 #address-cells = <2>;
 180                 #size-cells = <2>;
 181                 ranges;
 182
 183                 ddr: memory-controller@1080000 {
 184                         compatible = "fsl,qoriq-memory-controller";
 185                         reg = <0x0 0x1080000 0x0 0x1000>;
 186                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 187                         big-endian;
 188                 };
 189
 190                 ifc: ifc@1530000 {
 191                         compatible = "fsl,ifc", "simple-bus";
 192                         reg = <0x0 0x1530000 0x0 0x10000>;
 193                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 194                 };
 195
 196                 qspi: quadspi@1550000 {
 197                         compatible = "fsl,ls1021a-qspi";
 198                         #address-cells = <1>;
 199                         #size-cells = <0>;
 200                         reg = <0x0 0x1550000 0x0 0x10000>,
 201                                 <0x0 0x40000000 0x0 0x10000000>;
 202                         reg-names = "QuadSPI", "QuadSPI-memory";
 203                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 204                         clock-names = "qspi_en", "qspi";
 205                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 206                         big-endian;
 207                         fsl,qspi-has-second-chip;
 208                         status = "disabled";
 209                 };
 210
 211                 esdhc: esdhc@1560000 {
 212                         compatible = "fsl,esdhc";
 213                         reg = <0x0 0x1560000 0x0 0x10000>;
 214                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 215                         clock-frequency = <0>;
 216                         voltage-ranges = <1800 1800 3300 3300>;
 217                         sdhci,auto-cmd12;
 218                         big-endian;
 219                         bus-width = <4>;
 220                 };
 221
 222                 scfg: scfg@1570000 {
 223                         compatible = "fsl,ls1046a-scfg", "syscon";
 224                         reg = <0x0 0x1570000 0x0 0x10000>;
 225                         big-endian;
 226                 };
 227
 228                 crypto: crypto@1700000 {
 229                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 230                                      "fsl,sec-v4.0";
 231                         fsl,sec-era = <8>;
 232                         #address-cells = <1>;
 233                         #size-cells = <1>;
 234                         ranges = <0x0 0x00 0x1700000 0x100000>;
 235                         reg = <0x00 0x1700000 0x0 0x100000>;
 236                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 237
 238                         sec_jr0: jr@10000 {
 239                                 compatible = "fsl,sec-v5.4-job-ring",
 240                                              "fsl,sec-v5.0-job-ring",
 241                                              "fsl,sec-v4.0-job-ring";
 242                                 reg        = <0x10000 0x10000>;
 243                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 244                         };
 245
 246                         sec_jr1: jr@20000 {
 247                                 compatible = "fsl,sec-v5.4-job-ring",
 248                                              "fsl,sec-v5.0-job-ring",
 249                                              "fsl,sec-v4.0-job-ring";
 250                                 reg        = <0x20000 0x10000>;
 251                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 252                         };
 253
 254                         sec_jr2: jr@30000 {
 255                                 compatible = "fsl,sec-v5.4-job-ring",
 256                                              "fsl,sec-v5.0-job-ring",
 257                                              "fsl,sec-v4.0-job-ring";
 258                                 reg        = <0x30000 0x10000>;
 259                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 260                         };
 261
 262                         sec_jr3: jr@40000 {
 263                                 compatible = "fsl,sec-v5.4-job-ring",
 264                                              "fsl,sec-v5.0-job-ring",
 265                                              "fsl,sec-v4.0-job-ring";
 266                                 reg        = <0x40000 0x10000>;
 267                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 268                         };
 269                 };
 270
 271                 dcfg: dcfg@1ee0000 {
 272                         compatible = "fsl,ls1046a-dcfg", "syscon";
 273                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 274                         big-endian;
 275                 };
 276
 277                 clockgen: clocking@1ee1000 {
 278                         compatible = "fsl,ls1046a-clockgen";
 279                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 280                         #clock-cells = <2>;
 281                         clocks = <&sysclk>;
 282                 };
 283
 284                 tmu: tmu@1f00000 {
 285                         compatible = "fsl,qoriq-tmu";
 286                         reg = <0x0 0x1f00000 0x0 0x10000>;
 287                         interrupts = <0 33 0x4>;
 288                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 289                         fsl,tmu-calibration =
 290                                 /* Calibration data group 1 */
 291                                 <0x00000000 0x00000026
 292                                 0x00000001 0x0000002d
 293                                 0x00000002 0x00000032
 294                                 0x00000003 0x00000039
 295                                 0x00000004 0x0000003f
 296                                 0x00000005 0x00000046
 297                                 0x00000006 0x0000004d
 298                                 0x00000007 0x00000054
 299                                 0x00000008 0x0000005a
 300                                 0x00000009 0x00000061
 301                                 0x0000000a 0x0000006a
 302                                 0x0000000b 0x00000071
 303                                 /* Calibration data group 2 */
 304                                 0x00010000 0x00000025
 305                                 0x00010001 0x0000002c
 306                                 0x00010002 0x00000035
 307                                 0x00010003 0x0000003d
 308                                 0x00010004 0x00000045
 309                                 0x00010005 0x0000004e
 310                                 0x00010006 0x00000057
 311                                 0x00010007 0x00000061
 312                                 0x00010008 0x0000006b
 313                                 0x00010009 0x00000076
 314                                 /* Calibration data group 3 */
 315                                 0x00020000 0x00000029
 316                                 0x00020001 0x00000033
 317                                 0x00020002 0x0000003d
 318                                 0x00020003 0x00000049
 319                                 0x00020004 0x00000056
 320                                 0x00020005 0x00000061
 321                                 0x00020006 0x0000006d
 322                                 /* Calibration data group 4 */
 323                                 0x00030000 0x00000021
 324                                 0x00030001 0x0000002a
 325                                 0x00030002 0x0000003c
 326                                 0x00030003 0x0000004e>;
 327                         big-endian;
 328                         #thermal-sensor-cells = <1>;
 329                 };
 330
 331                 thermal-zones {
 332                         cpu_thermal: cpu-thermal {
 333                                 polling-delay-passive = <1000>;
 334                                 polling-delay = <5000>;
 335                                 thermal-sensors = <&tmu 3>;
 336
 337                                 trips {
 338                                         cpu_alert: cpu-alert {
 339                                                 temperature = <85000>;
 340                                                 hysteresis = <2000>;
 341                                                 type = "passive";
 342                                         };
 343
 344                                         cpu_crit: cpu-crit {
 345                                                 temperature = <95000>;
 346                                                 hysteresis = <2000>;
 347                                                 type = "critical";
 348                                         };
 349                                 };
 350
 351                                 cooling-maps {
 352                                         map0 {
 353                                                 trip = <&cpu_alert>;
 354                                                 cooling-device =
 355                                                         <&cpu0 THERMAL_NO_LIMIT
 356                                                         THERMAL_NO_LIMIT>;
 357                                         };
 358                                 };
 359                         };
 360                 };
 361
 362                 dspi: dspi@2100000 {
 363                         compatible = "fsl,ls1021a-v1.0-dspi";
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         reg = <0x0 0x2100000 0x0 0x10000>;
 367                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 368                         clock-names = "dspi";
 369                         clocks = <&clockgen 4 1>;
 370                         spi-num-chipselects = <5>;
 371                         big-endian;
 372                         status = "disabled";
 373                 };
 374
 375                 i2c0: i2c@2180000 {
 376                         compatible = "fsl,vf610-i2c";
 377                         #address-cells = <1>;
 378                         #size-cells = <0>;
 379                         reg = <0x0 0x2180000 0x0 0x10000>;
 380                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 381                         clocks = <&clockgen 4 1>;
 382                         dmas = <&edma0 1 39>,
 383                                <&edma0 1 38>;
 384                         dma-names = "tx", "rx";
 385                         status = "disabled";
 386                 };
 387
 388                 i2c1: i2c@2190000 {
 389                         compatible = "fsl,vf610-i2c";
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         reg = <0x0 0x2190000 0x0 0x10000>;
 393                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&clockgen 4 1>;
 395                         status = "disabled";
 396                 };
 397
 398                 i2c2: i2c@21a0000 {
 399                         compatible = "fsl,vf610-i2c";
 400                         #address-cells = <1>;
 401                         #size-cells = <0>;
 402                         reg = <0x0 0x21a0000 0x0 0x10000>;
 403                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 404                         clocks = <&clockgen 4 1>;
 405                         status = "disabled";
 406                 };
 407
 408                 i2c3: i2c@21b0000 {
 409                         compatible = "fsl,vf610-i2c";
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412                         reg = <0x0 0x21b0000 0x0 0x10000>;
 413                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 414                         clocks = <&clockgen 4 1>;
 415                         status = "disabled";
 416                 };
 417
 418                 duart0: serial@21c0500 {
 419                         compatible = "fsl,ns16550", "ns16550a";
 420                         reg = <0x00 0x21c0500 0x0 0x100>;
 421                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 422                         clocks = <&clockgen 4 1>;
 423                 };
 424
 425                 duart1: serial@21c0600 {
 426                         compatible = "fsl,ns16550", "ns16550a";
 427                         reg = <0x00 0x21c0600 0x0 0x100>;
 428                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 429                         clocks = <&clockgen 4 1>;
 430                 };
 431
 432                 duart2: serial@21d0500 {
 433                         compatible = "fsl,ns16550", "ns16550a";
 434                         reg = <0x0 0x21d0500 0x0 0x100>;
 435                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&clockgen 4 1>;
 437                 };
 438
 439                 duart3: serial@21d0600 {
 440                         compatible = "fsl,ns16550", "ns16550a";
 441                         reg = <0x0 0x21d0600 0x0 0x100>;
 442                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 443                         clocks = <&clockgen 4 1>;
 444                 };
 445
 446                 gpio0: gpio@2300000 {
 447                         compatible = "fsl,qoriq-gpio";
 448                         reg = <0x0 0x2300000 0x0 0x10000>;
 449                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 450                         gpio-controller;
 451                         #gpio-cells = <2>;
 452                         interrupt-controller;
 453                         #interrupt-cells = <2>;
 454                 };
 455
 456                 gpio1: gpio@2310000 {
 457                         compatible = "fsl,qoriq-gpio";
 458                         reg = <0x0 0x2310000 0x0 0x10000>;
 459                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 460                         gpio-controller;
 461                         #gpio-cells = <2>;
 462                         interrupt-controller;
 463                         #interrupt-cells = <2>;
 464                 };
 465
 466                 gpio2: gpio@2320000 {
 467                         compatible = "fsl,qoriq-gpio";
 468                         reg = <0x0 0x2320000 0x0 0x10000>;
 469                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 470                         gpio-controller;
 471                         #gpio-cells = <2>;
 472                         interrupt-controller;
 473                         #interrupt-cells = <2>;
 474                 };
 475
 476                 gpio3: gpio@2330000 {
 477                         compatible = "fsl,qoriq-gpio";
 478                         reg = <0x0 0x2330000 0x0 0x10000>;
 479                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 480                         gpio-controller;
 481                         #gpio-cells = <2>;
 482                         interrupt-controller;
 483                         #interrupt-cells = <2>;
 484                 };
 485
 486                 lpuart0: serial@2950000 {
 487                         compatible = "fsl,ls1021a-lpuart";
 488                         reg = <0x0 0x2950000 0x0 0x1000>;
 489                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&clockgen 4 0>;
 491                         clock-names = "ipg";
 492                         status = "disabled";
 493                 };
 494
 495                 lpuart1: serial@2960000 {
 496                         compatible = "fsl,ls1021a-lpuart";
 497                         reg = <0x0 0x2960000 0x0 0x1000>;
 498                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 499                         clocks = <&clockgen 4 1>;
 500                         clock-names = "ipg";
 501                         status = "disabled";
 502                 };
 503
 504                 lpuart2: serial@2970000 {
 505                         compatible = "fsl,ls1021a-lpuart";
 506                         reg = <0x0 0x2970000 0x0 0x1000>;
 507                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&clockgen 4 1>;
 509                         clock-names = "ipg";
 510                         status = "disabled";
 511                 };
 512
 513                 lpuart3: serial@2980000 {
 514                         compatible = "fsl,ls1021a-lpuart";
 515                         reg = <0x0 0x2980000 0x0 0x1000>;
 516                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 517                         clocks = <&clockgen 4 1>;
 518                         clock-names = "ipg";
 519                         status = "disabled";
 520                 };
 521
 522                 lpuart4: serial@2990000 {
 523                         compatible = "fsl,ls1021a-lpuart";
 524                         reg = <0x0 0x2990000 0x0 0x1000>;
 525                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&clockgen 4 1>;
 527                         clock-names = "ipg";
 528                         status = "disabled";
 529                 };
 530
 531                 lpuart5: serial@29a0000 {
 532                         compatible = "fsl,ls1021a-lpuart";
 533                         reg = <0x0 0x29a0000 0x0 0x1000>;
 534                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 535                         clocks = <&clockgen 4 1>;
 536                         clock-names = "ipg";
 537                         status = "disabled";
 538                 };
 539
 540                 wdog0: watchdog@2ad0000 {
 541                         compatible = "fsl,imx21-wdt";
 542                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 543                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&clockgen 4 1>;
 545                         big-endian;
 546                 };
 547
 548                 edma0: edma@2c00000 {
 549                         #dma-cells = <2>;
 550                         compatible = "fsl,vf610-edma";
 551                         reg = <0x0 0x2c00000 0x0 0x10000>,
 552                               <0x0 0x2c10000 0x0 0x10000>,
 553                               <0x0 0x2c20000 0x0 0x10000>;
 554                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 555                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 556                         interrupt-names = "edma-tx", "edma-err";
 557                         dma-channels = <32>;
 558                         big-endian;
 559                         clock-names = "dmamux0", "dmamux1";
 560                         clocks = <&clockgen 4 1>,
 561                                  <&clockgen 4 1>;
 562                 };
 563
 564                 usb0: usb@2f00000 {
 565                         compatible = "snps,dwc3";
 566                         reg = <0x0 0x2f00000 0x0 0x10000>;
 567                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 568                         dr_mode = "host";
 569                         snps,quirk-frame-length-adjustment = <0x20>;
 570                 };
 571
 572                 usb1: usb@3000000 {
 573                         compatible = "snps,dwc3";
 574                         reg = <0x0 0x3000000 0x0 0x10000>;
 575                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 576                         dr_mode = "host";
 577                         snps,quirk-frame-length-adjustment = <0x20>;
 578                 };
 579
 580                 usb2: usb@3100000 {
 581                         compatible = "snps,dwc3";
 582                         reg = <0x0 0x3100000 0x0 0x10000>;
 583                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 584                         dr_mode = "host";
 585                         snps,quirk-frame-length-adjustment = <0x20>;
 586                 };
 587
 588                 sata: sata@3200000 {
 589                         compatible = "fsl,ls1046a-ahci";
 590                         reg = <0x0 0x3200000 0x0 0x10000>,
 591                                 <0x0 0x20140520 0x0 0x4>;
 592                         reg-names = "ahci", "sata-ecc";
 593                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 594                         clocks = <&clockgen 4 1>;
 595                 };
 596         };
 597 };