arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

   1 /*
   2  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
   3  *
   4  * Copyright 2016 Freescale Semiconductor, Inc.
   5  *
   6  * Mingkai Hu <mingkai.hu@nxp.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPLv2 or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This library is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This library is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 / {
  51         compatible = "fsl,ls1046a";
  52         interrupt-parent = <&gic>;
  53         #address-cells = <2>;
  54         #size-cells = <2>;
  55
  56         aliases {
  57                 crypto = &crypto;
  58                 fman0 = &fman0;
  59                 ethernet0 = &enet0;
  60                 ethernet1 = &enet1;
  61                 ethernet2 = &enet2;
  62                 ethernet3 = &enet3;
  63                 ethernet4 = &enet4;
  64                 ethernet5 = &enet5;
  65                 ethernet6 = &enet6;
  66                 ethernet7 = &enet7;
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a72";
  76                         reg = <0x0>;
  77                         clocks = <&clockgen 1 0>;
  78                         next-level-cache = <&l2>;
  79                         cpu-idle-states = <&CPU_PH20>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a72";
  86                         reg = <0x1>;
  87                         clocks = <&clockgen 1 0>;
  88                         next-level-cache = <&l2>;
  89                         cpu-idle-states = <&CPU_PH20>;
  90                 };
  91
  92                 cpu2: cpu@2 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a72";
  95                         reg = <0x2>;
  96                         clocks = <&clockgen 1 0>;
  97                         next-level-cache = <&l2>;
  98                         cpu-idle-states = <&CPU_PH20>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a72";
 104                         reg = <0x3>;
 105                         clocks = <&clockgen 1 0>;
 106                         next-level-cache = <&l2>;
 107                         cpu-idle-states = <&CPU_PH20>;
 108                 };
 109
 110                 l2: l2-cache {
 111                         compatible = "cache";
 112                 };
 113         };
 114
 115         idle-states {
 116                 /*
 117                  * PSCI node is not added default, U-boot will add missing
 118                  * parts if it determines to use PSCI.
 119                  */
 120                 entry-method = "arm,psci";
 121
 122                 CPU_PH20: cpu-ph20 {
 123                         compatible = "arm,idle-state";
 124                         idle-state-name = "PH20";
 125                         arm,psci-suspend-param = <0x00010000>;
 126                         entry-latency-us = <1000>;
 127                         exit-latency-us = <1000>;
 128                         min-residency-us = <3000>;
 129                 };
 130         };
 131
 132         memory@80000000 {
 133                 device_type = "memory";
 134         };
 135
 136         sysclk: sysclk {
 137                 compatible = "fixed-clock";
 138                 #clock-cells = <0>;
 139                 clock-frequency = <100000000>;
 140                 clock-output-names = "sysclk";
 141         };
 142
 143         reboot {
 144                 compatible ="syscon-reboot";
 145                 regmap = <&dcfg>;
 146                 offset = <0xb0>;
 147                 mask = <0x02>;
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
 153                                           IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
 155                                           IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
 157                                           IRQ_TYPE_LEVEL_LOW)>,
 158                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
 159                                           IRQ_TYPE_LEVEL_LOW)>;
 160         };
 161
 162         pmu {
 163                 compatible = "arm,cortex-a72-pmu";
 164                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 168                 interrupt-affinity = <&cpu0>,
 169                                      <&cpu1>,
 170                                      <&cpu2>,
 171                                      <&cpu3>;
 172         };
 173
 174         gic: interrupt-controller@1400000 {
 175                 compatible = "arm,gic-400";
 176                 #interrupt-cells = <3>;
 177                 interrupt-controller;
 178                 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
 179                       <0x0 0x1420000 0 0x20000>, /* GICC */
 180                       <0x0 0x1440000 0 0x20000>, /* GICH */
 181                       <0x0 0x1460000 0 0x20000>; /* GICV */
 182                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 183                                          IRQ_TYPE_LEVEL_LOW)>;
 184         };
 185
 186         soc: soc {
 187                 compatible = "simple-bus";
 188                 #address-cells = <2>;
 189                 #size-cells = <2>;
 190                 ranges;
 191
 192                 ddr: memory-controller@1080000 {
 193                         compatible = "fsl,qoriq-memory-controller";
 194                         reg = <0x0 0x1080000 0x0 0x1000>;
 195                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 196                         big-endian;
 197                 };
 198
 199                 ifc: ifc@1530000 {
 200                         compatible = "fsl,ifc", "simple-bus";
 201                         reg = <0x0 0x1530000 0x0 0x10000>;
 202                         big-endian;
 203                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 204                 };
 205
 206                 qspi: quadspi@1550000 {
 207                         compatible = "fsl,ls1021a-qspi";
 208                         #address-cells = <1>;
 209                         #size-cells = <0>;
 210                         reg = <0x0 0x1550000 0x0 0x10000>,
 211                                 <0x0 0x40000000 0x0 0x10000000>;
 212                         reg-names = "QuadSPI", "QuadSPI-memory";
 213                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 214                         clock-names = "qspi_en", "qspi";
 215                         clocks = <&clockgen 4 1>, <&clockgen 4 1>;
 216                         big-endian;
 217                         fsl,qspi-has-second-chip;
 218                         status = "disabled";
 219                 };
 220
 221                 esdhc: esdhc@1560000 {
 222                         compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
 223                         reg = <0x0 0x1560000 0x0 0x10000>;
 224                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&clockgen 2 1>;
 226                         voltage-ranges = <1800 1800 3300 3300>;
 227                         sdhci,auto-cmd12;
 228                         big-endian;
 229                         bus-width = <4>;
 230                 };
 231
 232                 scfg: scfg@1570000 {
 233                         compatible = "fsl,ls1046a-scfg", "syscon";
 234                         reg = <0x0 0x1570000 0x0 0x10000>;
 235                         big-endian;
 236                 };
 237
 238                 crypto: crypto@1700000 {
 239                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 240                                      "fsl,sec-v4.0";
 241                         fsl,sec-era = <8>;
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244                         ranges = <0x0 0x00 0x1700000 0x100000>;
 245                         reg = <0x00 0x1700000 0x0 0x100000>;
 246                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 247
 248                         sec_jr0: jr@10000 {
 249                                 compatible = "fsl,sec-v5.4-job-ring",
 250                                              "fsl,sec-v5.0-job-ring",
 251                                              "fsl,sec-v4.0-job-ring";
 252                                 reg        = <0x10000 0x10000>;
 253                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 254                         };
 255
 256                         sec_jr1: jr@20000 {
 257                                 compatible = "fsl,sec-v5.4-job-ring",
 258                                              "fsl,sec-v5.0-job-ring",
 259                                              "fsl,sec-v4.0-job-ring";
 260                                 reg        = <0x20000 0x10000>;
 261                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 262                         };
 263
 264                         sec_jr2: jr@30000 {
 265                                 compatible = "fsl,sec-v5.4-job-ring",
 266                                              "fsl,sec-v5.0-job-ring",
 267                                              "fsl,sec-v4.0-job-ring";
 268                                 reg        = <0x30000 0x10000>;
 269                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 270                         };
 271
 272                         sec_jr3: jr@40000 {
 273                                 compatible = "fsl,sec-v5.4-job-ring",
 274                                              "fsl,sec-v5.0-job-ring",
 275                                              "fsl,sec-v4.0-job-ring";
 276                                 reg        = <0x40000 0x10000>;
 277                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 278                         };
 279                 };
 280
 281                 qman: qman@1880000 {
 282                         compatible = "fsl,qman";
 283                         reg = <0x0 0x1880000 0x0 0x10000>;
 284                         interrupts = <0 45 0x4>;
 285                         memory-region = <&qman_fqd &qman_pfdr>;
 286
 287                 };
 288
 289                 bman: bman@1890000 {
 290                         compatible = "fsl,bman";
 291                         reg = <0x0 0x1890000 0x0 0x10000>;
 292                         interrupts = <0 45 0x4>;
 293                         memory-region = <&bman_fbpr>;
 294
 295                 };
 296
 297                 qportals: qman-portals@500000000 {
 298                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 299                 };
 300
 301                 bportals: bman-portals@508000000 {
 302                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 303                 };
 304
 305                 dcfg: dcfg@1ee0000 {
 306                         compatible = "fsl,ls1046a-dcfg", "syscon";
 307                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 308                         big-endian;
 309                 };
 310
 311                 clockgen: clocking@1ee1000 {
 312                         compatible = "fsl,ls1046a-clockgen";
 313                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 314                         #clock-cells = <2>;
 315                         clocks = <&sysclk>;
 316                 };
 317
 318                 tmu: tmu@1f00000 {
 319                         compatible = "fsl,qoriq-tmu";
 320                         reg = <0x0 0x1f00000 0x0 0x10000>;
 321                         interrupts = <0 33 0x4>;
 322                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 323                         fsl,tmu-calibration =
 324                                 /* Calibration data group 1 */
 325                                 <0x00000000 0x00000026
 326                                 0x00000001 0x0000002d
 327                                 0x00000002 0x00000032
 328                                 0x00000003 0x00000039
 329                                 0x00000004 0x0000003f
 330                                 0x00000005 0x00000046
 331                                 0x00000006 0x0000004d
 332                                 0x00000007 0x00000054
 333                                 0x00000008 0x0000005a
 334                                 0x00000009 0x00000061
 335                                 0x0000000a 0x0000006a
 336                                 0x0000000b 0x00000071
 337                                 /* Calibration data group 2 */
 338                                 0x00010000 0x00000025
 339                                 0x00010001 0x0000002c
 340                                 0x00010002 0x00000035
 341                                 0x00010003 0x0000003d
 342                                 0x00010004 0x00000045
 343                                 0x00010005 0x0000004e
 344                                 0x00010006 0x00000057
 345                                 0x00010007 0x00000061
 346                                 0x00010008 0x0000006b
 347                                 0x00010009 0x00000076
 348                                 /* Calibration data group 3 */
 349                                 0x00020000 0x00000029
 350                                 0x00020001 0x00000033
 351                                 0x00020002 0x0000003d
 352                                 0x00020003 0x00000049
 353                                 0x00020004 0x00000056
 354                                 0x00020005 0x00000061
 355                                 0x00020006 0x0000006d
 356                                 /* Calibration data group 4 */
 357                                 0x00030000 0x00000021
 358                                 0x00030001 0x0000002a
 359                                 0x00030002 0x0000003c
 360                                 0x00030003 0x0000004e>;
 361                         big-endian;
 362                         #thermal-sensor-cells = <1>;
 363                 };
 364
 365                 thermal-zones {
 366                         cpu_thermal: cpu-thermal {
 367                                 polling-delay-passive = <1000>;
 368                                 polling-delay = <5000>;
 369                                 thermal-sensors = <&tmu 3>;
 370
 371                                 trips {
 372                                         cpu_alert: cpu-alert {
 373                                                 temperature = <85000>;
 374                                                 hysteresis = <2000>;
 375                                                 type = "passive";
 376                                         };
 377
 378                                         cpu_crit: cpu-crit {
 379                                                 temperature = <95000>;
 380                                                 hysteresis = <2000>;
 381                                                 type = "critical";
 382                                         };
 383                                 };
 384
 385                                 cooling-maps {
 386                                         map0 {
 387                                                 trip = <&cpu_alert>;
 388                                                 cooling-device =
 389                                                         <&cpu0 THERMAL_NO_LIMIT
 390                                                         THERMAL_NO_LIMIT>;
 391                                         };
 392                                 };
 393                         };
 394                 };
 395
 396                 dspi: dspi@2100000 {
 397                         compatible = "fsl,ls1021a-v1.0-dspi";
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         reg = <0x0 0x2100000 0x0 0x10000>;
 401                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 402                         clock-names = "dspi";
 403                         clocks = <&clockgen 4 1>;
 404                         spi-num-chipselects = <5>;
 405                         big-endian;
 406                         status = "disabled";
 407                 };
 408
 409                 i2c0: i2c@2180000 {
 410                         compatible = "fsl,vf610-i2c";
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         reg = <0x0 0x2180000 0x0 0x10000>;
 414                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 415                         clocks = <&clockgen 4 1>;
 416                         dmas = <&edma0 1 39>,
 417                                <&edma0 1 38>;
 418                         dma-names = "tx", "rx";
 419                         status = "disabled";
 420                 };
 421
 422                 i2c1: i2c@2190000 {
 423                         compatible = "fsl,vf610-i2c";
 424                         #address-cells = <1>;
 425                         #size-cells = <0>;
 426                         reg = <0x0 0x2190000 0x0 0x10000>;
 427                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 428                         clocks = <&clockgen 4 1>;
 429                         status = "disabled";
 430                 };
 431
 432                 i2c2: i2c@21a0000 {
 433                         compatible = "fsl,vf610-i2c";
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         reg = <0x0 0x21a0000 0x0 0x10000>;
 437                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&clockgen 4 1>;
 439                         status = "disabled";
 440                 };
 441
 442                 i2c3: i2c@21b0000 {
 443                         compatible = "fsl,vf610-i2c";
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         reg = <0x0 0x21b0000 0x0 0x10000>;
 447                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 448                         clocks = <&clockgen 4 1>;
 449                         status = "disabled";
 450                 };
 451
 452                 duart0: serial@21c0500 {
 453                         compatible = "fsl,ns16550", "ns16550a";
 454                         reg = <0x00 0x21c0500 0x0 0x100>;
 455                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&clockgen 4 1>;
 457                 };
 458
 459                 duart1: serial@21c0600 {
 460                         compatible = "fsl,ns16550", "ns16550a";
 461                         reg = <0x00 0x21c0600 0x0 0x100>;
 462                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 463                         clocks = <&clockgen 4 1>;
 464                 };
 465
 466                 duart2: serial@21d0500 {
 467                         compatible = "fsl,ns16550", "ns16550a";
 468                         reg = <0x0 0x21d0500 0x0 0x100>;
 469                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 470                         clocks = <&clockgen 4 1>;
 471                 };
 472
 473                 duart3: serial@21d0600 {
 474                         compatible = "fsl,ns16550", "ns16550a";
 475                         reg = <0x0 0x21d0600 0x0 0x100>;
 476                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 477                         clocks = <&clockgen 4 1>;
 478                 };
 479
 480                 gpio0: gpio@2300000 {
 481                         compatible = "fsl,qoriq-gpio";
 482                         reg = <0x0 0x2300000 0x0 0x10000>;
 483                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 484                         gpio-controller;
 485                         #gpio-cells = <2>;
 486                         interrupt-controller;
 487                         #interrupt-cells = <2>;
 488                 };
 489
 490                 gpio1: gpio@2310000 {
 491                         compatible = "fsl,qoriq-gpio";
 492                         reg = <0x0 0x2310000 0x0 0x10000>;
 493                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 494                         gpio-controller;
 495                         #gpio-cells = <2>;
 496                         interrupt-controller;
 497                         #interrupt-cells = <2>;
 498                 };
 499
 500                 gpio2: gpio@2320000 {
 501                         compatible = "fsl,qoriq-gpio";
 502                         reg = <0x0 0x2320000 0x0 0x10000>;
 503                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 504                         gpio-controller;
 505                         #gpio-cells = <2>;
 506                         interrupt-controller;
 507                         #interrupt-cells = <2>;
 508                 };
 509
 510                 gpio3: gpio@2330000 {
 511                         compatible = "fsl,qoriq-gpio";
 512                         reg = <0x0 0x2330000 0x0 0x10000>;
 513                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 514                         gpio-controller;
 515                         #gpio-cells = <2>;
 516                         interrupt-controller;
 517                         #interrupt-cells = <2>;
 518                 };
 519
 520                 lpuart0: serial@2950000 {
 521                         compatible = "fsl,ls1021a-lpuart";
 522                         reg = <0x0 0x2950000 0x0 0x1000>;
 523                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&clockgen 4 0>;
 525                         clock-names = "ipg";
 526                         status = "disabled";
 527                 };
 528
 529                 lpuart1: serial@2960000 {
 530                         compatible = "fsl,ls1021a-lpuart";
 531                         reg = <0x0 0x2960000 0x0 0x1000>;
 532                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&clockgen 4 1>;
 534                         clock-names = "ipg";
 535                         status = "disabled";
 536                 };
 537
 538                 lpuart2: serial@2970000 {
 539                         compatible = "fsl,ls1021a-lpuart";
 540                         reg = <0x0 0x2970000 0x0 0x1000>;
 541                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 542                         clocks = <&clockgen 4 1>;
 543                         clock-names = "ipg";
 544                         status = "disabled";
 545                 };
 546
 547                 lpuart3: serial@2980000 {
 548                         compatible = "fsl,ls1021a-lpuart";
 549                         reg = <0x0 0x2980000 0x0 0x1000>;
 550                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&clockgen 4 1>;
 552                         clock-names = "ipg";
 553                         status = "disabled";
 554                 };
 555
 556                 lpuart4: serial@2990000 {
 557                         compatible = "fsl,ls1021a-lpuart";
 558                         reg = <0x0 0x2990000 0x0 0x1000>;
 559                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 560                         clocks = <&clockgen 4 1>;
 561                         clock-names = "ipg";
 562                         status = "disabled";
 563                 };
 564
 565                 lpuart5: serial@29a0000 {
 566                         compatible = "fsl,ls1021a-lpuart";
 567                         reg = <0x0 0x29a0000 0x0 0x1000>;
 568                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 569                         clocks = <&clockgen 4 1>;
 570                         clock-names = "ipg";
 571                         status = "disabled";
 572                 };
 573
 574                 wdog0: watchdog@2ad0000 {
 575                         compatible = "fsl,imx21-wdt";
 576                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 577                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 578                         clocks = <&clockgen 4 1>;
 579                         big-endian;
 580                 };
 581
 582                 edma0: edma@2c00000 {
 583                         #dma-cells = <2>;
 584                         compatible = "fsl,vf610-edma";
 585                         reg = <0x0 0x2c00000 0x0 0x10000>,
 586                               <0x0 0x2c10000 0x0 0x10000>,
 587                               <0x0 0x2c20000 0x0 0x10000>;
 588                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 590                         interrupt-names = "edma-tx", "edma-err";
 591                         dma-channels = <32>;
 592                         big-endian;
 593                         clock-names = "dmamux0", "dmamux1";
 594                         clocks = <&clockgen 4 1>,
 595                                  <&clockgen 4 1>;
 596                 };
 597
 598                 usb0: usb@2f00000 {
 599                         compatible = "snps,dwc3";
 600                         reg = <0x0 0x2f00000 0x0 0x10000>;
 601                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 602                         dr_mode = "host";
 603                         snps,quirk-frame-length-adjustment = <0x20>;
 604                         snps,dis_rxdet_inp3_quirk;
 605                 };
 606
 607                 usb1: usb@3000000 {
 608                         compatible = "snps,dwc3";
 609                         reg = <0x0 0x3000000 0x0 0x10000>;
 610                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 611                         dr_mode = "host";
 612                         snps,quirk-frame-length-adjustment = <0x20>;
 613                         snps,dis_rxdet_inp3_quirk;
 614                 };
 615
 616                 usb2: usb@3100000 {
 617                         compatible = "snps,dwc3";
 618                         reg = <0x0 0x3100000 0x0 0x10000>;
 619                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 620                         dr_mode = "host";
 621                         snps,quirk-frame-length-adjustment = <0x20>;
 622                         snps,dis_rxdet_inp3_quirk;
 623                 };
 624
 625                 sata: sata@3200000 {
 626                         compatible = "fsl,ls1046a-ahci";
 627                         reg = <0x0 0x3200000 0x0 0x10000>,
 628                                 <0x0 0x20140520 0x0 0x4>;
 629                         reg-names = "ahci", "sata-ecc";
 630                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&clockgen 4 1>;
 632                 };
 633
 634                 msi1: msi-controller@1580000 {
 635                         compatible = "fsl,ls1046a-msi";
 636                         msi-controller;
 637                         reg = <0x0 0x1580000 0x0 0x10000>;
 638                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 639                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 640                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 641                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 642                 };
 643
 644                 msi2: msi-controller@1590000 {
 645                         compatible = "fsl,ls1046a-msi";
 646                         msi-controller;
 647                         reg = <0x0 0x1590000 0x0 0x10000>;
 648                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 651                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 652                 };
 653
 654                 msi3: msi-controller@15a0000 {
 655                         compatible = "fsl,ls1046a-msi";
 656                         msi-controller;
 657                         reg = <0x0 0x15a0000 0x0 0x10000>;
 658                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 659                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 660                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 661                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 662                 };
 663
 664         };
 665
 666         reserved-memory {
 667                 #address-cells = <2>;
 668                 #size-cells = <2>;
 669                 ranges;
 670
 671                 bman_fbpr: bman-fbpr {
 672                         compatible = "shared-dma-pool";
 673                         size = <0 0x1000000>;
 674                         alignment = <0 0x1000000>;
 675                         no-map;
 676                 };
 677
 678                 qman_fqd: qman-fqd {
 679                         compatible = "shared-dma-pool";
 680                         size = <0 0x800000>;
 681                         alignment = <0 0x800000>;
 682                         no-map;
 683                 };
 684
 685                 qman_pfdr: qman-pfdr {
 686                         compatible = "shared-dma-pool";
 687                         size = <0 0x2000000>;
 688                         alignment = <0 0x2000000>;
 689                         no-map;
 690                 };
 691         };
 692 };
 693
 694 #include "qoriq-qman-portals.dtsi"
 695 #include "qoriq-bman-portals.dtsi"