1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
8 * Mingkai Hu <mingkai.hu@nxp.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
15 compatible = "fsl,ls1046a";
16 interrupt-parent = <&gic>;
39 compatible = "arm,cortex-a72";
41 clocks = <&clockgen 1 0>;
42 next-level-cache = <&l2>;
43 cpu-idle-states = <&CPU_PH20>;
49 compatible = "arm,cortex-a72";
51 clocks = <&clockgen 1 0>;
52 next-level-cache = <&l2>;
53 cpu-idle-states = <&CPU_PH20>;
59 compatible = "arm,cortex-a72";
61 clocks = <&clockgen 1 0>;
62 next-level-cache = <&l2>;
63 cpu-idle-states = <&CPU_PH20>;
69 compatible = "arm,cortex-a72";
71 clocks = <&clockgen 1 0>;
72 next-level-cache = <&l2>;
73 cpu-idle-states = <&CPU_PH20>;
84 * PSCI node is not added default, U-boot will add missing
85 * parts if it determines to use PSCI.
87 entry-method = "psci";
90 compatible = "arm,idle-state";
91 idle-state-name = "PH20";
92 arm,psci-suspend-param = <0x0>;
93 entry-latency-us = <1000>;
94 exit-latency-us = <1000>;
95 min-residency-us = <3000>;
100 device_type = "memory";
101 /* Real size will be filled by bootloader */
102 reg = <0x0 0x80000000 0x0 0x0>;
106 compatible = "fixed-clock";
108 clock-frequency = <100000000>;
109 clock-output-names = "sysclk";
113 compatible ="syscon-reboot";
120 cpu_thermal: cpu-thermal {
121 polling-delay-passive = <1000>;
122 polling-delay = <5000>;
123 thermal-sensors = <&tmu 3>;
126 cpu_alert: cpu-alert {
127 temperature = <85000>;
133 temperature = <95000>;
143 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
144 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
145 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
146 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
153 compatible = "arm,armv8-timer";
154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
155 IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
157 IRQ_TYPE_LEVEL_LOW)>,
158 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
159 IRQ_TYPE_LEVEL_LOW)>,
160 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
161 IRQ_TYPE_LEVEL_LOW)>;
165 compatible = "arm,cortex-a72-pmu";
166 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
168 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
169 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-affinity = <&cpu0>,
176 gic: interrupt-controller@1400000 {
177 compatible = "arm,gic-400";
178 #interrupt-cells = <3>;
179 interrupt-controller;
180 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
181 <0x0 0x1420000 0 0x20000>, /* GICC */
182 <0x0 0x1440000 0 0x20000>, /* GICH */
183 <0x0 0x1460000 0 0x20000>; /* GICV */
184 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
185 IRQ_TYPE_LEVEL_LOW)>;
189 compatible = "simple-bus";
190 #address-cells = <2>;
194 ddr: memory-controller@1080000 {
195 compatible = "fsl,qoriq-memory-controller";
196 reg = <0x0 0x1080000 0x0 0x1000>;
197 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
202 compatible = "fsl,ifc", "simple-bus";
203 reg = <0x0 0x1530000 0x0 0x10000>;
204 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
209 compatible = "fsl,ls1021a-qspi";
210 #address-cells = <1>;
212 reg = <0x0 0x1550000 0x0 0x10000>,
213 <0x0 0x40000000 0x0 0x10000000>;
214 reg-names = "QuadSPI", "QuadSPI-memory";
215 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
216 clock-names = "qspi_en", "qspi";
217 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
219 fsl,qspi-has-second-chip;
223 esdhc: esdhc@1560000 {
224 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
225 reg = <0x0 0x1560000 0x0 0x10000>;
226 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clockgen 2 1>;
228 voltage-ranges = <1800 1800 3300 3300>;
235 compatible = "fsl,ls1046a-scfg", "syscon";
236 reg = <0x0 0x1570000 0x0 0x10000>;
240 crypto: crypto@1700000 {
241 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
244 #address-cells = <1>;
246 ranges = <0x0 0x00 0x1700000 0x100000>;
247 reg = <0x00 0x1700000 0x0 0x100000>;
248 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
251 compatible = "fsl,sec-v5.4-job-ring",
252 "fsl,sec-v5.0-job-ring",
253 "fsl,sec-v4.0-job-ring";
254 reg = <0x10000 0x10000>;
255 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
259 compatible = "fsl,sec-v5.4-job-ring",
260 "fsl,sec-v5.0-job-ring",
261 "fsl,sec-v4.0-job-ring";
262 reg = <0x20000 0x10000>;
263 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
267 compatible = "fsl,sec-v5.4-job-ring",
268 "fsl,sec-v5.0-job-ring",
269 "fsl,sec-v4.0-job-ring";
270 reg = <0x30000 0x10000>;
271 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
275 compatible = "fsl,sec-v5.4-job-ring",
276 "fsl,sec-v5.0-job-ring",
277 "fsl,sec-v4.0-job-ring";
278 reg = <0x40000 0x10000>;
279 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
284 compatible = "fsl,qman";
285 reg = <0x0 0x1880000 0x0 0x10000>;
286 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
287 memory-region = <&qman_fqd &qman_pfdr>;
292 compatible = "fsl,bman";
293 reg = <0x0 0x1890000 0x0 0x10000>;
294 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
295 memory-region = <&bman_fbpr>;
299 qportals: qman-portals@500000000 {
300 ranges = <0x0 0x5 0x00000000 0x8000000>;
303 bportals: bman-portals@508000000 {
304 ranges = <0x0 0x5 0x08000000 0x8000000>;
308 compatible = "fsl,ls1046a-dcfg", "syscon";
309 reg = <0x0 0x1ee0000 0x0 0x10000>;
313 clockgen: clocking@1ee1000 {
314 compatible = "fsl,ls1046a-clockgen";
315 reg = <0x0 0x1ee1000 0x0 0x1000>;
321 compatible = "fsl,qoriq-tmu";
322 reg = <0x0 0x1f00000 0x0 0x10000>;
323 interrupts = <0 33 0x4>;
324 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
325 fsl,tmu-calibration =
326 /* Calibration data group 1 */
327 <0x00000000 0x00000026
328 0x00000001 0x0000002d
329 0x00000002 0x00000032
330 0x00000003 0x00000039
331 0x00000004 0x0000003f
332 0x00000005 0x00000046
333 0x00000006 0x0000004d
334 0x00000007 0x00000054
335 0x00000008 0x0000005a
336 0x00000009 0x00000061
337 0x0000000a 0x0000006a
338 0x0000000b 0x00000071
339 /* Calibration data group 2 */
340 0x00010000 0x00000025
341 0x00010001 0x0000002c
342 0x00010002 0x00000035
343 0x00010003 0x0000003d
344 0x00010004 0x00000045
345 0x00010005 0x0000004e
346 0x00010006 0x00000057
347 0x00010007 0x00000061
348 0x00010008 0x0000006b
349 0x00010009 0x00000076
350 /* Calibration data group 3 */
351 0x00020000 0x00000029
352 0x00020001 0x00000033
353 0x00020002 0x0000003d
354 0x00020003 0x00000049
355 0x00020004 0x00000056
356 0x00020005 0x00000061
357 0x00020006 0x0000006d
358 /* Calibration data group 4 */
359 0x00030000 0x00000021
360 0x00030001 0x0000002a
361 0x00030002 0x0000003c
362 0x00030003 0x0000004e>;
364 #thermal-sensor-cells = <1>;
368 compatible = "fsl,ls1021a-v1.0-dspi";
369 #address-cells = <1>;
371 reg = <0x0 0x2100000 0x0 0x10000>;
372 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
373 clock-names = "dspi";
374 clocks = <&clockgen 4 1>;
375 spi-num-chipselects = <5>;
381 compatible = "fsl,vf610-i2c";
382 #address-cells = <1>;
384 reg = <0x0 0x2180000 0x0 0x10000>;
385 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&clockgen 4 1>;
387 dmas = <&edma0 1 39>,
389 dma-names = "tx", "rx";
394 compatible = "fsl,vf610-i2c";
395 #address-cells = <1>;
397 reg = <0x0 0x2190000 0x0 0x10000>;
398 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&clockgen 4 1>;
404 compatible = "fsl,vf610-i2c";
405 #address-cells = <1>;
407 reg = <0x0 0x21a0000 0x0 0x10000>;
408 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&clockgen 4 1>;
414 compatible = "fsl,vf610-i2c";
415 #address-cells = <1>;
417 reg = <0x0 0x21b0000 0x0 0x10000>;
418 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clockgen 4 1>;
423 duart0: serial@21c0500 {
424 compatible = "fsl,ns16550", "ns16550a";
425 reg = <0x00 0x21c0500 0x0 0x100>;
426 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clockgen 4 1>;
431 duart1: serial@21c0600 {
432 compatible = "fsl,ns16550", "ns16550a";
433 reg = <0x00 0x21c0600 0x0 0x100>;
434 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clockgen 4 1>;
439 duart2: serial@21d0500 {
440 compatible = "fsl,ns16550", "ns16550a";
441 reg = <0x0 0x21d0500 0x0 0x100>;
442 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clockgen 4 1>;
447 duart3: serial@21d0600 {
448 compatible = "fsl,ns16550", "ns16550a";
449 reg = <0x0 0x21d0600 0x0 0x100>;
450 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clockgen 4 1>;
455 gpio0: gpio@2300000 {
456 compatible = "fsl,qoriq-gpio";
457 reg = <0x0 0x2300000 0x0 0x10000>;
458 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
465 gpio1: gpio@2310000 {
466 compatible = "fsl,qoriq-gpio";
467 reg = <0x0 0x2310000 0x0 0x10000>;
468 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
475 gpio2: gpio@2320000 {
476 compatible = "fsl,qoriq-gpio";
477 reg = <0x0 0x2320000 0x0 0x10000>;
478 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
485 gpio3: gpio@2330000 {
486 compatible = "fsl,qoriq-gpio";
487 reg = <0x0 0x2330000 0x0 0x10000>;
488 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
491 interrupt-controller;
492 #interrupt-cells = <2>;
495 lpuart0: serial@2950000 {
496 compatible = "fsl,ls1021a-lpuart";
497 reg = <0x0 0x2950000 0x0 0x1000>;
498 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clockgen 4 0>;
504 lpuart1: serial@2960000 {
505 compatible = "fsl,ls1021a-lpuart";
506 reg = <0x0 0x2960000 0x0 0x1000>;
507 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&clockgen 4 1>;
513 lpuart2: serial@2970000 {
514 compatible = "fsl,ls1021a-lpuart";
515 reg = <0x0 0x2970000 0x0 0x1000>;
516 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clockgen 4 1>;
522 lpuart3: serial@2980000 {
523 compatible = "fsl,ls1021a-lpuart";
524 reg = <0x0 0x2980000 0x0 0x1000>;
525 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clockgen 4 1>;
531 lpuart4: serial@2990000 {
532 compatible = "fsl,ls1021a-lpuart";
533 reg = <0x0 0x2990000 0x0 0x1000>;
534 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&clockgen 4 1>;
540 lpuart5: serial@29a0000 {
541 compatible = "fsl,ls1021a-lpuart";
542 reg = <0x0 0x29a0000 0x0 0x1000>;
543 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clockgen 4 1>;
549 wdog0: watchdog@2ad0000 {
550 compatible = "fsl,imx21-wdt";
551 reg = <0x0 0x2ad0000 0x0 0x10000>;
552 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&clockgen 4 1>;
557 edma0: edma@2c00000 {
559 compatible = "fsl,vf610-edma";
560 reg = <0x0 0x2c00000 0x0 0x10000>,
561 <0x0 0x2c10000 0x0 0x10000>,
562 <0x0 0x2c20000 0x0 0x10000>;
563 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "edma-tx", "edma-err";
568 clock-names = "dmamux0", "dmamux1";
569 clocks = <&clockgen 4 1>,
574 compatible = "snps,dwc3";
575 reg = <0x0 0x2f00000 0x0 0x10000>;
576 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
578 snps,quirk-frame-length-adjustment = <0x20>;
579 snps,dis_rxdet_inp3_quirk;
580 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
584 compatible = "snps,dwc3";
585 reg = <0x0 0x3000000 0x0 0x10000>;
586 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
588 snps,quirk-frame-length-adjustment = <0x20>;
589 snps,dis_rxdet_inp3_quirk;
590 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
594 compatible = "snps,dwc3";
595 reg = <0x0 0x3100000 0x0 0x10000>;
596 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
598 snps,quirk-frame-length-adjustment = <0x20>;
599 snps,dis_rxdet_inp3_quirk;
600 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
604 compatible = "fsl,ls1046a-ahci";
605 reg = <0x0 0x3200000 0x0 0x10000>,
606 <0x0 0x20140520 0x0 0x4>;
607 reg-names = "ahci", "sata-ecc";
608 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&clockgen 4 1>;
612 msi1: msi-controller@1580000 {
613 compatible = "fsl,ls1046a-msi";
615 reg = <0x0 0x1580000 0x0 0x10000>;
616 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
618 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
619 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
622 msi2: msi-controller@1590000 {
623 compatible = "fsl,ls1046a-msi";
625 reg = <0x0 0x1590000 0x0 0x10000>;
626 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
627 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
628 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
632 msi3: msi-controller@15a0000 {
633 compatible = "fsl,ls1046a-msi";
635 reg = <0x0 0x15a0000 0x0 0x10000>;
636 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
643 compatible = "fsl,ls1046a-pcie";
644 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
645 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
646 reg-names = "regs", "config";
647 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
648 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
649 interrupt-names = "aer", "pme";
650 #address-cells = <3>;
656 bus-range = <0x0 0xff>;
657 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
658 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
659 msi-parent = <&msi1>, <&msi2>, <&msi3>;
660 #interrupt-cells = <1>;
661 interrupt-map-mask = <0 0 0 7>;
662 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
663 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
664 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
665 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
670 compatible = "fsl,ls1046a-pcie";
671 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
672 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
673 reg-names = "regs", "config";
674 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
675 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
676 interrupt-names = "aer", "pme";
677 #address-cells = <3>;
683 bus-range = <0x0 0xff>;
684 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
685 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
686 msi-parent = <&msi2>, <&msi3>, <&msi1>;
687 #interrupt-cells = <1>;
688 interrupt-map-mask = <0 0 0 7>;
689 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
690 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
691 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
692 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
697 compatible = "fsl,ls1046a-pcie";
698 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
699 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
700 reg-names = "regs", "config";
701 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
702 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
703 interrupt-names = "aer", "pme";
704 #address-cells = <3>;
710 bus-range = <0x0 0xff>;
711 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
712 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
713 msi-parent = <&msi3>, <&msi1>, <&msi2>;
714 #interrupt-cells = <1>;
715 interrupt-map-mask = <0 0 0 7>;
716 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
717 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
718 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
719 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
723 qdma: dma-controller@8380000 {
724 compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
725 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
726 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
727 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
728 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
733 interrupt-names = "qdma-error", "qdma-queue0",
734 "qdma-queue1", "qdma-queue2", "qdma-queue3";
737 block-offset = <0x10000>;
738 fsl,dma-queues = <2>;
740 queue-sizes = <64 64>;
747 #address-cells = <2>;
751 bman_fbpr: bman-fbpr {
752 compatible = "shared-dma-pool";
753 size = <0 0x1000000>;
754 alignment = <0 0x1000000>;
759 compatible = "shared-dma-pool";
761 alignment = <0 0x800000>;
765 qman_pfdr: qman-pfdr {
766 compatible = "shared-dma-pool";
767 size = <0 0x2000000>;
768 alignment = <0 0x2000000>;
775 compatible = "linaro,optee-tz";
781 #include "qoriq-qman-portals.dtsi"
782 #include "qoriq-bman-portals.dtsi"