arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
   4  *
   5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   6  * Copyright 2018 NXP
   7  *
   8  * Mingkai Hu <Mingkai.hu@freescale.com>
   9  */
  10
  11 #include <dt-bindings/thermal/thermal.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14 / {
  15         compatible = "fsl,ls1043a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 fman0 = &fman0;
  22                 ethernet0 = &enet0;
  23                 ethernet1 = &enet1;
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26                 ethernet4 = &enet4;
  27                 ethernet5 = &enet5;
  28                 ethernet6 = &enet6;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 /*
  36                  * We expect the enable-method for cpu's to be "psci", but this
  37                  * is dependent on the SoC FW, which will fill this in.
  38                  *
  39                  * Currently supported enable-method is psci v0.2
  40                  */
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0x0>;
  45                         clocks = <&clockgen 1 0>;
  46                         next-level-cache = <&l2>;
  47                         cpu-idle-states = <&CPU_PH20>;
  48                         #cooling-cells = <2>;
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x1>;
  55                         clocks = <&clockgen 1 0>;
  56                         next-level-cache = <&l2>;
  57                         cpu-idle-states = <&CPU_PH20>;
  58                         #cooling-cells = <2>;
  59                 };
  60
  61                 cpu2: cpu@2 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         reg = <0x2>;
  65                         clocks = <&clockgen 1 0>;
  66                         next-level-cache = <&l2>;
  67                         cpu-idle-states = <&CPU_PH20>;
  68                         #cooling-cells = <2>;
  69                 };
  70
  71                 cpu3: cpu@3 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x3>;
  75                         clocks = <&clockgen 1 0>;
  76                         next-level-cache = <&l2>;
  77                         cpu-idle-states = <&CPU_PH20>;
  78                         #cooling-cells = <2>;
  79                 };
  80
  81                 l2: l2-cache {
  82                         compatible = "cache";
  83                 };
  84         };
  85
  86         idle-states {
  87                 /*
  88                  * PSCI node is not added default, U-boot will add missing
  89                  * parts if it determines to use PSCI.
  90                  */
  91                 entry-method = "psci";
  92
  93                 CPU_PH20: cpu-ph20 {
  94                         compatible = "arm,idle-state";
  95                         idle-state-name = "PH20";
  96                         arm,psci-suspend-param = <0x0>;
  97                         entry-latency-us = <1000>;
  98                         exit-latency-us = <1000>;
  99                         min-residency-us = <3000>;
 100                 };
 101         };
 102
 103         memory@80000000 {
 104                 device_type = "memory";
 105                 reg = <0x0 0x80000000 0 0x80000000>;
 106                       /* DRAM space 1, size: 2GiB DRAM */
 107         };
 108
 109         reserved-memory {
 110                 #address-cells = <2>;
 111                 #size-cells = <2>;
 112                 ranges;
 113
 114                 bman_fbpr: bman-fbpr {
 115                         compatible = "shared-dma-pool";
 116                         size = <0 0x1000000>;
 117                         alignment = <0 0x1000000>;
 118                         no-map;
 119                 };
 120
 121                 qman_fqd: qman-fqd {
 122                         compatible = "shared-dma-pool";
 123                         size = <0 0x400000>;
 124                         alignment = <0 0x400000>;
 125                         no-map;
 126                 };
 127
 128                 qman_pfdr: qman-pfdr {
 129                         compatible = "shared-dma-pool";
 130                         size = <0 0x2000000>;
 131                         alignment = <0 0x2000000>;
 132                         no-map;
 133                 };
 134         };
 135
 136         sysclk: sysclk {
 137                 compatible = "fixed-clock";
 138                 #clock-cells = <0>;
 139                 clock-frequency = <100000000>;
 140                 clock-output-names = "sysclk";
 141         };
 142
 143         reboot {
 144                 compatible ="syscon-reboot";
 145                 regmap = <&dcfg>;
 146                 offset = <0xb0>;
 147                 mask = <0x02>;
 148         };
 149
 150         thermal-zones {
 151                 cpu_thermal: cpu-thermal {
 152                         polling-delay-passive = <1000>;
 153                         polling-delay = <5000>;
 154
 155                         thermal-sensors = <&tmu 3>;
 156
 157                         trips {
 158                                 cpu_alert: cpu-alert {
 159                                         temperature = <85000>;
 160                                         hysteresis = <2000>;
 161                                         type = "passive";
 162                                 };
 163                                 cpu_crit: cpu-crit {
 164                                         temperature = <95000>;
 165                                         hysteresis = <2000>;
 166                                         type = "critical";
 167                                 };
 168                         };
 169
 170                         cooling-maps {
 171                                 map0 {
 172                                         trip = <&cpu_alert>;
 173                                         cooling-device =
 174                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 175                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 176                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 177                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 178                                 };
 179                         };
 180                 };
 181         };
 182
 183         timer {
 184                 compatible = "arm,armv8-timer";
 185                 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
 186                              <1 14 0xf08>, /* Physical Non-Secure PPI */
 187                              <1 11 0xf08>, /* Virtual PPI */
 188                              <1 10 0xf08>; /* Hypervisor PPI */
 189                 fsl,erratum-a008585;
 190         };
 191
 192         pmu {
 193                 compatible = "arm,armv8-pmuv3";
 194                 interrupts = <0 106 0x4>,
 195                              <0 107 0x4>,
 196                              <0 95 0x4>,
 197                              <0 97 0x4>;
 198                 interrupt-affinity = <&cpu0>,
 199                                      <&cpu1>,
 200                                      <&cpu2>,
 201                                      <&cpu3>;
 202         };
 203
 204         gic: interrupt-controller@1400000 {
 205                 compatible = "arm,gic-400";
 206                 #interrupt-cells = <3>;
 207                 interrupt-controller;
 208                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
 209                       <0x0 0x1402000 0 0x2000>, /* GICC */
 210                       <0x0 0x1404000 0 0x2000>, /* GICH */
 211                       <0x0 0x1406000 0 0x2000>; /* GICV */
 212                 interrupts = <1 9 0xf08>;
 213         };
 214
 215         soc: soc {
 216                 compatible = "simple-bus";
 217                 #address-cells = <2>;
 218                 #size-cells = <2>;
 219                 ranges;
 220
 221                 clockgen: clocking@1ee1000 {
 222                         compatible = "fsl,ls1043a-clockgen";
 223                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 224                         #clock-cells = <2>;
 225                         clocks = <&sysclk>;
 226                 };
 227
 228                 scfg: scfg@1570000 {
 229                         compatible = "fsl,ls1043a-scfg", "syscon";
 230                         reg = <0x0 0x1570000 0x0 0x10000>;
 231                         big-endian;
 232                 };
 233
 234                 crypto: crypto@1700000 {
 235                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 236                                      "fsl,sec-v4.0";
 237                         fsl,sec-era = <3>;
 238                         #address-cells = <1>;
 239                         #size-cells = <1>;
 240                         ranges = <0x0 0x00 0x1700000 0x100000>;
 241                         reg = <0x00 0x1700000 0x0 0x100000>;
 242                         interrupts = <0 75 0x4>;
 243
 244                         sec_jr0: jr@10000 {
 245                                 compatible = "fsl,sec-v5.4-job-ring",
 246                                              "fsl,sec-v5.0-job-ring",
 247                                              "fsl,sec-v4.0-job-ring";
 248                                 reg        = <0x10000 0x10000>;
 249                                 interrupts = <0 71 0x4>;
 250                         };
 251
 252                         sec_jr1: jr@20000 {
 253                                 compatible = "fsl,sec-v5.4-job-ring",
 254                                              "fsl,sec-v5.0-job-ring",
 255                                              "fsl,sec-v4.0-job-ring";
 256                                 reg        = <0x20000 0x10000>;
 257                                 interrupts = <0 72 0x4>;
 258                         };
 259
 260                         sec_jr2: jr@30000 {
 261                                 compatible = "fsl,sec-v5.4-job-ring",
 262                                              "fsl,sec-v5.0-job-ring",
 263                                              "fsl,sec-v4.0-job-ring";
 264                                 reg        = <0x30000 0x10000>;
 265                                 interrupts = <0 73 0x4>;
 266                         };
 267
 268                         sec_jr3: jr@40000 {
 269                                 compatible = "fsl,sec-v5.4-job-ring",
 270                                              "fsl,sec-v5.0-job-ring",
 271                                              "fsl,sec-v4.0-job-ring";
 272                                 reg        = <0x40000 0x10000>;
 273                                 interrupts = <0 74 0x4>;
 274                         };
 275                 };
 276
 277                 dcfg: dcfg@1ee0000 {
 278                         compatible = "fsl,ls1043a-dcfg", "syscon";
 279                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 280                         big-endian;
 281                 };
 282
 283                 ifc: ifc@1530000 {
 284                         compatible = "fsl,ifc", "simple-bus";
 285                         reg = <0x0 0x1530000 0x0 0x10000>;
 286                         interrupts = <0 43 0x4>;
 287                 };
 288
 289                 qspi: spi@1550000 {
 290                         compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
 291                         #address-cells = <1>;
 292                         #size-cells = <0>;
 293                         reg = <0x0 0x1550000 0x0 0x10000>,
 294                                 <0x0 0x40000000 0x0 0x4000000>;
 295                         reg-names = "QuadSPI", "QuadSPI-memory";
 296                         interrupts = <0 99 0x4>;
 297                         clock-names = "qspi_en", "qspi";
 298                         clocks = <&clockgen 4 0>, <&clockgen 4 0>;
 299                         big-endian;
 300                         status = "disabled";
 301                 };
 302
 303                 esdhc: esdhc@1560000 {
 304                         compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
 305                         reg = <0x0 0x1560000 0x0 0x10000>;
 306                         interrupts = <0 62 0x4>;
 307                         clock-frequency = <0>;
 308                         voltage-ranges = <1800 1800 3300 3300>;
 309                         sdhci,auto-cmd12;
 310                         big-endian;
 311                         bus-width = <4>;
 312                 };
 313
 314                 ddr: memory-controller@1080000 {
 315                         compatible = "fsl,qoriq-memory-controller";
 316                         reg = <0x0 0x1080000 0x0 0x1000>;
 317                         interrupts = <0 144 0x4>;
 318                         big-endian;
 319                 };
 320
 321                 tmu: tmu@1f00000 {
 322                         compatible = "fsl,qoriq-tmu";
 323                         reg = <0x0 0x1f00000 0x0 0x10000>;
 324                         interrupts = <0 33 0x4>;
 325                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 326                         fsl,tmu-calibration = <0x00000000 0x00000026
 327                                                0x00000001 0x0000002d
 328                                                0x00000002 0x00000032
 329                                                0x00000003 0x00000039
 330                                                0x00000004 0x0000003f
 331                                                0x00000005 0x00000046
 332                                                0x00000006 0x0000004d
 333                                                0x00000007 0x00000054
 334                                                0x00000008 0x0000005a
 335                                                0x00000009 0x00000061
 336                                                0x0000000a 0x0000006a
 337                                                0x0000000b 0x00000071
 338
 339                                                0x00010000 0x00000025
 340                                                0x00010001 0x0000002c
 341                                                0x00010002 0x00000035
 342                                                0x00010003 0x0000003d
 343                                                0x00010004 0x00000045
 344                                                0x00010005 0x0000004e
 345                                                0x00010006 0x00000057
 346                                                0x00010007 0x00000061
 347                                                0x00010008 0x0000006b
 348                                                0x00010009 0x00000076
 349
 350                                                0x00020000 0x00000029
 351                                                0x00020001 0x00000033
 352                                                0x00020002 0x0000003d
 353                                                0x00020003 0x00000049
 354                                                0x00020004 0x00000056
 355                                                0x00020005 0x00000061
 356                                                0x00020006 0x0000006d
 357
 358                                                0x00030000 0x00000021
 359                                                0x00030001 0x0000002a
 360                                                0x00030002 0x0000003c
 361                                                0x00030003 0x0000004e>;
 362                         #thermal-sensor-cells = <1>;
 363                 };
 364
 365                 qman: qman@1880000 {
 366                         compatible = "fsl,qman";
 367                         reg = <0x0 0x1880000 0x0 0x10000>;
 368                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 369                         memory-region = <&qman_fqd &qman_pfdr>;
 370                 };
 371
 372                 bman: bman@1890000 {
 373                         compatible = "fsl,bman";
 374                         reg = <0x0 0x1890000 0x0 0x10000>;
 375                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 376                         memory-region = <&bman_fbpr>;
 377                 };
 378
 379                 bportals: bman-portals@508000000 {
 380                         ranges = <0x0 0x5 0x08000000 0x8000000>;
 381                 };
 382
 383                 qportals: qman-portals@500000000 {
 384                         ranges = <0x0 0x5 0x00000000 0x8000000>;
 385                 };
 386
 387                 dspi0: spi@2100000 {
 388                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         reg = <0x0 0x2100000 0x0 0x10000>;
 392                         interrupts = <0 64 0x4>;
 393                         clock-names = "dspi";
 394                         clocks = <&clockgen 4 0>;
 395                         spi-num-chipselects = <5>;
 396                         big-endian;
 397                         status = "disabled";
 398                 };
 399
 400                 dspi1: spi@2110000 {
 401                         compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         reg = <0x0 0x2110000 0x0 0x10000>;
 405                         interrupts = <0 65 0x4>;
 406                         clock-names = "dspi";
 407                         clocks = <&clockgen 4 0>;
 408                         spi-num-chipselects = <5>;
 409                         big-endian;
 410                         status = "disabled";
 411                 };
 412
 413                 i2c0: i2c@2180000 {
 414                         compatible = "fsl,vf610-i2c";
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         reg = <0x0 0x2180000 0x0 0x10000>;
 418                         interrupts = <0 56 0x4>;
 419                         clock-names = "i2c";
 420                         clocks = <&clockgen 4 0>;
 421                         dmas = <&edma0 1 39>,
 422                                <&edma0 1 38>;
 423                         dma-names = "tx", "rx";
 424                         status = "disabled";
 425                 };
 426
 427                 i2c1: i2c@2190000 {
 428                         compatible = "fsl,vf610-i2c";
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         reg = <0x0 0x2190000 0x0 0x10000>;
 432                         interrupts = <0 57 0x4>;
 433                         clock-names = "i2c";
 434                         clocks = <&clockgen 4 0>;
 435                         status = "disabled";
 436                 };
 437
 438                 i2c2: i2c@21a0000 {
 439                         compatible = "fsl,vf610-i2c";
 440                         #address-cells = <1>;
 441                         #size-cells = <0>;
 442                         reg = <0x0 0x21a0000 0x0 0x10000>;
 443                         interrupts = <0 58 0x4>;
 444                         clock-names = "i2c";
 445                         clocks = <&clockgen 4 0>;
 446                         status = "disabled";
 447                 };
 448
 449                 i2c3: i2c@21b0000 {
 450                         compatible = "fsl,vf610-i2c";
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         reg = <0x0 0x21b0000 0x0 0x10000>;
 454                         interrupts = <0 59 0x4>;
 455                         clock-names = "i2c";
 456                         clocks = <&clockgen 4 0>;
 457                         status = "disabled";
 458                 };
 459
 460                 duart0: serial@21c0500 {
 461                         compatible = "fsl,ns16550", "ns16550a";
 462                         reg = <0x00 0x21c0500 0x0 0x100>;
 463                         interrupts = <0 54 0x4>;
 464                         clocks = <&clockgen 4 0>;
 465                 };
 466
 467                 duart1: serial@21c0600 {
 468                         compatible = "fsl,ns16550", "ns16550a";
 469                         reg = <0x00 0x21c0600 0x0 0x100>;
 470                         interrupts = <0 54 0x4>;
 471                         clocks = <&clockgen 4 0>;
 472                 };
 473
 474                 duart2: serial@21d0500 {
 475                         compatible = "fsl,ns16550", "ns16550a";
 476                         reg = <0x0 0x21d0500 0x0 0x100>;
 477                         interrupts = <0 55 0x4>;
 478                         clocks = <&clockgen 4 0>;
 479                 };
 480
 481                 duart3: serial@21d0600 {
 482                         compatible = "fsl,ns16550", "ns16550a";
 483                         reg = <0x0 0x21d0600 0x0 0x100>;
 484                         interrupts = <0 55 0x4>;
 485                         clocks = <&clockgen 4 0>;
 486                 };
 487
 488                 gpio1: gpio@2300000 {
 489                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 490                         reg = <0x0 0x2300000 0x0 0x10000>;
 491                         interrupts = <0 66 0x4>;
 492                         gpio-controller;
 493                         #gpio-cells = <2>;
 494                         interrupt-controller;
 495                         #interrupt-cells = <2>;
 496                 };
 497
 498                 gpio2: gpio@2310000 {
 499                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 500                         reg = <0x0 0x2310000 0x0 0x10000>;
 501                         interrupts = <0 67 0x4>;
 502                         gpio-controller;
 503                         #gpio-cells = <2>;
 504                         interrupt-controller;
 505                         #interrupt-cells = <2>;
 506                 };
 507
 508                 gpio3: gpio@2320000 {
 509                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 510                         reg = <0x0 0x2320000 0x0 0x10000>;
 511                         interrupts = <0 68 0x4>;
 512                         gpio-controller;
 513                         #gpio-cells = <2>;
 514                         interrupt-controller;
 515                         #interrupt-cells = <2>;
 516                 };
 517
 518                 gpio4: gpio@2330000 {
 519                         compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
 520                         reg = <0x0 0x2330000 0x0 0x10000>;
 521                         interrupts = <0 134 0x4>;
 522                         gpio-controller;
 523                         #gpio-cells = <2>;
 524                         interrupt-controller;
 525                         #interrupt-cells = <2>;
 526                 };
 527
 528                 lpuart0: serial@2950000 {
 529                         compatible = "fsl,ls1021a-lpuart";
 530                         reg = <0x0 0x2950000 0x0 0x1000>;
 531                         interrupts = <0 48 0x4>;
 532                         clocks = <&clockgen 0 0>;
 533                         clock-names = "ipg";
 534                         status = "disabled";
 535                 };
 536
 537                 lpuart1: serial@2960000 {
 538                         compatible = "fsl,ls1021a-lpuart";
 539                         reg = <0x0 0x2960000 0x0 0x1000>;
 540                         interrupts = <0 49 0x4>;
 541                         clocks = <&clockgen 4 0>;
 542                         clock-names = "ipg";
 543                         status = "disabled";
 544                 };
 545
 546                 lpuart2: serial@2970000 {
 547                         compatible = "fsl,ls1021a-lpuart";
 548                         reg = <0x0 0x2970000 0x0 0x1000>;
 549                         interrupts = <0 50 0x4>;
 550                         clocks = <&clockgen 4 0>;
 551                         clock-names = "ipg";
 552                         status = "disabled";
 553                 };
 554
 555                 lpuart3: serial@2980000 {
 556                         compatible = "fsl,ls1021a-lpuart";
 557                         reg = <0x0 0x2980000 0x0 0x1000>;
 558                         interrupts = <0 51 0x4>;
 559                         clocks = <&clockgen 4 0>;
 560                         clock-names = "ipg";
 561                         status = "disabled";
 562                 };
 563
 564                 lpuart4: serial@2990000 {
 565                         compatible = "fsl,ls1021a-lpuart";
 566                         reg = <0x0 0x2990000 0x0 0x1000>;
 567                         interrupts = <0 52 0x4>;
 568                         clocks = <&clockgen 4 0>;
 569                         clock-names = "ipg";
 570                         status = "disabled";
 571                 };
 572
 573                 lpuart5: serial@29a0000 {
 574                         compatible = "fsl,ls1021a-lpuart";
 575                         reg = <0x0 0x29a0000 0x0 0x1000>;
 576                         interrupts = <0 53 0x4>;
 577                         clocks = <&clockgen 4 0>;
 578                         clock-names = "ipg";
 579                         status = "disabled";
 580                 };
 581
 582                 wdog0: wdog@2ad0000 {
 583                         compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
 584                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 585                         interrupts = <0 83 0x4>;
 586                         clocks = <&clockgen 4 0>;
 587                         clock-names = "wdog";
 588                         big-endian;
 589                 };
 590
 591                 edma0: edma@2c00000 {
 592                         #dma-cells = <2>;
 593                         compatible = "fsl,vf610-edma";
 594                         reg = <0x0 0x2c00000 0x0 0x10000>,
 595                               <0x0 0x2c10000 0x0 0x10000>,
 596                               <0x0 0x2c20000 0x0 0x10000>;
 597                         interrupts = <0 103 0x4>,
 598                                      <0 103 0x4>;
 599                         interrupt-names = "edma-tx", "edma-err";
 600                         dma-channels = <32>;
 601                         big-endian;
 602                         clock-names = "dmamux0", "dmamux1";
 603                         clocks = <&clockgen 4 0>,
 604                                  <&clockgen 4 0>;
 605                 };
 606
 607                 usb0: usb3@2f00000 {
 608                         compatible = "snps,dwc3";
 609                         reg = <0x0 0x2f00000 0x0 0x10000>;
 610                         interrupts = <0 60 0x4>;
 611                         dr_mode = "host";
 612                         snps,quirk-frame-length-adjustment = <0x20>;
 613                         snps,dis_rxdet_inp3_quirk;
 614                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 615                 };
 616
 617                 usb1: usb3@3000000 {
 618                         compatible = "snps,dwc3";
 619                         reg = <0x0 0x3000000 0x0 0x10000>;
 620                         interrupts = <0 61 0x4>;
 621                         dr_mode = "host";
 622                         snps,quirk-frame-length-adjustment = <0x20>;
 623                         snps,dis_rxdet_inp3_quirk;
 624                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 625                 };
 626
 627                 usb2: usb3@3100000 {
 628                         compatible = "snps,dwc3";
 629                         reg = <0x0 0x3100000 0x0 0x10000>;
 630                         interrupts = <0 63 0x4>;
 631                         dr_mode = "host";
 632                         snps,quirk-frame-length-adjustment = <0x20>;
 633                         snps,dis_rxdet_inp3_quirk;
 634                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 635                 };
 636
 637                 sata: sata@3200000 {
 638                         compatible = "fsl,ls1043a-ahci";
 639                         reg = <0x0 0x3200000 0x0 0x10000>,
 640                                 <0x0 0x20140520 0x0 0x4>;
 641                         reg-names = "ahci", "sata-ecc";
 642                         interrupts = <0 69 0x4>;
 643                         clocks = <&clockgen 4 0>;
 644                         dma-coherent;
 645                 };
 646
 647                 msi1: msi-controller1@1571000 {
 648                         compatible = "fsl,ls1043a-msi";
 649                         reg = <0x0 0x1571000 0x0 0x8>;
 650                         msi-controller;
 651                         interrupts = <0 116 0x4>;
 652                 };
 653
 654                 msi2: msi-controller2@1572000 {
 655                         compatible = "fsl,ls1043a-msi";
 656                         reg = <0x0 0x1572000 0x0 0x8>;
 657                         msi-controller;
 658                         interrupts = <0 126 0x4>;
 659                 };
 660
 661                 msi3: msi-controller3@1573000 {
 662                         compatible = "fsl,ls1043a-msi";
 663                         reg = <0x0 0x1573000 0x0 0x8>;
 664                         msi-controller;
 665                         interrupts = <0 160 0x4>;
 666                 };
 667
 668                 pcie@3400000 {
 669                         compatible = "fsl,ls1043a-pcie";
 670                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 671                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 672                         reg-names = "regs", "config";
 673                         interrupts = <0 118 0x4>, /* controller interrupt */
 674                                      <0 117 0x4>; /* PME interrupt */
 675                         interrupt-names = "intr", "pme";
 676                         #address-cells = <3>;
 677                         #size-cells = <2>;
 678                         device_type = "pci";
 679                         dma-coherent;
 680                         num-lanes = <4>;
 681                         num-viewport = <6>;
 682                         bus-range = <0x0 0xff>;
 683                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 684                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 685                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 686                         #interrupt-cells = <1>;
 687                         interrupt-map-mask = <0 0 0 7>;
 688                         interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
 689                                         <0000 0 0 2 &gic 0 111 0x4>,
 690                                         <0000 0 0 3 &gic 0 112 0x4>,
 691                                         <0000 0 0 4 &gic 0 113 0x4>;
 692                         status = "disabled";
 693                 };
 694
 695                 pcie@3500000 {
 696                         compatible = "fsl,ls1043a-pcie";
 697                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 698                                0x48 0x00000000 0x0 0x00002000>; /* configuration space */
 699                         reg-names = "regs", "config";
 700                         interrupts = <0 128 0x4>,
 701                                      <0 127 0x4>;
 702                         interrupt-names = "intr", "pme";
 703                         #address-cells = <3>;
 704                         #size-cells = <2>;
 705                         device_type = "pci";
 706                         dma-coherent;
 707                         num-lanes = <2>;
 708                         num-viewport = <6>;
 709                         bus-range = <0x0 0xff>;
 710                         ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
 711                                   0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 712                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 713                         #interrupt-cells = <1>;
 714                         interrupt-map-mask = <0 0 0 7>;
 715                         interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
 716                                         <0000 0 0 2 &gic 0 121 0x4>,
 717                                         <0000 0 0 3 &gic 0 122 0x4>,
 718                                         <0000 0 0 4 &gic 0 123 0x4>;
 719                         status = "disabled";
 720                 };
 721
 722                 pcie@3600000 {
 723                         compatible = "fsl,ls1043a-pcie";
 724                         reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
 725                                0x50 0x00000000 0x0 0x00002000>; /* configuration space */
 726                         reg-names = "regs", "config";
 727                         interrupts = <0 162 0x4>,
 728                                      <0 161 0x4>;
 729                         interrupt-names = "intr", "pme";
 730                         #address-cells = <3>;
 731                         #size-cells = <2>;
 732                         device_type = "pci";
 733                         dma-coherent;
 734                         num-lanes = <2>;
 735                         num-viewport = <6>;
 736                         bus-range = <0x0 0xff>;
 737                         ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
 738                                   0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 739                         msi-parent = <&msi1>, <&msi2>, <&msi3>;
 740                         #interrupt-cells = <1>;
 741                         interrupt-map-mask = <0 0 0 7>;
 742                         interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
 743                                         <0000 0 0 2 &gic 0 155 0x4>,
 744                                         <0000 0 0 3 &gic 0 156 0x4>,
 745                                         <0000 0 0 4 &gic 0 157 0x4>;
 746                         status = "disabled";
 747                 };
 748
 749                 qdma: dma-controller@8380000 {
 750                         compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
 751                         reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
 752                               <0x0 0x8390000 0x0 0x10000>, /* Status regs */
 753                               <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
 754                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 759                         interrupt-names = "qdma-error", "qdma-queue0",
 760                                 "qdma-queue1", "qdma-queue2", "qdma-queue3";
 761                         dma-channels = <8>;
 762                         block-number = <1>;
 763                         block-offset = <0x10000>;
 764                         fsl,dma-queues = <2>;
 765                         status-sizes = <64>;
 766                         queue-sizes = <64 64>;
 767                         big-endian;
 768                 };
 769
 770         };
 771
 772         firmware {
 773                 optee {
 774                         compatible = "linaro,optee-tz";
 775                         method = "smc";
 776                 };
 777         };
 778
 779 };
 780
 781 #include "qoriq-qman-portals.dtsi"
 782 #include "qoriq-bman-portals.dtsi"