arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1028A family SoC.
   4  *
   5  * Copyright 2018 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "fsl,ls1028a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a72";
  27                         reg = <0x0>;
  28                         enable-method = "psci";
  29                         clocks = <&clockgen 1 0>;
  30                         next-level-cache = <&l2>;
  31                         cpu-idle-states = <&CPU_PH20>;
  32                 };
  33
  34                 cpu1: cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a72";
  37                         reg = <0x1>;
  38                         enable-method = "psci";
  39                         clocks = <&clockgen 1 0>;
  40                         next-level-cache = <&l2>;
  41                         cpu-idle-states = <&CPU_PH20>;
  42                 };
  43
  44                 l2: l2-cache {
  45                         compatible = "cache";
  46                 };
  47         };
  48
  49         idle-states {
  50                 /*
  51                  * PSCI node is not added default, U-boot will add missing
  52                  * parts if it determines to use PSCI.
  53                  */
  54                 entry-method = "arm,psci";
  55
  56                 CPU_PH20: cpu-ph20 {
  57                         compatible = "arm,idle-state";
  58                         idle-state-name = "PH20";
  59                         arm,psci-suspend-param = <0x00010000>;
  60                         entry-latency-us = <1000>;
  61                         exit-latency-us = <1000>;
  62                         min-residency-us = <3000>;
  63                 };
  64         };
  65
  66         sysclk: clock-sysclk {
  67                 compatible = "fixed-clock";
  68                 #clock-cells = <0>;
  69                 clock-frequency = <100000000>;
  70                 clock-output-names = "sysclk";
  71         };
  72
  73         reboot {
  74                 compatible ="syscon-reboot";
  75                 regmap = <&dcfg>;
  76                 offset = <0xb0>;
  77                 mask = <0x02>;
  78         };
  79
  80         timer {
  81                 compatible = "arm,armv8-timer";
  82                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  83                                           IRQ_TYPE_LEVEL_LOW)>,
  84                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  85                                           IRQ_TYPE_LEVEL_LOW)>,
  86                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  87                                           IRQ_TYPE_LEVEL_LOW)>,
  88                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  89                                           IRQ_TYPE_LEVEL_LOW)>;
  90         };
  91
  92         gic: interrupt-controller@6000000 {
  93                 compatible= "arm,gic-v3";
  94                 #address-cells = <2>;
  95                 #size-cells = <2>;
  96                 ranges;
  97                 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  98                         <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
  99                 #interrupt-cells= <3>;
 100                 interrupt-controller;
 101                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 102                                          IRQ_TYPE_LEVEL_LOW)>;
 103                 its: gic-its@6020000 {
 104                         compatible = "arm,gic-v3-its";
 105                         msi-controller;
 106                         reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
 107                 };
 108         };
 109
 110         soc: soc {
 111                 compatible = "simple-bus";
 112                 #address-cells = <2>;
 113                 #size-cells = <2>;
 114                 ranges;
 115
 116                 ddr: memory-controller@1080000 {
 117                         compatible = "fsl,qoriq-memory-controller";
 118                         reg = <0x0 0x1080000 0x0 0x1000>;
 119                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 120                         big-endian;
 121                 };
 122
 123                 dcfg: syscon@1e00000 {
 124                         compatible = "fsl,ls1028a-dcfg", "syscon";
 125                         reg = <0x0 0x1e00000 0x0 0x10000>;
 126                         big-endian;
 127                 };
 128
 129                 scfg: syscon@1fc0000 {
 130                         compatible = "fsl,ls1028a-scfg", "syscon";
 131                         reg = <0x0 0x1fc0000 0x0 0x10000>;
 132                         big-endian;
 133                 };
 134
 135                 clockgen: clock-controller@1300000 {
 136                         compatible = "fsl,ls1028a-clockgen";
 137                         reg = <0x0 0x1300000 0x0 0xa0000>;
 138                         #clock-cells = <2>;
 139                         clocks = <&sysclk>;
 140                 };
 141
 142                 i2c0: i2c@2000000 {
 143                         compatible = "fsl,vf610-i2c";
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         reg = <0x0 0x2000000 0x0 0x10000>;
 147                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 148                         clocks = <&clockgen 4 1>;
 149                         status = "disabled";
 150                 };
 151
 152                 i2c1: i2c@2010000 {
 153                         compatible = "fsl,vf610-i2c";
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         reg = <0x0 0x2010000 0x0 0x10000>;
 157                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 158                         clocks = <&clockgen 4 1>;
 159                         status = "disabled";
 160                 };
 161
 162                 i2c2: i2c@2020000 {
 163                         compatible = "fsl,vf610-i2c";
 164                         #address-cells = <1>;
 165                         #size-cells = <0>;
 166                         reg = <0x0 0x2020000 0x0 0x10000>;
 167                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&clockgen 4 1>;
 169                         status = "disabled";
 170                 };
 171
 172                 i2c3: i2c@2030000 {
 173                         compatible = "fsl,vf610-i2c";
 174                         #address-cells = <1>;
 175                         #size-cells = <0>;
 176                         reg = <0x0 0x2030000 0x0 0x10000>;
 177                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 178                         clocks = <&clockgen 4 1>;
 179                         status = "disabled";
 180                 };
 181
 182                 i2c4: i2c@2040000 {
 183                         compatible = "fsl,vf610-i2c";
 184                         #address-cells = <1>;
 185                         #size-cells = <0>;
 186                         reg = <0x0 0x2040000 0x0 0x10000>;
 187                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 188                         clocks = <&clockgen 4 1>;
 189                         status = "disabled";
 190                 };
 191
 192                 i2c5: i2c@2050000 {
 193                         compatible = "fsl,vf610-i2c";
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         reg = <0x0 0x2050000 0x0 0x10000>;
 197                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&clockgen 4 1>;
 199                         status = "disabled";
 200                 };
 201
 202                 i2c6: i2c@2060000 {
 203                         compatible = "fsl,vf610-i2c";
 204                         #address-cells = <1>;
 205                         #size-cells = <0>;
 206                         reg = <0x0 0x2060000 0x0 0x10000>;
 207                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 208                         clocks = <&clockgen 4 1>;
 209                         status = "disabled";
 210                 };
 211
 212                 i2c7: i2c@2070000 {
 213                         compatible = "fsl,vf610-i2c";
 214                         #address-cells = <1>;
 215                         #size-cells = <0>;
 216                         reg = <0x0 0x2070000 0x0 0x10000>;
 217                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 218                         clocks = <&clockgen 4 1>;
 219                         status = "disabled";
 220                 };
 221
 222                 duart0: serial@21c0500 {
 223                         compatible = "fsl,ns16550", "ns16550a";
 224                         reg = <0x00 0x21c0500 0x0 0x100>;
 225                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 226                         clocks = <&clockgen 4 1>;
 227                         status = "disabled";
 228                 };
 229
 230                 duart1: serial@21c0600 {
 231                         compatible = "fsl,ns16550", "ns16550a";
 232                         reg = <0x00 0x21c0600 0x0 0x100>;
 233                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 234                         clocks = <&clockgen 4 1>;
 235                         status = "disabled";
 236                 };
 237
 238                 gpio1: gpio@2300000 {
 239                         compatible = "fsl,qoriq-gpio";
 240                         reg = <0x0 0x2300000 0x0 0x10000>;
 241                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 242                         gpio-controller;
 243                         #gpio-cells = <2>;
 244                         interrupt-controller;
 245                         #interrupt-cells = <2>;
 246                 };
 247
 248                 gpio2: gpio@2310000 {
 249                         compatible = "fsl,qoriq-gpio";
 250                         reg = <0x0 0x2310000 0x0 0x10000>;
 251                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 252                         gpio-controller;
 253                         #gpio-cells = <2>;
 254                         interrupt-controller;
 255                         #interrupt-cells = <2>;
 256                 };
 257
 258                 gpio3: gpio@2320000 {
 259                         compatible = "fsl,qoriq-gpio";
 260                         reg = <0x0 0x2320000 0x0 0x10000>;
 261                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 262                         gpio-controller;
 263                         #gpio-cells = <2>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <2>;
 266                 };
 267
 268                 wdog0: watchdog@23c0000 {
 269                         compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt";
 270                         reg = <0x0 0x23c0000 0x0 0x10000>;
 271                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&clockgen 4 1>;
 273                         big-endian;
 274                         status = "disabled";
 275                 };
 276
 277                 sata: sata@3200000 {
 278                         compatible = "fsl,ls1028a-ahci";
 279                         reg = <0x0 0x3200000 0x0 0x10000>,
 280                                 <0x0 0x20140520 0x0 0x4>;
 281                         reg-names = "ahci", "sata-ecc";
 282                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&clockgen 4 1>;
 284                         status = "disabled";
 285                 };
 286
 287                 smmu: iommu@5000000 {
 288                         compatible = "arm,mmu-500";
 289                         reg = <0 0x5000000 0 0x800000>;
 290                         #global-interrupts = <8>;
 291                         #iommu-cells = <1>;
 292                         stream-match-mask = <0x7c00>;
 293                         /* global secure fault */
 294                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 295                         /* combined secure interrupt */
 296                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 297                         /* global non-secure fault */
 298                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 299                         /* combined non-secure interrupt */
 300                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 301                         /* performance counter interrupts 0-7 */
 302                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 303                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 304                         /* per context interrupt, 64 interrupts */
 305                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 306                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 307                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 308                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 309                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 310                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 312                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 313                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 314                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 315                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 316                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 317                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 318                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 319                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 320                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 321                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 322                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 324                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 325                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 326                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 327                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 328                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 329                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 330                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 331                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 332                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 333                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 334                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 335                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 337                 };
 338
 339                 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
 340                         compatible = "pci-host-ecam-generic";
 341                         reg = <0x01 0xf0000000 0x0 0x100000>;
 342                         #address-cells = <3>;
 343                         #size-cells = <2>;
 344                         #interrupt-cells = <1>;
 345                         msi-parent = <&its>;
 346                         device_type = "pci";
 347                         bus-range = <0x0 0x0>;
 348                         dma-coherent;
 349                         msi-map = <0 &its 0x17 0xe>;
 350                         iommu-map = <0 &smmu 0x17 0xe>;
 351                                   /* PF0-6 BAR0 - non-prefetchable memory */
 352                         ranges = <0x82000000 0x0 0x00000000  0x1 0xf8000000  0x0 0x160000
 353                                   /* PF0-6 BAR2 - prefetchable memory */
 354                                   0xc2000000 0x0 0x00000000  0x1 0xf8160000  0x0 0x070000
 355                                   /* PF0: VF0-1 BAR0 - non-prefetchable memory */
 356                                   0x82000000 0x0 0x00000000  0x1 0xf81d0000  0x0 0x020000
 357                                   /* PF0: VF0-1 BAR2 - prefetchable memory */
 358                                   0xc2000000 0x0 0x00000000  0x1 0xf81f0000  0x0 0x020000
 359                                   /* PF1: VF0-1 BAR0 - non-prefetchable memory */
 360                                   0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
 361                                   /* PF1: VF0-1 BAR2 - prefetchable memory */
 362                                   0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;
 363
 364                         enetc_port0: ethernet@0,0 {
 365                                 compatible = "fsl,enetc";
 366                                 reg = <0x000000 0 0 0 0>;
 367                         };
 368                         enetc_port1: ethernet@0,1 {
 369                                 compatible = "fsl,enetc";
 370                                 reg = <0x000100 0 0 0 0>;
 371                         };
 372                 };
 373         };
 374 };