arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree file for NXP LS1028A RDB Board.
   4  *
   5  * Copyright 2018 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10
  11 /dts-v1/;
  12 #include "fsl-ls1028a.dtsi"
  13
  14 / {
  15         model = "LS1028A RDB Board";
  16         compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
  17
  18         aliases {
  19                 serial0 = &duart0;
  20                 serial1 = &duart1;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25         };
  26
  27         memory@80000000 {
  28                 device_type = "memory";
  29                 reg = <0x0 0x80000000 0x1 0x0000000>;
  30         };
  31 };
  32
  33 &i2c0 {
  34         status = "okay";
  35
  36         i2c-mux@77 {
  37                 compatible = "nxp,pca9847";
  38                 reg = <0x77>;
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41
  42                 i2c@2 {
  43                         #address-cells = <1>;
  44                         #size-cells = <0>;
  45                         reg = <0x02>;
  46
  47                         current-monitor@40 {
  48                                 compatible = "ti,ina220";
  49                                 reg = <0x40>;
  50                                 shunt-resistor = <500>;
  51                         };
  52                 };
  53
  54                 i2c@3 {
  55                         #address-cells = <1>;
  56                         #size-cells = <0>;
  57                         reg = <0x3>;
  58
  59                         rtc@51 {
  60                                 compatible = "nxp,pcf2129";
  61                                 reg = <0x51>;
  62                         };
  63                 };
  64         };
  65 };
  66
  67 &duart0 {
  68         status = "okay";
  69 };
  70
  71 &duart1 {
  72         status = "okay";
  73 };
  74
  75 &enetc_port0 {
  76         phy-handle = <&sgmii_phy0>;
  77         phy-connection-type = "sgmii";
  78
  79         mdio {
  80                 #address-cells = <1>;
  81                 #size-cells = <0>;
  82                 sgmii_phy0: ethernet-phy@2 {
  83                         reg = <0x2>;
  84                 };
  85         };
  86 };
  87
  88 &enetc_port1 {
  89         status = "disabled";
  90 };