arch/arm64/boot/dts/exynos/exynos5433.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos5433 SoC device tree source
   4  *
   5  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
   6  *
   7  * Samsung's Exynos5433 SoC device nodes are listed in this file.
   8  * Exynos5433 based board files can include this file and provide
   9  * values for board specific bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
  13  * additional nodes can be added to this file.
  14  */
  15
  16 #include <dt-bindings/clock/exynos5433.h>
  17 #include <dt-bindings/interrupt-controller/arm-gic.h>
  18
  19 / {
  20         compatible = "samsung,exynos5433";
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         interrupt-parent = <&gic>;
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29
  30                 cpu0: cpu@100 {
  31                         device_type = "cpu";
  32                         compatible = "arm,cortex-a53";
  33                         enable-method = "psci";
  34                         reg = <0x100>;
  35                         clock-frequency = <1300000000>;
  36                         clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
  37                         clock-names = "apolloclk";
  38                         operating-points-v2 = <&cluster_a53_opp_table>;
  39                         #cooling-cells = <2>;
  40                 };
  41
  42                 cpu1: cpu@101 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53";
  45                         enable-method = "psci";
  46                         reg = <0x101>;
  47                         clock-frequency = <1300000000>;
  48                         operating-points-v2 = <&cluster_a53_opp_table>;
  49                         #cooling-cells = <2>;
  50                 };
  51
  52                 cpu2: cpu@102 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a53";
  55                         enable-method = "psci";
  56                         reg = <0x102>;
  57                         clock-frequency = <1300000000>;
  58                         operating-points-v2 = <&cluster_a53_opp_table>;
  59                         #cooling-cells = <2>;
  60                 };
  61
  62                 cpu3: cpu@103 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53";
  65                         enable-method = "psci";
  66                         reg = <0x103>;
  67                         clock-frequency = <1300000000>;
  68                         operating-points-v2 = <&cluster_a53_opp_table>;
  69                         #cooling-cells = <2>;
  70                 };
  71
  72                 cpu4: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a57";
  75                         enable-method = "psci";
  76                         reg = <0x0>;
  77                         clock-frequency = <1900000000>;
  78                         clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
  79                         clock-names = "atlasclk";
  80                         operating-points-v2 = <&cluster_a57_opp_table>;
  81                         #cooling-cells = <2>;
  82                 };
  83
  84                 cpu5: cpu@1 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a57";
  87                         enable-method = "psci";
  88                         reg = <0x1>;
  89                         clock-frequency = <1900000000>;
  90                         operating-points-v2 = <&cluster_a57_opp_table>;
  91                         #cooling-cells = <2>;
  92                 };
  93
  94                 cpu6: cpu@2 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a57";
  97                         enable-method = "psci";
  98                         reg = <0x2>;
  99                         clock-frequency = <1900000000>;
 100                         operating-points-v2 = <&cluster_a57_opp_table>;
 101                         #cooling-cells = <2>;
 102                 };
 103
 104                 cpu7: cpu@3 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a57";
 107                         enable-method = "psci";
 108                         reg = <0x3>;
 109                         clock-frequency = <1900000000>;
 110                         operating-points-v2 = <&cluster_a57_opp_table>;
 111                         #cooling-cells = <2>;
 112                 };
 113         };
 114
 115         cluster_a53_opp_table: opp_table0 {
 116                 compatible = "operating-points-v2";
 117                 opp-shared;
 118
 119                 opp-400000000 {
 120                         opp-hz = /bits/ 64 <400000000>;
 121                         opp-microvolt = <900000>;
 122                 };
 123                 opp-500000000 {
 124                         opp-hz = /bits/ 64 <500000000>;
 125                         opp-microvolt = <925000>;
 126                 };
 127                 opp-600000000 {
 128                         opp-hz = /bits/ 64 <600000000>;
 129                         opp-microvolt = <950000>;
 130                 };
 131                 opp-700000000 {
 132                         opp-hz = /bits/ 64 <700000000>;
 133                         opp-microvolt = <975000>;
 134                 };
 135                 opp-800000000 {
 136                         opp-hz = /bits/ 64 <800000000>;
 137                         opp-microvolt = <1000000>;
 138                 };
 139                 opp-900000000 {
 140                         opp-hz = /bits/ 64 <900000000>;
 141                         opp-microvolt = <1050000>;
 142                 };
 143                 opp-1000000000 {
 144                         opp-hz = /bits/ 64 <1000000000>;
 145                         opp-microvolt = <1075000>;
 146                 };
 147                 opp-1100000000 {
 148                         opp-hz = /bits/ 64 <1100000000>;
 149                         opp-microvolt = <1112500>;
 150                 };
 151                 opp-1200000000 {
 152                         opp-hz = /bits/ 64 <1200000000>;
 153                         opp-microvolt = <1112500>;
 154                 };
 155                 opp-1300000000 {
 156                         opp-hz = /bits/ 64 <1300000000>;
 157                         opp-microvolt = <1150000>;
 158                 };
 159         };
 160
 161         cluster_a57_opp_table: opp_table1 {
 162                 compatible = "operating-points-v2";
 163                 opp-shared;
 164
 165                 opp-500000000 {
 166                         opp-hz = /bits/ 64 <500000000>;
 167                         opp-microvolt = <900000>;
 168                 };
 169                 opp-600000000 {
 170                         opp-hz = /bits/ 64 <600000000>;
 171                         opp-microvolt = <900000>;
 172                 };
 173                 opp-700000000 {
 174                         opp-hz = /bits/ 64 <700000000>;
 175                         opp-microvolt = <912500>;
 176                 };
 177                 opp-800000000 {
 178                         opp-hz = /bits/ 64 <800000000>;
 179                         opp-microvolt = <912500>;
 180                 };
 181                 opp-900000000 {
 182                         opp-hz = /bits/ 64 <900000000>;
 183                         opp-microvolt = <937500>;
 184                 };
 185                 opp-1000000000 {
 186                         opp-hz = /bits/ 64 <1000000000>;
 187                         opp-microvolt = <975000>;
 188                 };
 189                 opp-1100000000 {
 190                         opp-hz = /bits/ 64 <1100000000>;
 191                         opp-microvolt = <1012500>;
 192                 };
 193                 opp-1200000000 {
 194                         opp-hz = /bits/ 64 <1200000000>;
 195                         opp-microvolt = <1037500>;
 196                 };
 197                 opp-1300000000 {
 198                         opp-hz = /bits/ 64 <1300000000>;
 199                         opp-microvolt = <1062500>;
 200                 };
 201                 opp-1400000000 {
 202                         opp-hz = /bits/ 64 <1400000000>;
 203                         opp-microvolt = <1087500>;
 204                 };
 205                 opp-1500000000 {
 206                         opp-hz = /bits/ 64 <1500000000>;
 207                         opp-microvolt = <1125000>;
 208                 };
 209                 opp-1600000000 {
 210                         opp-hz = /bits/ 64 <1600000000>;
 211                         opp-microvolt = <1137500>;
 212                 };
 213                 opp-1700000000 {
 214                         opp-hz = /bits/ 64 <1700000000>;
 215                         opp-microvolt = <1175000>;
 216                 };
 217                 opp-1800000000 {
 218                         opp-hz = /bits/ 64 <1800000000>;
 219                         opp-microvolt = <1212500>;
 220                 };
 221                 opp-1900000000 {
 222                         opp-hz = /bits/ 64 <1900000000>;
 223                         opp-microvolt = <1262500>;
 224                 };
 225         };
 226
 227         psci {
 228                 compatible = "arm,psci";
 229                 method = "smc";
 230                 cpu_off = <0x84000002>;
 231                 cpu_on = <0xC4000003>;
 232         };
 233
 234         soc: soc {
 235                 compatible = "simple-bus";
 236                 #address-cells = <1>;
 237                 #size-cells = <1>;
 238                 ranges;
 239
 240                 arm_a53_pmu {
 241                         compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
 242                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 246                         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 247                 };
 248
 249                 arm_a57_pmu {
 250                         compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
 251                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 252                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 253                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 255                         interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 256                 };
 257
 258                 chipid@10000000 {
 259                         compatible = "samsung,exynos4210-chipid";
 260                         reg = <0x10000000 0x100>;
 261                 };
 262
 263                 xxti: xxti {
 264                         compatible = "fixed-clock";
 265                         clock-output-names = "oscclk";
 266                         #clock-cells = <0>;
 267                 };
 268
 269                 cmu_top: clock-controller@10030000 {
 270                         compatible = "samsung,exynos5433-cmu-top";
 271                         reg = <0x10030000 0x1000>;
 272                         #clock-cells = <1>;
 273
 274                         clock-names = "oscclk",
 275                                 "sclk_mphy_pll",
 276                                 "sclk_mfc_pll",
 277                                 "sclk_bus_pll";
 278                         clocks = <&xxti>,
 279                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
 280                                 <&cmu_mif CLK_SCLK_MFC_PLL>,
 281                                 <&cmu_mif CLK_SCLK_BUS_PLL>;
 282                 };
 283
 284                 cmu_cpif: clock-controller@10fc0000 {
 285                         compatible = "samsung,exynos5433-cmu-cpif";
 286                         reg = <0x10fc0000 0x1000>;
 287                         #clock-cells = <1>;
 288
 289                         clock-names = "oscclk";
 290                         clocks = <&xxti>;
 291                 };
 292
 293                 cmu_mif: clock-controller@105b0000 {
 294                         compatible = "samsung,exynos5433-cmu-mif";
 295                         reg = <0x105b0000 0x2000>;
 296                         #clock-cells = <1>;
 297
 298                         clock-names = "oscclk",
 299                                 "sclk_mphy_pll";
 300                         clocks = <&xxti>,
 301                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
 302                 };
 303
 304                 cmu_peric: clock-controller@14c80000 {
 305                         compatible = "samsung,exynos5433-cmu-peric";
 306                         reg = <0x14c80000 0x1000>;
 307                         #clock-cells = <1>;
 308                 };
 309
 310                 cmu_peris: clock-controller@10040000 {
 311                         compatible = "samsung,exynos5433-cmu-peris";
 312                         reg = <0x10040000 0x1000>;
 313                         #clock-cells = <1>;
 314                 };
 315
 316                 cmu_fsys: clock-controller@156e0000 {
 317                         compatible = "samsung,exynos5433-cmu-fsys";
 318                         reg = <0x156e0000 0x1000>;
 319                         #clock-cells = <1>;
 320
 321                         clock-names = "oscclk",
 322                                 "sclk_ufs_mphy",
 323                                 "aclk_fsys_200",
 324                                 "sclk_pcie_100_fsys",
 325                                 "sclk_ufsunipro_fsys",
 326                                 "sclk_mmc2_fsys",
 327                                 "sclk_mmc1_fsys",
 328                                 "sclk_mmc0_fsys",
 329                                 "sclk_usbhost30_fsys",
 330                                 "sclk_usbdrd30_fsys";
 331                         clocks = <&xxti>,
 332                                 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
 333                                 <&cmu_top CLK_ACLK_FSYS_200>,
 334                                 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 335                                 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 336                                 <&cmu_top CLK_SCLK_MMC2_FSYS>,
 337                                 <&cmu_top CLK_SCLK_MMC1_FSYS>,
 338                                 <&cmu_top CLK_SCLK_MMC0_FSYS>,
 339                                 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 340                                 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 341                 };
 342
 343                 cmu_g2d: clock-controller@12460000 {
 344                         compatible = "samsung,exynos5433-cmu-g2d";
 345                         reg = <0x12460000 0x1000>;
 346                         #clock-cells = <1>;
 347
 348                         clock-names = "oscclk",
 349                                 "aclk_g2d_266",
 350                                 "aclk_g2d_400";
 351                         clocks = <&xxti>,
 352                                 <&cmu_top CLK_ACLK_G2D_266>,
 353                                 <&cmu_top CLK_ACLK_G2D_400>;
 354                         power-domains = <&pd_g2d>;
 355                 };
 356
 357                 cmu_disp: clock-controller@13b90000 {
 358                         compatible = "samsung,exynos5433-cmu-disp";
 359                         reg = <0x13b90000 0x1000>;
 360                         #clock-cells = <1>;
 361
 362                         clock-names = "oscclk",
 363                                 "sclk_dsim1_disp",
 364                                 "sclk_dsim0_disp",
 365                                 "sclk_dsd_disp",
 366                                 "sclk_decon_tv_eclk_disp",
 367                                 "sclk_decon_vclk_disp",
 368                                 "sclk_decon_eclk_disp",
 369                                 "sclk_decon_tv_vclk_disp",
 370                                 "aclk_disp_333";
 371                         clocks = <&xxti>,
 372                                 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
 373                                 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
 374                                 <&cmu_mif CLK_SCLK_DSD_DISP>,
 375                                 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 376                                 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 377                                 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 378                                 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 379                                 <&cmu_mif CLK_ACLK_DISP_333>;
 380                         power-domains = <&pd_disp>;
 381                 };
 382
 383                 cmu_aud: clock-controller@114c0000 {
 384                         compatible = "samsung,exynos5433-cmu-aud";
 385                         reg = <0x114c0000 0x1000>;
 386                         #clock-cells = <1>;
 387                         clock-names = "oscclk", "fout_aud_pll";
 388                         clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
 389                         power-domains = <&pd_aud>;
 390                 };
 391
 392                 cmu_bus0: clock-controller@13600000 {
 393                         compatible = "samsung,exynos5433-cmu-bus0";
 394                         reg = <0x13600000 0x1000>;
 395                         #clock-cells = <1>;
 396
 397                         clock-names = "aclk_bus0_400";
 398                         clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 399                 };
 400
 401                 cmu_bus1: clock-controller@14800000 {
 402                         compatible = "samsung,exynos5433-cmu-bus1";
 403                         reg = <0x14800000 0x1000>;
 404                         #clock-cells = <1>;
 405
 406                         clock-names = "aclk_bus1_400";
 407                         clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 408                 };
 409
 410                 cmu_bus2: clock-controller@13400000 {
 411                         compatible = "samsung,exynos5433-cmu-bus2";
 412                         reg = <0x13400000 0x1000>;
 413                         #clock-cells = <1>;
 414
 415                         clock-names = "oscclk", "aclk_bus2_400";
 416                         clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 417                 };
 418
 419                 cmu_g3d: clock-controller@14aa0000 {
 420                         compatible = "samsung,exynos5433-cmu-g3d";
 421                         reg = <0x14aa0000 0x2000>;
 422                         #clock-cells = <1>;
 423
 424                         clock-names = "oscclk", "aclk_g3d_400";
 425                         clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 426                         power-domains = <&pd_g3d>;
 427                 };
 428
 429                 cmu_gscl: clock-controller@13cf0000 {
 430                         compatible = "samsung,exynos5433-cmu-gscl";
 431                         reg = <0x13cf0000 0x1000>;
 432                         #clock-cells = <1>;
 433
 434                         clock-names = "oscclk",
 435                                 "aclk_gscl_111",
 436                                 "aclk_gscl_333";
 437                         clocks = <&xxti>,
 438                                 <&cmu_top CLK_ACLK_GSCL_111>,
 439                                 <&cmu_top CLK_ACLK_GSCL_333>;
 440                         power-domains = <&pd_gscl>;
 441                 };
 442
 443                 cmu_apollo: clock-controller@11900000 {
 444                         compatible = "samsung,exynos5433-cmu-apollo";
 445                         reg = <0x11900000 0x2000>;
 446                         #clock-cells = <1>;
 447
 448                         clock-names = "oscclk", "sclk_bus_pll_apollo";
 449                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 450                 };
 451
 452                 cmu_atlas: clock-controller@11800000 {
 453                         compatible = "samsung,exynos5433-cmu-atlas";
 454                         reg = <0x11800000 0x2000>;
 455                         #clock-cells = <1>;
 456
 457                         clock-names = "oscclk", "sclk_bus_pll_atlas";
 458                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 459                 };
 460
 461                 cmu_mscl: clock-controller@150d0000 {
 462                         compatible = "samsung,exynos5433-cmu-mscl";
 463                         reg = <0x150d0000 0x1000>;
 464                         #clock-cells = <1>;
 465
 466                         clock-names = "oscclk",
 467                                 "sclk_jpeg_mscl",
 468                                 "aclk_mscl_400";
 469                         clocks = <&xxti>,
 470                                 <&cmu_top CLK_SCLK_JPEG_MSCL>,
 471                                 <&cmu_top CLK_ACLK_MSCL_400>;
 472                         power-domains = <&pd_mscl>;
 473                 };
 474
 475                 cmu_mfc: clock-controller@15280000 {
 476                         compatible = "samsung,exynos5433-cmu-mfc";
 477                         reg = <0x15280000 0x1000>;
 478                         #clock-cells = <1>;
 479
 480                         clock-names = "oscclk", "aclk_mfc_400";
 481                         clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 482                         power-domains = <&pd_mfc>;
 483                 };
 484
 485                 cmu_hevc: clock-controller@14f80000 {
 486                         compatible = "samsung,exynos5433-cmu-hevc";
 487                         reg = <0x14f80000 0x1000>;
 488                         #clock-cells = <1>;
 489
 490                         clock-names = "oscclk", "aclk_hevc_400";
 491                         clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 492                         power-domains = <&pd_hevc>;
 493                 };
 494
 495                 cmu_isp: clock-controller@146d0000 {
 496                         compatible = "samsung,exynos5433-cmu-isp";
 497                         reg = <0x146d0000 0x1000>;
 498                         #clock-cells = <1>;
 499
 500                         clock-names = "oscclk",
 501                                 "aclk_isp_dis_400",
 502                                 "aclk_isp_400";
 503                         clocks = <&xxti>,
 504                                 <&cmu_top CLK_ACLK_ISP_DIS_400>,
 505                                 <&cmu_top CLK_ACLK_ISP_400>;
 506                         power-domains = <&pd_isp>;
 507                 };
 508
 509                 cmu_cam0: clock-controller@120d0000 {
 510                         compatible = "samsung,exynos5433-cmu-cam0";
 511                         reg = <0x120d0000 0x1000>;
 512                         #clock-cells = <1>;
 513
 514                         clock-names = "oscclk",
 515                                 "aclk_cam0_333",
 516                                 "aclk_cam0_400",
 517                                 "aclk_cam0_552";
 518                         clocks = <&xxti>,
 519                                 <&cmu_top CLK_ACLK_CAM0_333>,
 520                                 <&cmu_top CLK_ACLK_CAM0_400>,
 521                                 <&cmu_top CLK_ACLK_CAM0_552>;
 522                         power-domains = <&pd_cam0>;
 523                 };
 524
 525                 cmu_cam1: clock-controller@145d0000 {
 526                         compatible = "samsung,exynos5433-cmu-cam1";
 527                         reg = <0x145d0000 0x1000>;
 528                         #clock-cells = <1>;
 529
 530                         clock-names = "oscclk",
 531                                 "sclk_isp_uart_cam1",
 532                                 "sclk_isp_spi1_cam1",
 533                                 "sclk_isp_spi0_cam1",
 534                                 "aclk_cam1_333",
 535                                 "aclk_cam1_400",
 536                                 "aclk_cam1_552";
 537                         clocks = <&xxti>,
 538                                 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
 539                                 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
 540                                 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
 541                                 <&cmu_top CLK_ACLK_CAM1_333>,
 542                                 <&cmu_top CLK_ACLK_CAM1_400>,
 543                                 <&cmu_top CLK_ACLK_CAM1_552>;
 544                         power-domains = <&pd_cam1>;
 545                 };
 546
 547                 cmu_imem: clock-controller@11060000 {
 548                         compatible = "samsung,exynos5433-cmu-imem";
 549                         reg = <0x11060000 0x1000>;
 550                         #clock-cells = <1>;
 551
 552                         clock-names = "oscclk",
 553                                 "aclk_imem_sssx_266",
 554                                 "aclk_imem_266",
 555                                 "aclk_imem_200";
 556                         clocks = <&xxti>,
 557                                 <&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
 558                                 <&cmu_top CLK_DIV_ACLK_IMEM_266>,
 559                                 <&cmu_top CLK_DIV_ACLK_IMEM_200>;
 560                 };
 561
 562                 pd_gscl: power-domain@105c4000 {
 563                         compatible = "samsung,exynos5433-pd";
 564                         reg = <0x105c4000 0x20>;
 565                         #power-domain-cells = <0>;
 566                         label = "GSCL";
 567                 };
 568
 569                 pd_cam0: power-domain@105c4020 {
 570                         compatible = "samsung,exynos5433-pd";
 571                         reg = <0x105c4020 0x20>;
 572                         #power-domain-cells = <0>;
 573                         power-domains = <&pd_cam1>;
 574                         label = "CAM0";
 575                 };
 576
 577                 pd_mscl: power-domain@105c4040 {
 578                         compatible = "samsung,exynos5433-pd";
 579                         reg = <0x105c4040 0x20>;
 580                         #power-domain-cells = <0>;
 581                         label = "MSCL";
 582                 };
 583
 584                 pd_g3d: power-domain@105c4060 {
 585                         compatible = "samsung,exynos5433-pd";
 586                         reg = <0x105c4060 0x20>;
 587                         #power-domain-cells = <0>;
 588                         label = "G3D";
 589                 };
 590
 591                 pd_disp: power-domain@105c4080 {
 592                         compatible = "samsung,exynos5433-pd";
 593                         reg = <0x105c4080 0x20>;
 594                         #power-domain-cells = <0>;
 595                         label = "DISP";
 596                 };
 597
 598                 pd_cam1: power-domain@105c40a0 {
 599                         compatible = "samsung,exynos5433-pd";
 600                         reg = <0x105c40a0 0x20>;
 601                         #power-domain-cells = <0>;
 602                         label = "CAM1";
 603                 };
 604
 605                 pd_aud: power-domain@105c40c0 {
 606                         compatible = "samsung,exynos5433-pd";
 607                         reg = <0x105c40c0 0x20>;
 608                         #power-domain-cells = <0>;
 609                         label = "AUD";
 610                 };
 611
 612                 pd_g2d: power-domain@105c4120 {
 613                         compatible = "samsung,exynos5433-pd";
 614                         reg = <0x105c4120 0x20>;
 615                         #power-domain-cells = <0>;
 616                         label = "G2D";
 617                 };
 618
 619                 pd_isp: power-domain@105c4140 {
 620                         compatible = "samsung,exynos5433-pd";
 621                         reg = <0x105c4140 0x20>;
 622                         #power-domain-cells = <0>;
 623                         power-domains = <&pd_cam0>;
 624                         label = "ISP";
 625                 };
 626
 627                 pd_mfc: power-domain@105c4180 {
 628                         compatible = "samsung,exynos5433-pd";
 629                         reg = <0x105c4180 0x20>;
 630                         #power-domain-cells = <0>;
 631                         label = "MFC";
 632                 };
 633
 634                 pd_hevc: power-domain@105c41c0 {
 635                         compatible = "samsung,exynos5433-pd";
 636                         reg = <0x105c41c0 0x20>;
 637                         #power-domain-cells = <0>;
 638                         label = "HEVC";
 639                 };
 640
 641                 tmu_atlas0: tmu@10060000 {
 642                         compatible = "samsung,exynos5433-tmu";
 643                         reg = <0x10060000 0x200>;
 644                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 646                                 <&cmu_peris CLK_SCLK_TMU0>;
 647                         clock-names = "tmu_apbif", "tmu_sclk";
 648                         #thermal-sensor-cells = <0>;
 649                         status = "disabled";
 650                 };
 651
 652                 tmu_atlas1: tmu@10068000 {
 653                         compatible = "samsung,exynos5433-tmu";
 654                         reg = <0x10068000 0x200>;
 655                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 656                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 657                                 <&cmu_peris CLK_SCLK_TMU0>;
 658                         clock-names = "tmu_apbif", "tmu_sclk";
 659                         #thermal-sensor-cells = <0>;
 660                         status = "disabled";
 661                 };
 662
 663                 tmu_g3d: tmu@10070000 {
 664                         compatible = "samsung,exynos5433-tmu";
 665                         reg = <0x10070000 0x200>;
 666                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 667                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 668                                 <&cmu_peris CLK_SCLK_TMU1>;
 669                         clock-names = "tmu_apbif", "tmu_sclk";
 670                         #thermal-sensor-cells = <0>;
 671                         status = "disabled";
 672                 };
 673
 674                 tmu_apollo: tmu@10078000 {
 675                         compatible = "samsung,exynos5433-tmu";
 676                         reg = <0x10078000 0x200>;
 677                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 678                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 679                                 <&cmu_peris CLK_SCLK_TMU1>;
 680                         clock-names = "tmu_apbif", "tmu_sclk";
 681                         #thermal-sensor-cells = <0>;
 682                         status = "disabled";
 683                 };
 684
 685                 tmu_isp: tmu@1007c000 {
 686                         compatible = "samsung,exynos5433-tmu";
 687                         reg = <0x1007c000 0x200>;
 688                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 689                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 690                                 <&cmu_peris CLK_SCLK_TMU1>;
 691                         clock-names = "tmu_apbif", "tmu_sclk";
 692                         #thermal-sensor-cells = <0>;
 693                         status = "disabled";
 694                 };
 695
 696                 mct@101c0000 {
 697                         compatible = "samsung,exynos4210-mct";
 698                         reg = <0x101c0000 0x800>;
 699                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 700                                 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 701                                 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 702                                 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 703                                 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 704                                 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 705                                 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 706                                 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 707                                 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 708                                 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 709                                 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 710                                 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
 712                         clock-names = "fin_pll", "mct";
 713                 };
 714
 715                 ppmu_d0_cpu: ppmu@10480000 {
 716                         compatible = "samsung,exynos-ppmu-v2";
 717                         reg = <0x10480000 0x2000>;
 718                         status = "disabled";
 719                 };
 720
 721                 ppmu_d0_general: ppmu@10490000 {
 722                         compatible = "samsung,exynos-ppmu-v2";
 723                         reg = <0x10490000 0x2000>;
 724                         status = "disabled";
 725                 };
 726
 727                 ppmu_d1_cpu: ppmu@104b0000 {
 728                         compatible = "samsung,exynos-ppmu-v2";
 729                         reg = <0x104b0000 0x2000>;
 730                         status = "disabled";
 731                 };
 732
 733                 ppmu_d1_general: ppmu@104c0000 {
 734                         compatible = "samsung,exynos-ppmu-v2";
 735                         reg = <0x104c0000 0x2000>;
 736                         status = "disabled";
 737                 };
 738
 739                 pinctrl_alive: pinctrl@10580000 {
 740                         compatible = "samsung,exynos5433-pinctrl";
 741                         reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
 742
 743                         wakeup-interrupt-controller {
 744                                 compatible = "samsung,exynos7-wakeup-eint";
 745                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 746                         };
 747                 };
 748
 749                 pinctrl_aud: pinctrl@114b0000 {
 750                         compatible = "samsung,exynos5433-pinctrl";
 751                         reg = <0x114b0000 0x1000>;
 752                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 753                         power-domains = <&pd_aud>;
 754                 };
 755
 756                 pinctrl_cpif: pinctrl@10fe0000 {
 757                         compatible = "samsung,exynos5433-pinctrl";
 758                         reg = <0x10fe0000 0x1000>;
 759                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 760                 };
 761
 762                 pinctrl_ese: pinctrl@14ca0000 {
 763                         compatible = "samsung,exynos5433-pinctrl";
 764                         reg = <0x14ca0000 0x1000>;
 765                         interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 766                 };
 767
 768                 pinctrl_finger: pinctrl@14cb0000 {
 769                         compatible = "samsung,exynos5433-pinctrl";
 770                         reg = <0x14cb0000 0x1000>;
 771                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 772                 };
 773
 774                 pinctrl_fsys: pinctrl@15690000 {
 775                         compatible = "samsung,exynos5433-pinctrl";
 776                         reg = <0x15690000 0x1000>;
 777                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 778                 };
 779
 780                 pinctrl_imem: pinctrl@11090000 {
 781                         compatible = "samsung,exynos5433-pinctrl";
 782                         reg = <0x11090000 0x1000>;
 783                         interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
 784                 };
 785
 786                 pinctrl_nfc: pinctrl@14cd0000 {
 787                         compatible = "samsung,exynos5433-pinctrl";
 788                         reg = <0x14cd0000 0x1000>;
 789                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 790                 };
 791
 792                 pinctrl_peric: pinctrl@14cc0000 {
 793                         compatible = "samsung,exynos5433-pinctrl";
 794                         reg = <0x14cc0000 0x1100>;
 795                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 796                 };
 797
 798                 pinctrl_touch: pinctrl@14ce0000 {
 799                         compatible = "samsung,exynos5433-pinctrl";
 800                         reg = <0x14ce0000 0x1100>;
 801                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 802                 };
 803
 804                 pmu_system_controller: system-controller@105c0000 {
 805                         compatible = "samsung,exynos5433-pmu", "syscon";
 806                         reg = <0x105c0000 0x5008>;
 807                         #clock-cells = <1>;
 808                         clock-names = "clkout16";
 809                         clocks = <&xxti>;
 810
 811                         reboot: syscon-reboot {
 812                                 compatible = "syscon-reboot";
 813                                 regmap = <&pmu_system_controller>;
 814                                 offset = <0x400>; /* SWRESET */
 815                                 mask = <0x1>;
 816                         };
 817                 };
 818
 819                 gic: interrupt-controller@11001000 {
 820                         compatible = "arm,gic-400";
 821                         #interrupt-cells = <3>;
 822                         interrupt-controller;
 823                         reg = <0x11001000 0x1000>,
 824                                 <0x11002000 0x2000>,
 825                                 <0x11004000 0x2000>,
 826                                 <0x11006000 0x2000>;
 827                         interrupts = <GIC_PPI 9 0xf04>;
 828                 };
 829
 830                 mipi_phy: video-phy {
 831                         compatible = "samsung,exynos5433-mipi-video-phy";
 832                         #phy-cells = <1>;
 833                         samsung,pmu-syscon = <&pmu_system_controller>;
 834                         samsung,cam0-sysreg = <&syscon_cam0>;
 835                         samsung,cam1-sysreg = <&syscon_cam1>;
 836                         samsung,disp-sysreg = <&syscon_disp>;
 837                 };
 838
 839                 decon: decon@13800000 {
 840                         compatible = "samsung,exynos5433-decon";
 841                         reg = <0x13800000 0x2104>;
 842                         clocks = <&cmu_disp CLK_PCLK_DECON>,
 843                                 <&cmu_disp CLK_ACLK_DECON>,
 844                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 845                                 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
 846                                 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 847                                 <&cmu_disp CLK_ACLK_SMMU_DECON1X>,
 848                                 <&cmu_disp CLK_ACLK_XIU_DECON1X>,
 849                                 <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 850                                 <&cmu_disp CLK_SCLK_DECON_VCLK>,
 851                                 <&cmu_disp CLK_SCLK_DECON_ECLK>;
 852                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 853                                 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 854                                 "aclk_smmu_decon1x", "aclk_xiu_decon1x",
 855                                 "pclk_smmu_decon1x", "sclk_decon_vclk",
 856                                 "sclk_decon_eclk";
 857                         power-domains = <&pd_disp>;
 858                         interrupt-names = "fifo", "vsync", "lcd_sys";
 859                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 860                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 861                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 862                         samsung,disp-sysreg = <&syscon_disp>;
 863                         status = "disabled";
 864                         iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
 865                         iommu-names = "m0", "m1";
 866
 867                         ports {
 868                                 #address-cells = <1>;
 869                                 #size-cells = <0>;
 870
 871                                 port@0 {
 872                                         reg = <0>;
 873                                         decon_to_mic: endpoint {
 874                                                 remote-endpoint =
 875                                                         <&mic_to_decon>;
 876                                         };
 877                                 };
 878                         };
 879                 };
 880
 881                 decon_tv: decon@13880000 {
 882                         compatible = "samsung,exynos5433-decon-tv";
 883                         reg = <0x13880000 0x20b8>;
 884                         clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
 885                                  <&cmu_disp CLK_ACLK_DECON_TV>,
 886                                  <&cmu_disp CLK_ACLK_SMMU_TV0X>,
 887                                  <&cmu_disp CLK_ACLK_XIU_TV0X>,
 888                                  <&cmu_disp CLK_PCLK_SMMU_TV0X>,
 889                                  <&cmu_disp CLK_ACLK_SMMU_TV1X>,
 890                                  <&cmu_disp CLK_ACLK_XIU_TV1X>,
 891                                  <&cmu_disp CLK_PCLK_SMMU_TV1X>,
 892                                  <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
 893                                  <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
 894                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 895                                       "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 896                                       "aclk_smmu_decon1x", "aclk_xiu_decon1x",
 897                                       "pclk_smmu_decon1x", "sclk_decon_vclk",
 898                                       "sclk_decon_eclk";
 899                         samsung,disp-sysreg = <&syscon_disp>;
 900                         power-domains = <&pd_disp>;
 901                         interrupt-names = "fifo", "vsync", "lcd_sys";
 902                         interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 903                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 904                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
 905                         status = "disabled";
 906                         iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
 907                         iommu-names = "m0", "m1";
 908                 };
 909
 910                 dsi: dsi@13900000 {
 911                         compatible = "samsung,exynos5433-mipi-dsi";
 912                         reg = <0x13900000 0xC0>;
 913                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 914                         phys = <&mipi_phy 1>;
 915                         phy-names = "dsim";
 916                         clocks = <&cmu_disp CLK_PCLK_DSIM0>,
 917                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
 918                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
 919                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
 920                                 <&cmu_disp CLK_SCLK_DSIM0>;
 921                         clock-names = "bus_clk",
 922                                         "phyclk_mipidphy0_bitclkdiv8",
 923                                         "phyclk_mipidphy0_rxclkesc0",
 924                                         "sclk_rgb_vclk_to_dsim0",
 925                                         "sclk_mipi";
 926                         power-domains = <&pd_disp>;
 927                         status = "disabled";
 928                         #address-cells = <1>;
 929                         #size-cells = <0>;
 930
 931                         ports {
 932                                 #address-cells = <1>;
 933                                 #size-cells = <0>;
 934
 935                                 port@0 {
 936                                         reg = <0>;
 937                                         dsi_to_mic: endpoint {
 938                                                 remote-endpoint = <&mic_to_dsi>;
 939                                         };
 940                                 };
 941                         };
 942                 };
 943
 944                 mic: mic@13930000 {
 945                         compatible = "samsung,exynos5433-mic";
 946                         reg = <0x13930000 0x48>;
 947                         clocks = <&cmu_disp CLK_PCLK_MIC0>,
 948                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
 949                         clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
 950                         power-domains = <&pd_disp>;
 951                         samsung,disp-syscon = <&syscon_disp>;
 952                         status = "disabled";
 953
 954                         ports {
 955                                 #address-cells = <1>;
 956                                 #size-cells = <0>;
 957
 958                                 port@0 {
 959                                         reg = <0>;
 960                                         mic_to_decon: endpoint {
 961                                                 remote-endpoint =
 962                                                         <&decon_to_mic>;
 963                                         };
 964                                 };
 965
 966                                 port@1 {
 967                                         reg = <1>;
 968                                         mic_to_dsi: endpoint {
 969                                                 remote-endpoint = <&dsi_to_mic>;
 970                                         };
 971                                 };
 972                         };
 973                 };
 974
 975                 hdmi: hdmi@13970000 {
 976                         compatible = "samsung,exynos5433-hdmi";
 977                         reg = <0x13970000 0x70000>;
 978                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 979                         clocks = <&cmu_disp CLK_PCLK_HDMI>,
 980                                 <&cmu_disp CLK_PCLK_HDMIPHY>,
 981                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
 982                                 <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
 983                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
 984                                 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
 985                                 <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
 986                                 <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
 987                                 <&xxti>, <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
 988                         clock-names = "hdmi_pclk", "hdmi_i_pclk",
 989                                 "i_tmds_clk", "i_pixel_clk",
 990                                 "tmds_clko", "tmds_clko_user",
 991                                 "pixel_clko", "pixel_clko_user",
 992                                 "oscclk", "i_spdif_clk";
 993                         phy = <&hdmiphy>;
 994                         ddc = <&hsi2c_11>;
 995                         samsung,syscon-phandle = <&pmu_system_controller>;
 996                         samsung,sysreg-phandle = <&syscon_disp>;
 997                         #sound-dai-cells = <0>;
 998                         status = "disabled";
 999                 };
1000
1001                 hdmiphy: hdmiphy@13af0000 {
1002                         reg = <0x13af0000 0x80>;
1003                 };
1004
1005                 syscon_disp: syscon@13b80000 {
1006                         compatible = "syscon";
1007                         reg = <0x13b80000 0x1010>;
1008                 };
1009
1010                 syscon_cam0: syscon@120f0000 {
1011                         compatible = "syscon";
1012                         reg = <0x120f0000 0x1020>;
1013                 };
1014
1015                 syscon_cam1: syscon@145f0000 {
1016                         compatible = "syscon";
1017                         reg = <0x145f0000 0x1038>;
1018                 };
1019
1020                 gsc_0: video-scaler@13c00000 {
1021                         compatible = "samsung,exynos5433-gsc";
1022                         reg = <0x13c00000 0x1000>;
1023                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
1024                         clock-names = "pclk", "aclk", "aclk_xiu",
1025                                       "aclk_gsclbend";
1026                         clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
1027                                  <&cmu_gscl CLK_ACLK_GSCL0>,
1028                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1029                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1030                         iommus = <&sysmmu_gscl0>;
1031                         power-domains = <&pd_gscl>;
1032                 };
1033
1034                 gsc_1: video-scaler@13c10000 {
1035                         compatible = "samsung,exynos5433-gsc";
1036                         reg = <0x13c10000 0x1000>;
1037                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
1038                         clock-names = "pclk", "aclk", "aclk_xiu",
1039                                       "aclk_gsclbend";
1040                         clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
1041                                  <&cmu_gscl CLK_ACLK_GSCL1>,
1042                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1043                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1044                         iommus = <&sysmmu_gscl1>;
1045                         power-domains = <&pd_gscl>;
1046                 };
1047
1048                 gsc_2: video-scaler@13c20000 {
1049                         compatible = "samsung,exynos5433-gsc";
1050                         reg = <0x13c20000 0x1000>;
1051                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
1052                         clock-names = "pclk", "aclk", "aclk_xiu",
1053                                       "aclk_gsclbend";
1054                         clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
1055                                  <&cmu_gscl CLK_ACLK_GSCL2>,
1056                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
1057                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
1058                         iommus = <&sysmmu_gscl2>;
1059                         power-domains = <&pd_gscl>;
1060                 };
1061
1062                 scaler_0: scaler@15000000 {
1063                         compatible = "samsung,exynos5433-scaler";
1064                         reg = <0x15000000 0x1294>;
1065                         interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1066                         clock-names = "pclk", "aclk", "aclk_xiu";
1067                         clocks = <&cmu_mscl CLK_PCLK_M2MSCALER0>,
1068                                  <&cmu_mscl CLK_ACLK_M2MSCALER0>,
1069                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1070                         iommus = <&sysmmu_scaler_0>;
1071                         power-domains = <&pd_mscl>;
1072                 };
1073
1074                 scaler_1: scaler@15010000 {
1075                         compatible = "samsung,exynos5433-scaler";
1076                         reg = <0x15010000 0x1294>;
1077                         interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1078                         clock-names = "pclk", "aclk", "aclk_xiu";
1079                         clocks = <&cmu_mscl CLK_PCLK_M2MSCALER1>,
1080                                  <&cmu_mscl CLK_ACLK_M2MSCALER1>,
1081                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>;
1082                         iommus = <&sysmmu_scaler_1>;
1083                         power-domains = <&pd_mscl>;
1084                 };
1085
1086                 jpeg: codec@15020000 {
1087                         compatible = "samsung,exynos5433-jpeg";
1088                         reg = <0x15020000 0x10000>;
1089                         interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
1090                         clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
1091                         clocks = <&cmu_mscl CLK_PCLK_JPEG>,
1092                                  <&cmu_mscl CLK_ACLK_JPEG>,
1093                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
1094                                  <&cmu_mscl CLK_SCLK_JPEG>;
1095                         iommus = <&sysmmu_jpeg>;
1096                         power-domains = <&pd_mscl>;
1097                 };
1098
1099                 mfc: codec@152e0000 {
1100                         compatible = "samsung,exynos5433-mfc";
1101                         reg = <0x152E0000 0x10000>;
1102                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1103                         clock-names = "pclk", "aclk", "aclk_xiu";
1104                         clocks = <&cmu_mfc CLK_PCLK_MFC>,
1105                                  <&cmu_mfc CLK_ACLK_MFC>,
1106                                  <&cmu_mfc CLK_ACLK_XIU_MFCX>;
1107                         iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
1108                         iommu-names = "left", "right";
1109                         power-domains = <&pd_mfc>;
1110                 };
1111
1112                 sysmmu_decon0x: sysmmu@13a00000 {
1113                         compatible = "samsung,exynos-sysmmu";
1114                         reg = <0x13a00000 0x1000>;
1115                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
1116                         clock-names = "pclk", "aclk";
1117                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
1118                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
1119                         power-domains = <&pd_disp>;
1120                         #iommu-cells = <0>;
1121                 };
1122
1123                 sysmmu_decon1x: sysmmu@13a10000 {
1124                         compatible = "samsung,exynos-sysmmu";
1125                         reg = <0x13a10000 0x1000>;
1126                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
1127                         clock-names = "pclk", "aclk";
1128                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
1129                                 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
1130                         #iommu-cells = <0>;
1131                         power-domains = <&pd_disp>;
1132                 };
1133
1134                 sysmmu_tv0x: sysmmu@13a20000 {
1135                         compatible = "samsung,exynos-sysmmu";
1136                         reg = <0x13a20000 0x1000>;
1137                         interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
1138                         clock-names = "pclk", "aclk";
1139                         clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
1140                                 <&cmu_disp CLK_ACLK_SMMU_TV0X>;
1141                         #iommu-cells = <0>;
1142                         power-domains = <&pd_disp>;
1143                 };
1144
1145                 sysmmu_tv1x: sysmmu@13a30000 {
1146                         compatible = "samsung,exynos-sysmmu";
1147                         reg = <0x13a30000 0x1000>;
1148                         interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
1149                         clock-names = "pclk", "aclk";
1150                         clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
1151                                 <&cmu_disp CLK_ACLK_SMMU_TV1X>;
1152                         #iommu-cells = <0>;
1153                         power-domains = <&pd_disp>;
1154                 };
1155
1156                 sysmmu_gscl0: sysmmu@13c80000 {
1157                         compatible = "samsung,exynos-sysmmu";
1158                         reg = <0x13C80000 0x1000>;
1159                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
1160                         clock-names = "aclk", "pclk";
1161                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
1162                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
1163                         #iommu-cells = <0>;
1164                         power-domains = <&pd_gscl>;
1165                 };
1166
1167                 sysmmu_gscl1: sysmmu@13c90000 {
1168                         compatible = "samsung,exynos-sysmmu";
1169                         reg = <0x13C90000 0x1000>;
1170                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
1171                         clock-names = "aclk", "pclk";
1172                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
1173                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
1174                         #iommu-cells = <0>;
1175                         power-domains = <&pd_gscl>;
1176                 };
1177
1178                 sysmmu_gscl2: sysmmu@13ca0000 {
1179                         compatible = "samsung,exynos-sysmmu";
1180                         reg = <0x13CA0000 0x1000>;
1181                         interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
1182                         clock-names = "aclk", "pclk";
1183                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
1184                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
1185                         #iommu-cells = <0>;
1186                         power-domains = <&pd_gscl>;
1187                 };
1188
1189                 sysmmu_scaler_0: sysmmu@15040000 {
1190                         compatible = "samsung,exynos-sysmmu";
1191                         reg = <0x15040000 0x1000>;
1192                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
1193                         clock-names = "pclk", "aclk";
1194                         clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER0>,
1195                                  <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER0>;
1196                         #iommu-cells = <0>;
1197                         power-domains = <&pd_mscl>;
1198                 };
1199
1200                 sysmmu_scaler_1: sysmmu@15050000 {
1201                         compatible = "samsung,exynos-sysmmu";
1202                         reg = <0x15050000 0x1000>;
1203                         interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
1204                         clock-names = "pclk", "aclk";
1205                         clocks = <&cmu_mscl CLK_PCLK_SMMU_M2MSCALER1>,
1206                                  <&cmu_mscl CLK_ACLK_SMMU_M2MSCALER1>;
1207                         #iommu-cells = <0>;
1208                         power-domains = <&pd_mscl>;
1209                 };
1210
1211                 sysmmu_jpeg: sysmmu@15060000 {
1212                         compatible = "samsung,exynos-sysmmu";
1213                         reg = <0x15060000 0x1000>;
1214                         interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1215                         clock-names = "pclk", "aclk";
1216                         clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
1217                                  <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
1218                         #iommu-cells = <0>;
1219                         power-domains = <&pd_mscl>;
1220                 };
1221
1222                 sysmmu_mfc_0: sysmmu@15200000 {
1223                         compatible = "samsung,exynos-sysmmu";
1224                         reg = <0x15200000 0x1000>;
1225                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1226                         clock-names = "pclk", "aclk";
1227                         clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
1228                                  <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
1229                         #iommu-cells = <0>;
1230                         power-domains = <&pd_mfc>;
1231                 };
1232
1233                 sysmmu_mfc_1: sysmmu@15210000 {
1234                         compatible = "samsung,exynos-sysmmu";
1235                         reg = <0x15210000 0x1000>;
1236                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1237                         clock-names = "pclk", "aclk";
1238                         clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
1239                                  <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
1240                         #iommu-cells = <0>;
1241                         power-domains = <&pd_mfc>;
1242                 };
1243
1244                 serial_0: serial@14c10000 {
1245                         compatible = "samsung,exynos5433-uart";
1246                         reg = <0x14c10000 0x100>;
1247                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1248                         clocks = <&cmu_peric CLK_PCLK_UART0>,
1249                                 <&cmu_peric CLK_SCLK_UART0>;
1250                         clock-names = "uart", "clk_uart_baud0";
1251                         pinctrl-names = "default";
1252                         pinctrl-0 = <&uart0_bus>;
1253                         status = "disabled";
1254                 };
1255
1256                 serial_1: serial@14c20000 {
1257                         compatible = "samsung,exynos5433-uart";
1258                         reg = <0x14c20000 0x100>;
1259                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1260                         clocks = <&cmu_peric CLK_PCLK_UART1>,
1261                                 <&cmu_peric CLK_SCLK_UART1>;
1262                         clock-names = "uart", "clk_uart_baud0";
1263                         pinctrl-names = "default";
1264                         pinctrl-0 = <&uart1_bus>;
1265                         status = "disabled";
1266                 };
1267
1268                 serial_2: serial@14c30000 {
1269                         compatible = "samsung,exynos5433-uart";
1270                         reg = <0x14c30000 0x100>;
1271                         interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
1272                         clocks = <&cmu_peric CLK_PCLK_UART2>,
1273                                 <&cmu_peric CLK_SCLK_UART2>;
1274                         clock-names = "uart", "clk_uart_baud0";
1275                         pinctrl-names = "default";
1276                         pinctrl-0 = <&uart2_bus>;
1277                         status = "disabled";
1278                 };
1279
1280                 spi_0: spi@14d20000 {
1281                         compatible = "samsung,exynos5433-spi";
1282                         reg = <0x14d20000 0x100>;
1283                         interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
1284                         dmas = <&pdma0 9>, <&pdma0 8>;
1285                         dma-names = "tx", "rx";
1286                         #address-cells = <1>;
1287                         #size-cells = <0>;
1288                         clocks = <&cmu_peric CLK_PCLK_SPI0>,
1289                                 <&cmu_peric CLK_SCLK_SPI0>,
1290                                 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
1291                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1292                         samsung,spi-src-clk = <0>;
1293                         pinctrl-names = "default";
1294                         pinctrl-0 = <&spi0_bus>;
1295                         num-cs = <1>;
1296                         status = "disabled";
1297                 };
1298
1299                 spi_1: spi@14d30000 {
1300                         compatible = "samsung,exynos5433-spi";
1301                         reg = <0x14d30000 0x100>;
1302                         interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1303                         dmas = <&pdma0 11>, <&pdma0 10>;
1304                         dma-names = "tx", "rx";
1305                         #address-cells = <1>;
1306                         #size-cells = <0>;
1307                         clocks = <&cmu_peric CLK_PCLK_SPI1>,
1308                                 <&cmu_peric CLK_SCLK_SPI1>,
1309                                 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1310                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1311                         samsung,spi-src-clk = <0>;
1312                         pinctrl-names = "default";
1313                         pinctrl-0 = <&spi1_bus>;
1314                         num-cs = <1>;
1315                         status = "disabled";
1316                 };
1317
1318                 spi_2: spi@14d40000 {
1319                         compatible = "samsung,exynos5433-spi";
1320                         reg = <0x14d40000 0x100>;
1321                         interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1322                         dmas = <&pdma0 13>, <&pdma0 12>;
1323                         dma-names = "tx", "rx";
1324                         #address-cells = <1>;
1325                         #size-cells = <0>;
1326                         clocks = <&cmu_peric CLK_PCLK_SPI2>,
1327                                 <&cmu_peric CLK_SCLK_SPI2>,
1328                                 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1329                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1330                         samsung,spi-src-clk = <0>;
1331                         pinctrl-names = "default";
1332                         pinctrl-0 = <&spi2_bus>;
1333                         num-cs = <1>;
1334                         status = "disabled";
1335                 };
1336
1337                 spi_3: spi@14d50000 {
1338                         compatible = "samsung,exynos5433-spi";
1339                         reg = <0x14d50000 0x100>;
1340                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1341                         dmas = <&pdma0 23>, <&pdma0 22>;
1342                         dma-names = "tx", "rx";
1343                         #address-cells = <1>;
1344                         #size-cells = <0>;
1345                         clocks = <&cmu_peric CLK_PCLK_SPI3>,
1346                                 <&cmu_peric CLK_SCLK_SPI3>,
1347                                 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1348                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1349                         samsung,spi-src-clk = <0>;
1350                         pinctrl-names = "default";
1351                         pinctrl-0 = <&spi3_bus>;
1352                         num-cs = <1>;
1353                         status = "disabled";
1354                 };
1355
1356                 spi_4: spi@14d00000 {
1357                         compatible = "samsung,exynos5433-spi";
1358                         reg = <0x14d00000 0x100>;
1359                         interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1360                         dmas = <&pdma0 25>, <&pdma0 24>;
1361                         dma-names = "tx", "rx";
1362                         #address-cells = <1>;
1363                         #size-cells = <0>;
1364                         clocks = <&cmu_peric CLK_PCLK_SPI4>,
1365                                 <&cmu_peric CLK_SCLK_SPI4>,
1366                                 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1367                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1368                         samsung,spi-src-clk = <0>;
1369                         pinctrl-names = "default";
1370                         pinctrl-0 = <&spi4_bus>;
1371                         num-cs = <1>;
1372                         status = "disabled";
1373                 };
1374
1375                 adc: adc@14d10000 {
1376                         compatible = "samsung,exynos7-adc";
1377                         reg = <0x14d10000 0x100>;
1378                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1379                         clock-names = "adc";
1380                         clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1381                         #io-channel-cells = <1>;
1382                         io-channel-ranges;
1383                         status = "disabled";
1384                 };
1385
1386                 i2s1: i2s@14d60000 {
1387                         compatible = "samsung,exynos7-i2s";
1388                         reg = <0x14d60000 0x100>;
1389                         dmas = <&pdma0 31 &pdma0 30>;
1390                         dma-names = "tx", "rx";
1391                         interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
1392                         clocks = <&cmu_peric CLK_PCLK_I2S1>,
1393                                  <&cmu_peric CLK_PCLK_I2S1>,
1394                                  <&cmu_peric CLK_SCLK_I2S1>;
1395                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1396                         #clock-cells = <1>;
1397                         samsung,supports-6ch;
1398                         samsung,supports-rstclr;
1399                         samsung,supports-tdm;
1400                         samsung,supports-low-rfs;
1401                         #sound-dai-cells = <1>;
1402                         status = "disabled";
1403                 };
1404
1405                 pwm: pwm@14dd0000 {
1406                         compatible = "samsung,exynos4210-pwm";
1407                         reg = <0x14dd0000 0x100>;
1408                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1409                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1410                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1411                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1412                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1413                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1414                         clocks = <&cmu_peric CLK_PCLK_PWM>;
1415                         clock-names = "timers";
1416                         #pwm-cells = <3>;
1417                         status = "disabled";
1418                 };
1419
1420                 hsi2c_0: hsi2c@14e40000 {
1421                         compatible = "samsung,exynos7-hsi2c";
1422                         reg = <0x14e40000 0x1000>;
1423                         interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1424                         #address-cells = <1>;
1425                         #size-cells = <0>;
1426                         pinctrl-names = "default";
1427                         pinctrl-0 = <&hs_i2c0_bus>;
1428                         clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1429                         clock-names = "hsi2c";
1430                         status = "disabled";
1431                 };
1432
1433                 hsi2c_1: hsi2c@14e50000 {
1434                         compatible = "samsung,exynos7-hsi2c";
1435                         reg = <0x14e50000 0x1000>;
1436                         interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1437                         #address-cells = <1>;
1438                         #size-cells = <0>;
1439                         pinctrl-names = "default";
1440                         pinctrl-0 = <&hs_i2c1_bus>;
1441                         clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1442                         clock-names = "hsi2c";
1443                         status = "disabled";
1444                 };
1445
1446                 hsi2c_2: hsi2c@14e60000 {
1447                         compatible = "samsung,exynos7-hsi2c";
1448                         reg = <0x14e60000 0x1000>;
1449                         interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1450                         #address-cells = <1>;
1451                         #size-cells = <0>;
1452                         pinctrl-names = "default";
1453                         pinctrl-0 = <&hs_i2c2_bus>;
1454                         clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1455                         clock-names = "hsi2c";
1456                         status = "disabled";
1457                 };
1458
1459                 hsi2c_3: hsi2c@14e70000 {
1460                         compatible = "samsung,exynos7-hsi2c";
1461                         reg = <0x14e70000 0x1000>;
1462                         interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1463                         #address-cells = <1>;
1464                         #size-cells = <0>;
1465                         pinctrl-names = "default";
1466                         pinctrl-0 = <&hs_i2c3_bus>;
1467                         clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1468                         clock-names = "hsi2c";
1469                         status = "disabled";
1470                 };
1471
1472                 hsi2c_4: hsi2c@14ec0000 {
1473                         compatible = "samsung,exynos7-hsi2c";
1474                         reg = <0x14ec0000 0x1000>;
1475                         interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1476                         #address-cells = <1>;
1477                         #size-cells = <0>;
1478                         pinctrl-names = "default";
1479                         pinctrl-0 = <&hs_i2c4_bus>;
1480                         clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1481                         clock-names = "hsi2c";
1482                         status = "disabled";
1483                 };
1484
1485                 hsi2c_5: hsi2c@14ed0000 {
1486                         compatible = "samsung,exynos7-hsi2c";
1487                         reg = <0x14ed0000 0x1000>;
1488                         interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1489                         #address-cells = <1>;
1490                         #size-cells = <0>;
1491                         pinctrl-names = "default";
1492                         pinctrl-0 = <&hs_i2c5_bus>;
1493                         clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1494                         clock-names = "hsi2c";
1495                         status = "disabled";
1496                 };
1497
1498                 hsi2c_6: hsi2c@14ee0000 {
1499                         compatible = "samsung,exynos7-hsi2c";
1500                         reg = <0x14ee0000 0x1000>;
1501                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1502                         #address-cells = <1>;
1503                         #size-cells = <0>;
1504                         pinctrl-names = "default";
1505                         pinctrl-0 = <&hs_i2c6_bus>;
1506                         clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1507                         clock-names = "hsi2c";
1508                         status = "disabled";
1509                 };
1510
1511                 hsi2c_7: hsi2c@14ef0000 {
1512                         compatible = "samsung,exynos7-hsi2c";
1513                         reg = <0x14ef0000 0x1000>;
1514                         interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1515                         #address-cells = <1>;
1516                         #size-cells = <0>;
1517                         pinctrl-names = "default";
1518                         pinctrl-0 = <&hs_i2c7_bus>;
1519                         clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1520                         clock-names = "hsi2c";
1521                         status = "disabled";
1522                 };
1523
1524                 hsi2c_8: hsi2c@14d90000 {
1525                         compatible = "samsung,exynos7-hsi2c";
1526                         reg = <0x14d90000 0x1000>;
1527                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1528                         #address-cells = <1>;
1529                         #size-cells = <0>;
1530                         pinctrl-names = "default";
1531                         pinctrl-0 = <&hs_i2c8_bus>;
1532                         clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1533                         clock-names = "hsi2c";
1534                         status = "disabled";
1535                 };
1536
1537                 hsi2c_9: hsi2c@14da0000 {
1538                         compatible = "samsung,exynos7-hsi2c";
1539                         reg = <0x14da0000 0x1000>;
1540                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1541                         #address-cells = <1>;
1542                         #size-cells = <0>;
1543                         pinctrl-names = "default";
1544                         pinctrl-0 = <&hs_i2c9_bus>;
1545                         clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1546                         clock-names = "hsi2c";
1547                         status = "disabled";
1548                 };
1549
1550                 hsi2c_10: hsi2c@14de0000 {
1551                         compatible = "samsung,exynos7-hsi2c";
1552                         reg = <0x14de0000 0x1000>;
1553                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1554                         #address-cells = <1>;
1555                         #size-cells = <0>;
1556                         pinctrl-names = "default";
1557                         pinctrl-0 = <&hs_i2c10_bus>;
1558                         clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1559                         clock-names = "hsi2c";
1560                         status = "disabled";
1561                 };
1562
1563                 hsi2c_11: hsi2c@14df0000 {
1564                         compatible = "samsung,exynos7-hsi2c";
1565                         reg = <0x14df0000 0x1000>;
1566                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1567                         #address-cells = <1>;
1568                         #size-cells = <0>;
1569                         pinctrl-names = "default";
1570                         pinctrl-0 = <&hs_i2c11_bus>;
1571                         clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1572                         clock-names = "hsi2c";
1573                         status = "disabled";
1574                 };
1575
1576                 usbdrd30: usbdrd {
1577                         compatible = "samsung,exynos5433-dwusb3";
1578                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1579                                 <&cmu_fsys CLK_SCLK_USBDRD30>,
1580                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1581                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
1582                         clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1583                         #address-cells = <1>;
1584                         #size-cells = <1>;
1585                         ranges;
1586                         status = "disabled";
1587
1588                         usbdrd_dwc3: dwc3@15400000 {
1589                                 compatible = "snps,dwc3";
1590                                 clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
1591                                         <&cmu_fsys CLK_ACLK_USBDRD30>,
1592                                         <&cmu_fsys CLK_SCLK_USBDRD30>;
1593                                 clock-names = "ref", "bus_early", "suspend";
1594                                 reg = <0x15400000 0x10000>;
1595                                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1596                                 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1597                                 phy-names = "usb2-phy", "usb3-phy";
1598                         };
1599                 };
1600
1601                 usbdrd30_phy: phy@15500000 {
1602                         compatible = "samsung,exynos5433-usbdrd-phy";
1603                         reg = <0x15500000 0x100>;
1604                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1605                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1606                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1607                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1608                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1609                                         "itp";
1610                         #phy-cells = <1>;
1611                         samsung,pmu-syscon = <&pmu_system_controller>;
1612                         status = "disabled";
1613                 };
1614
1615                 usbhost30_phy: phy@15580000 {
1616                         compatible = "samsung,exynos5433-usbdrd-phy";
1617                         reg = <0x15580000 0x100>;
1618                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1619                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1620                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1621                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1622                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1623                                         "itp";
1624                         #phy-cells = <1>;
1625                         samsung,pmu-syscon = <&pmu_system_controller>;
1626                         status = "disabled";
1627                 };
1628
1629                 usbhost30: usbhost {
1630                         compatible = "samsung,exynos5433-dwusb3";
1631                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1632                                 <&cmu_fsys CLK_SCLK_USBHOST30>,
1633                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1634                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
1635                         clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
1636                         #address-cells = <1>;
1637                         #size-cells = <1>;
1638                         ranges;
1639                         status = "disabled";
1640
1641                         usbhost_dwc3: dwc3@15a00000 {
1642                                 compatible = "snps,dwc3";
1643                                 clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
1644                                         <&cmu_fsys CLK_ACLK_USBHOST30>,
1645                                         <&cmu_fsys CLK_SCLK_USBHOST30>;
1646                                 clock-names = "ref", "bus_early", "suspend";
1647                                 reg = <0x15a00000 0x10000>;
1648                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1649                                 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1650                                 phy-names = "usb2-phy", "usb3-phy";
1651                         };
1652                 };
1653
1654                 mshc_0: mshc@15540000 {
1655                         compatible = "samsung,exynos7-dw-mshc-smu";
1656                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1657                         #address-cells = <1>;
1658                         #size-cells = <0>;
1659                         reg = <0x15540000 0x2000>;
1660                         clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1661                                 <&cmu_fsys CLK_SCLK_MMC0>;
1662                         clock-names = "biu", "ciu";
1663                         fifo-depth = <0x40>;
1664                         status = "disabled";
1665                 };
1666
1667                 mshc_1: mshc@15550000 {
1668                         compatible = "samsung,exynos7-dw-mshc-smu";
1669                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1670                         #address-cells = <1>;
1671                         #size-cells = <0>;
1672                         reg = <0x15550000 0x2000>;
1673                         clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1674                                 <&cmu_fsys CLK_SCLK_MMC1>;
1675                         clock-names = "biu", "ciu";
1676                         fifo-depth = <0x40>;
1677                         status = "disabled";
1678                 };
1679
1680                 mshc_2: mshc@15560000 {
1681                         compatible = "samsung,exynos7-dw-mshc-smu";
1682                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1683                         #address-cells = <1>;
1684                         #size-cells = <0>;
1685                         reg = <0x15560000 0x2000>;
1686                         clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1687                                 <&cmu_fsys CLK_SCLK_MMC2>;
1688                         clock-names = "biu", "ciu";
1689                         fifo-depth = <0x40>;
1690                         status = "disabled";
1691                 };
1692
1693                 amba {
1694                         compatible = "simple-bus";
1695                         #address-cells = <1>;
1696                         #size-cells = <1>;
1697                         ranges;
1698
1699                         pdma0: pdma@15610000 {
1700                                 compatible = "arm,pl330", "arm,primecell";
1701                                 reg = <0x15610000 0x1000>;
1702                                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1703                                 clocks = <&cmu_fsys CLK_PDMA0>;
1704                                 clock-names = "apb_pclk";
1705                                 #dma-cells = <1>;
1706                                 #dma-channels = <8>;
1707                                 #dma-requests = <32>;
1708                         };
1709
1710                         pdma1: pdma@15600000 {
1711                                 compatible = "arm,pl330", "arm,primecell";
1712                                 reg = <0x15600000 0x1000>;
1713                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1714                                 clocks = <&cmu_fsys CLK_PDMA1>;
1715                                 clock-names = "apb_pclk";
1716                                 #dma-cells = <1>;
1717                                 #dma-channels = <8>;
1718                                 #dma-requests = <32>;
1719                         };
1720                 };
1721
1722                 audio-subsystem@11400000 {
1723                         compatible = "samsung,exynos5433-lpass";
1724                         reg = <0x11400000 0x100>, <0x11500000 0x08>;
1725                         clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
1726                         clock-names = "sfr0_ctrl";
1727                         samsung,pmu-syscon = <&pmu_system_controller>;
1728                         power-domains = <&pd_aud>;
1729                         #address-cells = <1>;
1730                         #size-cells = <1>;
1731                         ranges;
1732
1733                         adma: adma@11420000 {
1734                                 compatible = "arm,pl330", "arm,primecell";
1735                                 reg = <0x11420000 0x1000>;
1736                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1737                                 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1738                                 clock-names = "apb_pclk";
1739                                 #dma-cells = <1>;
1740                                 #dma-channels = <8>;
1741                                 #dma-requests = <32>;
1742                                 power-domains = <&pd_aud>;
1743                         };
1744
1745                         i2s0: i2s@11440000 {
1746                                 compatible = "samsung,exynos7-i2s";
1747                                 reg = <0x11440000 0x100>;
1748                                 dmas = <&adma 0 &adma 2>;
1749                                 dma-names = "tx", "rx";
1750                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1751                                 #address-cells = <1>;
1752                                 #size-cells = <0>;
1753                                 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1754                                         <&cmu_aud CLK_SCLK_AUD_I2S>,
1755                                         <&cmu_aud CLK_SCLK_I2S_BCLK>;
1756                                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1757                                 #clock-cells = <1>;
1758                                 pinctrl-names = "default";
1759                                 pinctrl-0 = <&i2s0_bus>;
1760                                 power-domains = <&pd_aud>;
1761                                 #sound-dai-cells = <1>;
1762                                 status = "disabled";
1763                         };
1764
1765                         serial_3: serial@11460000 {
1766                                 compatible = "samsung,exynos5433-uart";
1767                                 reg = <0x11460000 0x100>;
1768                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1769                                 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1770                                         <&cmu_aud CLK_SCLK_AUD_UART>;
1771                                 clock-names = "uart", "clk_uart_baud0";
1772                                 pinctrl-names = "default";
1773                                 pinctrl-0 = <&uart_aud_bus>;
1774                                 power-domains = <&pd_aud>;
1775                                 status = "disabled";
1776                         };
1777                 };
1778         };
1779
1780         timer: timer {
1781                 compatible = "arm,armv8-timer";
1782                 interrupts = <GIC_PPI 13
1783                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1784                         <GIC_PPI 14
1785                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1786                         <GIC_PPI 11
1787                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1788                         <GIC_PPI 10
1789                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1790         };
1791 };
1792
1793 #include "exynos5433-bus.dtsi"
1794 #include "exynos5433-pinctrl.dtsi"
1795 #include "exynos5433-tmu.dtsi"