arch/arm64/boot/dts/exynos/exynos5433.dtsi

   1 /*
   2  * Samsung's Exynos5433 SoC device tree source
   3  *
   4  * Copyright (c) 2016 Samsung Electronics Co., Ltd.
   5  *
   6  * Samsung's Exynos5433 SoC device nodes are listed in this file.
   7  * Exynos5433 based board files can include this file and provide
   8  * values for board specific bindings.
   9  *
  10  * Note: This file does not include device nodes for all the controllers in
  11  * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
  12  * additional nodes can be added to this file.
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #include <dt-bindings/clock/exynos5433.h>
  20 #include <dt-bindings/interrupt-controller/arm-gic.h>
  21
  22 / {
  23         compatible = "samsung,exynos5433";
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         interrupt-parent = <&gic>;
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@100 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a53", "arm,armv8";
  36                         enable-method = "psci";
  37                         reg = <0x100>;
  38                         clock-frequency = <1300000000>;
  39                         clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
  40                         clock-names = "apolloclk";
  41                         operating-points-v2 = <&cluster_a53_opp_table>;
  42                         #cooling-cells = <2>;
  43                 };
  44
  45                 cpu1: cpu@101 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a53", "arm,armv8";
  48                         enable-method = "psci";
  49                         reg = <0x101>;
  50                         clock-frequency = <1300000000>;
  51                         operating-points-v2 = <&cluster_a53_opp_table>;
  52                         #cooling-cells = <2>;
  53                 };
  54
  55                 cpu2: cpu@102 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a53", "arm,armv8";
  58                         enable-method = "psci";
  59                         reg = <0x102>;
  60                         clock-frequency = <1300000000>;
  61                         operating-points-v2 = <&cluster_a53_opp_table>;
  62                         #cooling-cells = <2>;
  63                 };
  64
  65                 cpu3: cpu@103 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         enable-method = "psci";
  69                         reg = <0x103>;
  70                         clock-frequency = <1300000000>;
  71                         operating-points-v2 = <&cluster_a53_opp_table>;
  72                         #cooling-cells = <2>;
  73                 };
  74
  75                 cpu4: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a57", "arm,armv8";
  78                         enable-method = "psci";
  79                         reg = <0x0>;
  80                         clock-frequency = <1900000000>;
  81                         clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
  82                         clock-names = "atlasclk";
  83                         operating-points-v2 = <&cluster_a57_opp_table>;
  84                         #cooling-cells = <2>;
  85                 };
  86
  87                 cpu5: cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a57", "arm,armv8";
  90                         enable-method = "psci";
  91                         reg = <0x1>;
  92                         clock-frequency = <1900000000>;
  93                         operating-points-v2 = <&cluster_a57_opp_table>;
  94                         #cooling-cells = <2>;
  95                 };
  96
  97                 cpu6: cpu@2 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a57", "arm,armv8";
 100                         enable-method = "psci";
 101                         reg = <0x2>;
 102                         clock-frequency = <1900000000>;
 103                         operating-points-v2 = <&cluster_a57_opp_table>;
 104                         #cooling-cells = <2>;
 105                 };
 106
 107                 cpu7: cpu@3 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a57", "arm,armv8";
 110                         enable-method = "psci";
 111                         reg = <0x3>;
 112                         clock-frequency = <1900000000>;
 113                         operating-points-v2 = <&cluster_a57_opp_table>;
 114                         #cooling-cells = <2>;
 115                 };
 116         };
 117
 118         cluster_a53_opp_table: opp_table0 {
 119                 compatible = "operating-points-v2";
 120                 opp-shared;
 121
 122                 opp@400000000 {
 123                         opp-hz = /bits/ 64 <400000000>;
 124                         opp-microvolt = <900000>;
 125                 };
 126                 opp@500000000 {
 127                         opp-hz = /bits/ 64 <500000000>;
 128                         opp-microvolt = <925000>;
 129                 };
 130                 opp@600000000 {
 131                         opp-hz = /bits/ 64 <600000000>;
 132                         opp-microvolt = <950000>;
 133                 };
 134                 opp@700000000 {
 135                         opp-hz = /bits/ 64 <700000000>;
 136                         opp-microvolt = <975000>;
 137                 };
 138                 opp@800000000 {
 139                         opp-hz = /bits/ 64 <800000000>;
 140                         opp-microvolt = <1000000>;
 141                 };
 142                 opp@900000000 {
 143                         opp-hz = /bits/ 64 <900000000>;
 144                         opp-microvolt = <1050000>;
 145                 };
 146                 opp@1000000000 {
 147                         opp-hz = /bits/ 64 <1000000000>;
 148                         opp-microvolt = <1075000>;
 149                 };
 150                 opp@1100000000 {
 151                         opp-hz = /bits/ 64 <1100000000>;
 152                         opp-microvolt = <1112500>;
 153                 };
 154                 opp@1200000000 {
 155                         opp-hz = /bits/ 64 <1200000000>;
 156                         opp-microvolt = <1112500>;
 157                 };
 158                 opp@1300000000 {
 159                         opp-hz = /bits/ 64 <1300000000>;
 160                         opp-microvolt = <1150000>;
 161                 };
 162         };
 163
 164         cluster_a57_opp_table: opp_table1 {
 165                 compatible = "operating-points-v2";
 166                 opp-shared;
 167
 168                 opp@500000000 {
 169                         opp-hz = /bits/ 64 <500000000>;
 170                         opp-microvolt = <900000>;
 171                 };
 172                 opp@600000000 {
 173                         opp-hz = /bits/ 64 <600000000>;
 174                         opp-microvolt = <900000>;
 175                 };
 176                 opp@700000000 {
 177                         opp-hz = /bits/ 64 <700000000>;
 178                         opp-microvolt = <912500>;
 179                 };
 180                 opp@800000000 {
 181                         opp-hz = /bits/ 64 <800000000>;
 182                         opp-microvolt = <912500>;
 183                 };
 184                 opp@900000000 {
 185                         opp-hz = /bits/ 64 <900000000>;
 186                         opp-microvolt = <937500>;
 187                 };
 188                 opp@1000000000 {
 189                         opp-hz = /bits/ 64 <1000000000>;
 190                         opp-microvolt = <975000>;
 191                 };
 192                 opp@1100000000 {
 193                         opp-hz = /bits/ 64 <1100000000>;
 194                         opp-microvolt = <1012500>;
 195                 };
 196                 opp@1200000000 {
 197                         opp-hz = /bits/ 64 <1200000000>;
 198                         opp-microvolt = <1037500>;
 199                 };
 200                 opp@1300000000 {
 201                         opp-hz = /bits/ 64 <1300000000>;
 202                         opp-microvolt = <1062500>;
 203                 };
 204                 opp@1400000000 {
 205                         opp-hz = /bits/ 64 <1400000000>;
 206                         opp-microvolt = <1087500>;
 207                 };
 208                 opp@1500000000 {
 209                         opp-hz = /bits/ 64 <1500000000>;
 210                         opp-microvolt = <1125000>;
 211                 };
 212                 opp@1600000000 {
 213                         opp-hz = /bits/ 64 <1600000000>;
 214                         opp-microvolt = <1137500>;
 215                 };
 216                 opp@1700000000 {
 217                         opp-hz = /bits/ 64 <1700000000>;
 218                         opp-microvolt = <1175000>;
 219                 };
 220                 opp@1800000000 {
 221                         opp-hz = /bits/ 64 <1800000000>;
 222                         opp-microvolt = <1212500>;
 223                 };
 224                 opp@1900000000 {
 225                         opp-hz = /bits/ 64 <1900000000>;
 226                         opp-microvolt = <1262500>;
 227                 };
 228         };
 229
 230         psci {
 231                 compatible = "arm,psci";
 232                 method = "smc";
 233                 cpu_off = <0x84000002>;
 234                 cpu_on = <0xC4000003>;
 235         };
 236
 237         reboot: syscon-reboot {
 238                 compatible = "syscon-reboot";
 239                 regmap = <&pmu_system_controller>;
 240                 offset = <0x400>; /* SWRESET */
 241                 mask = <0x1>;
 242         };
 243
 244         soc: soc {
 245                 compatible = "simple-bus";
 246                 #address-cells = <1>;
 247                 #size-cells = <1>;
 248                 ranges = <0x0 0x0 0x0 0x18000000>;
 249
 250                 chipid@10000000 {
 251                         compatible = "samsung,exynos4210-chipid";
 252                         reg = <0x10000000 0x100>;
 253                 };
 254
 255                 xxti: xxti {
 256                         compatible = "fixed-clock";
 257                         clock-output-names = "oscclk";
 258                         #clock-cells = <0>;
 259                 };
 260
 261                 cmu_top: clock-controller@10030000 {
 262                         compatible = "samsung,exynos5433-cmu-top";
 263                         reg = <0x10030000 0x1000>;
 264                         #clock-cells = <1>;
 265
 266                         clock-names = "oscclk",
 267                                 "sclk_mphy_pll",
 268                                 "sclk_mfc_pll",
 269                                 "sclk_bus_pll";
 270                         clocks = <&xxti>,
 271                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>,
 272                                 <&cmu_mif CLK_SCLK_MFC_PLL>,
 273                                 <&cmu_mif CLK_SCLK_BUS_PLL>;
 274                 };
 275
 276                 cmu_cpif: clock-controller@10fc0000 {
 277                         compatible = "samsung,exynos5433-cmu-cpif";
 278                         reg = <0x10fc0000 0x1000>;
 279                         #clock-cells = <1>;
 280
 281                         clock-names = "oscclk";
 282                         clocks = <&xxti>;
 283                 };
 284
 285                 cmu_mif: clock-controller@105b0000 {
 286                         compatible = "samsung,exynos5433-cmu-mif";
 287                         reg = <0x105b0000 0x2000>;
 288                         #clock-cells = <1>;
 289
 290                         clock-names = "oscclk",
 291                                 "sclk_mphy_pll";
 292                         clocks = <&xxti>,
 293                                 <&cmu_cpif CLK_SCLK_MPHY_PLL>;
 294                 };
 295
 296                 cmu_peric: clock-controller@14c80000 {
 297                         compatible = "samsung,exynos5433-cmu-peric";
 298                         reg = <0x14c80000 0x1000>;
 299                         #clock-cells = <1>;
 300                 };
 301
 302                 cmu_peris: clock-controller@0x10040000 {
 303                         compatible = "samsung,exynos5433-cmu-peris";
 304                         reg = <0x10040000 0x1000>;
 305                         #clock-cells = <1>;
 306                 };
 307
 308                 cmu_fsys: clock-controller@156e0000 {
 309                         compatible = "samsung,exynos5433-cmu-fsys";
 310                         reg = <0x156e0000 0x1000>;
 311                         #clock-cells = <1>;
 312
 313                         clock-names = "oscclk",
 314                                 "sclk_ufs_mphy",
 315                                 "aclk_fsys_200",
 316                                 "sclk_pcie_100_fsys",
 317                                 "sclk_ufsunipro_fsys",
 318                                 "sclk_mmc2_fsys",
 319                                 "sclk_mmc1_fsys",
 320                                 "sclk_mmc0_fsys",
 321                                 "sclk_usbhost30_fsys",
 322                                 "sclk_usbdrd30_fsys";
 323                         clocks = <&xxti>,
 324                                 <&cmu_cpif CLK_SCLK_UFS_MPHY>,
 325                                 <&cmu_top CLK_ACLK_FSYS_200>,
 326                                 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 327                                 <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 328                                 <&cmu_top CLK_SCLK_MMC2_FSYS>,
 329                                 <&cmu_top CLK_SCLK_MMC1_FSYS>,
 330                                 <&cmu_top CLK_SCLK_MMC0_FSYS>,
 331                                 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 332                                 <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 333                 };
 334
 335                 cmu_g2d: clock-controller@12460000 {
 336                         compatible = "samsung,exynos5433-cmu-g2d";
 337                         reg = <0x12460000 0x1000>;
 338                         #clock-cells = <1>;
 339
 340                         clock-names = "oscclk",
 341                                 "aclk_g2d_266",
 342                                 "aclk_g2d_400";
 343                         clocks = <&xxti>,
 344                                 <&cmu_top CLK_ACLK_G2D_266>,
 345                                 <&cmu_top CLK_ACLK_G2D_400>;
 346                 };
 347
 348                 cmu_disp: clock-controller@13b90000 {
 349                         compatible = "samsung,exynos5433-cmu-disp";
 350                         reg = <0x13b90000 0x1000>;
 351                         #clock-cells = <1>;
 352
 353                         clock-names = "oscclk",
 354                                 "sclk_dsim1_disp",
 355                                 "sclk_dsim0_disp",
 356                                 "sclk_dsd_disp",
 357                                 "sclk_decon_tv_eclk_disp",
 358                                 "sclk_decon_vclk_disp",
 359                                 "sclk_decon_eclk_disp",
 360                                 "sclk_decon_tv_vclk_disp",
 361                                 "aclk_disp_333";
 362                         clocks = <&xxti>,
 363                                 <&cmu_mif CLK_SCLK_DSIM1_DISP>,
 364                                 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
 365                                 <&cmu_mif CLK_SCLK_DSD_DISP>,
 366                                 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 367                                 <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 368                                 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 369                                 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 370                                 <&cmu_mif CLK_ACLK_DISP_333>;
 371                 };
 372
 373                 cmu_aud: clock-controller@114c0000 {
 374                         compatible = "samsung,exynos5433-cmu-aud";
 375                         reg = <0x114c0000 0x1000>;
 376                         #clock-cells = <1>;
 377                         clock-names = "oscclk", "fout_aud_pll";
 378                         clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
 379                 };
 380
 381                 cmu_bus0: clock-controller@13600000 {
 382                         compatible = "samsung,exynos5433-cmu-bus0";
 383                         reg = <0x13600000 0x1000>;
 384                         #clock-cells = <1>;
 385
 386                         clock-names = "aclk_bus0_400";
 387                         clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 388                 };
 389
 390                 cmu_bus1: clock-controller@14800000 {
 391                         compatible = "samsung,exynos5433-cmu-bus1";
 392                         reg = <0x14800000 0x1000>;
 393                         #clock-cells = <1>;
 394
 395                         clock-names = "aclk_bus1_400";
 396                         clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 397                 };
 398
 399                 cmu_bus2: clock-controller@13400000 {
 400                         compatible = "samsung,exynos5433-cmu-bus2";
 401                         reg = <0x13400000 0x1000>;
 402                         #clock-cells = <1>;
 403
 404                         clock-names = "oscclk", "aclk_bus2_400";
 405                         clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 406                 };
 407
 408                 cmu_g3d: clock-controller@14aa0000 {
 409                         compatible = "samsung,exynos5433-cmu-g3d";
 410                         reg = <0x14aa0000 0x2000>;
 411                         #clock-cells = <1>;
 412
 413                         clock-names = "oscclk", "aclk_g3d_400";
 414                         clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 415                 };
 416
 417                 cmu_gscl: clock-controller@13cf0000 {
 418                         compatible = "samsung,exynos5433-cmu-gscl";
 419                         reg = <0x13cf0000 0x1000>;
 420                         #clock-cells = <1>;
 421
 422                         clock-names = "oscclk",
 423                                 "aclk_gscl_111",
 424                                 "aclk_gscl_333";
 425                         clocks = <&xxti>,
 426                                 <&cmu_top CLK_ACLK_GSCL_111>,
 427                                 <&cmu_top CLK_ACLK_GSCL_333>;
 428                 };
 429
 430                 cmu_apollo: clock-controller@11900000 {
 431                         compatible = "samsung,exynos5433-cmu-apollo";
 432                         reg = <0x11900000 0x2000>;
 433                         #clock-cells = <1>;
 434
 435                         clock-names = "oscclk", "sclk_bus_pll_apollo";
 436                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 437                 };
 438
 439                 cmu_atlas: clock-controller@11800000 {
 440                         compatible = "samsung,exynos5433-cmu-atlas";
 441                         reg = <0x11800000 0x2000>;
 442                         #clock-cells = <1>;
 443
 444                         clock-names = "oscclk", "sclk_bus_pll_atlas";
 445                         clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 446                 };
 447
 448                 cmu_mscl: clock-controller@105d0000 {
 449                         compatible = "samsung,exynos5433-cmu-mscl";
 450                         reg = <0x150d0000 0x1000>;
 451                         #clock-cells = <1>;
 452
 453                         clock-names = "oscclk",
 454                                 "sclk_jpeg_mscl",
 455                                 "aclk_mscl_400";
 456                         clocks = <&xxti>,
 457                                 <&cmu_top CLK_SCLK_JPEG_MSCL>,
 458                                 <&cmu_top CLK_ACLK_MSCL_400>;
 459                 };
 460
 461                 cmu_mfc: clock-controller@15280000 {
 462                         compatible = "samsung,exynos5433-cmu-mfc";
 463                         reg = <0x15280000 0x1000>;
 464                         #clock-cells = <1>;
 465
 466                         clock-names = "oscclk", "aclk_mfc_400";
 467                         clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 468                 };
 469
 470                 cmu_hevc: clock-controller@14f80000 {
 471                         compatible = "samsung,exynos5433-cmu-hevc";
 472                         reg = <0x14f80000 0x1000>;
 473                         #clock-cells = <1>;
 474
 475                         clock-names = "oscclk", "aclk_hevc_400";
 476                         clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 477                 };
 478
 479                 cmu_isp: clock-controller@146d0000 {
 480                         compatible = "samsung,exynos5433-cmu-isp";
 481                         reg = <0x146d0000 0x1000>;
 482                         #clock-cells = <1>;
 483
 484                         clock-names = "oscclk",
 485                                 "aclk_isp_dis_400",
 486                                 "aclk_isp_400";
 487                         clocks = <&xxti>,
 488                                 <&cmu_top CLK_ACLK_ISP_DIS_400>,
 489                                 <&cmu_top CLK_ACLK_ISP_400>;
 490                 };
 491
 492                 cmu_cam0: clock-controller@120d0000 {
 493                         compatible = "samsung,exynos5433-cmu-cam0";
 494                         reg = <0x120d0000 0x1000>;
 495                         #clock-cells = <1>;
 496
 497                         clock-names = "oscclk",
 498                                 "aclk_cam0_333",
 499                                 "aclk_cam0_400",
 500                                 "aclk_cam0_552";
 501                         clocks = <&xxti>,
 502                                 <&cmu_top CLK_ACLK_CAM0_333>,
 503                                 <&cmu_top CLK_ACLK_CAM0_400>,
 504                                 <&cmu_top CLK_ACLK_CAM0_552>;
 505                 };
 506
 507                 cmu_cam1: clock-controller@145d0000 {
 508                         compatible = "samsung,exynos5433-cmu-cam1";
 509                         reg = <0x145d0000 0x1000>;
 510                         #clock-cells = <1>;
 511
 512                         clock-names = "oscclk",
 513                                 "sclk_isp_uart_cam1",
 514                                 "sclk_isp_spi1_cam1",
 515                                 "sclk_isp_spi0_cam1",
 516                                 "aclk_cam1_333",
 517                                 "aclk_cam1_400",
 518                                 "aclk_cam1_552";
 519                         clocks = <&xxti>,
 520                                 <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
 521                                 <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
 522                                 <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
 523                                 <&cmu_top CLK_ACLK_CAM1_333>,
 524                                 <&cmu_top CLK_ACLK_CAM1_400>,
 525                                 <&cmu_top CLK_ACLK_CAM1_552>;
 526                 };
 527
 528                 tmu_atlas0: tmu@10060000 {
 529                         compatible = "samsung,exynos5433-tmu";
 530                         reg = <0x10060000 0x200>;
 531                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 533                                 <&cmu_peris CLK_SCLK_TMU0>;
 534                         clock-names = "tmu_apbif", "tmu_sclk";
 535                         #include "exynos5433-tmu-sensor-conf.dtsi"
 536                         status = "disabled";
 537                 };
 538
 539                 tmu_atlas1: tmu@10068000 {
 540                         compatible = "samsung,exynos5433-tmu";
 541                         reg = <0x10068000 0x200>;
 542                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
 544                                 <&cmu_peris CLK_SCLK_TMU0>;
 545                         clock-names = "tmu_apbif", "tmu_sclk";
 546                         #include "exynos5433-tmu-sensor-conf.dtsi"
 547                         status = "disabled";
 548                 };
 549
 550                 tmu_g3d: tmu@10070000 {
 551                         compatible = "samsung,exynos5433-tmu";
 552                         reg = <0x10070000 0x200>;
 553                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 555                                 <&cmu_peris CLK_SCLK_TMU1>;
 556                         clock-names = "tmu_apbif", "tmu_sclk";
 557                         #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
 558                         status = "disabled";
 559                 };
 560
 561                 tmu_apollo: tmu@10078000 {
 562                         compatible = "samsung,exynos5433-tmu";
 563                         reg = <0x10078000 0x200>;
 564                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 565                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 566                                 <&cmu_peris CLK_SCLK_TMU1>;
 567                         clock-names = "tmu_apbif", "tmu_sclk";
 568                         #include "exynos5433-tmu-sensor-conf.dtsi"
 569                         status = "disabled";
 570                 };
 571
 572                 tmu_isp: tmu@1007c000 {
 573                         compatible = "samsung,exynos5433-tmu";
 574                         reg = <0x1007c000 0x200>;
 575                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
 577                                 <&cmu_peris CLK_SCLK_TMU1>;
 578                         clock-names = "tmu_apbif", "tmu_sclk";
 579                         #include "exynos5433-tmu-sensor-conf.dtsi"
 580                         status = "disabled";
 581                 };
 582
 583                 mct@101c0000 {
 584                         compatible = "samsung,exynos4210-mct";
 585                         reg = <0x101c0000 0x800>;
 586                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 587                                 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 588                                 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 589                                 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 590                                 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 591                                 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 592                                 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 593                                 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 594                                 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 595                                 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 596                                 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 597                                 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 598                         clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
 599                         clock-names = "fin_pll", "mct";
 600                 };
 601
 602                 pinctrl_alive: pinctrl@10580000 {
 603                         compatible = "samsung,exynos5433-pinctrl";
 604                         reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
 605
 606                         wakeup-interrupt-controller {
 607                                 compatible = "samsung,exynos7-wakeup-eint";
 608                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 609                         };
 610                 };
 611
 612                 pinctrl_aud: pinctrl@114b0000 {
 613                         compatible = "samsung,exynos5433-pinctrl";
 614                         reg = <0x114b0000 0x1000>;
 615                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 616                 };
 617
 618                 pinctrl_cpif: pinctrl@10fe0000 {
 619                         compatible = "samsung,exynos5433-pinctrl";
 620                         reg = <0x10fe0000 0x1000>;
 621                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 622                 };
 623
 624                 pinctrl_ese: pinctrl@14ca0000 {
 625                         compatible = "samsung,exynos5433-pinctrl";
 626                         reg = <0x14ca0000 0x1000>;
 627                         interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 628                 };
 629
 630                 pinctrl_finger: pinctrl@14cb0000 {
 631                         compatible = "samsung,exynos5433-pinctrl";
 632                         reg = <0x14cb0000 0x1000>;
 633                         interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
 634                 };
 635
 636                 pinctrl_fsys: pinctrl@15690000 {
 637                         compatible = "samsung,exynos5433-pinctrl";
 638                         reg = <0x15690000 0x1000>;
 639                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 640                 };
 641
 642                 pinctrl_imem: pinctrl@11090000 {
 643                         compatible = "samsung,exynos5433-pinctrl";
 644                         reg = <0x11090000 0x1000>;
 645                         interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
 646                 };
 647
 648                 pinctrl_nfc: pinctrl@14cd0000 {
 649                         compatible = "samsung,exynos5433-pinctrl";
 650                         reg = <0x14cd0000 0x1000>;
 651                         interrupts = <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
 652                 };
 653
 654                 pinctrl_peric: pinctrl@14cc0000 {
 655                         compatible = "samsung,exynos5433-pinctrl";
 656                         reg = <0x14cc0000 0x1100>;
 657                         interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
 658                 };
 659
 660                 pinctrl_touch: pinctrl@14ce0000 {
 661                         compatible = "samsung,exynos5433-pinctrl";
 662                         reg = <0x14ce0000 0x1100>;
 663                         interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
 664                 };
 665
 666                 pmu_system_controller: system-controller@105c0000 {
 667                         compatible = "samsung,exynos5433-pmu", "syscon";
 668                         reg = <0x105c0000 0x5008>;
 669                         #clock-cells = <1>;
 670                         clock-names = "clkout16";
 671                         clocks = <&xxti>;
 672                 };
 673
 674                 gic: interrupt-controller@11001000 {
 675                         compatible = "arm,gic-400";
 676                         #interrupt-cells = <3>;
 677                         interrupt-controller;
 678                         reg = <0x11001000 0x1000>,
 679                                 <0x11002000 0x2000>,
 680                                 <0x11004000 0x2000>,
 681                                 <0x11006000 0x2000>;
 682                         interrupts = <GIC_PPI 9 0xf04>;
 683                 };
 684
 685                 mipi_phy: video-phy@105c0710 {
 686                         compatible = "samsung,exynos5433-mipi-video-phy";
 687                         #phy-cells = <1>;
 688                         samsung,pmu-syscon = <&pmu_system_controller>;
 689                         samsung,cam0-sysreg = <&syscon_cam0>;
 690                         samsung,cam1-sysreg = <&syscon_cam1>;
 691                         samsung,disp-sysreg = <&syscon_disp>;
 692                 };
 693
 694                 decon: decon@13800000 {
 695                         compatible = "samsung,exynos5433-decon";
 696                         reg = <0x13800000 0x2104>;
 697                         clocks = <&cmu_disp CLK_PCLK_DECON>,
 698                                 <&cmu_disp CLK_ACLK_DECON>,
 699                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 700                                 <&cmu_disp CLK_ACLK_XIU_DECON0X>,
 701                                 <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 702                                 <&cmu_disp CLK_SCLK_DECON_VCLK>,
 703                                 <&cmu_disp CLK_SCLK_DECON_ECLK>;
 704                         clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 705                                 "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 706                                 "sclk_decon_vclk", "sclk_decon_eclk";
 707                         interrupt-names = "fifo", "vsync", "lcd_sys";
 708                         interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 711                         samsung,disp-sysreg = <&syscon_disp>;
 712                         status = "disabled";
 713                         iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
 714                         iommu-names = "m0", "m1";
 715
 716                         ports {
 717                                 #address-cells = <1>;
 718                                 #size-cells = <0>;
 719
 720                                 port@0 {
 721                                         reg = <0>;
 722                                         decon_to_mic: endpoint {
 723                                                 remote-endpoint =
 724                                                         <&mic_to_decon>;
 725                                         };
 726                                 };
 727                         };
 728                 };
 729
 730                 dsi: dsi@13900000 {
 731                         compatible = "samsung,exynos5433-mipi-dsi";
 732                         reg = <0x13900000 0xC0>;
 733                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 734                         phys = <&mipi_phy 1>;
 735                         phy-names = "dsim";
 736                         clocks = <&cmu_disp CLK_PCLK_DSIM0>,
 737                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
 738                                 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
 739                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
 740                                 <&cmu_disp CLK_SCLK_DSIM0>;
 741                         clock-names = "bus_clk",
 742                                         "phyclk_mipidphy0_bitclkdiv8",
 743                                         "phyclk_mipidphy0_rxclkesc0",
 744                                         "sclk_rgb_vclk_to_dsim0",
 745                                         "sclk_mipi";
 746                         status = "disabled";
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749
 750                         ports {
 751                                 #address-cells = <1>;
 752                                 #size-cells = <0>;
 753
 754                                 port@0 {
 755                                         reg = <0>;
 756                                         dsi_to_mic: endpoint {
 757                                                 remote-endpoint = <&mic_to_dsi>;
 758                                         };
 759                                 };
 760                         };
 761                 };
 762
 763                 mic: mic@13930000 {
 764                         compatible = "samsung,exynos5433-mic";
 765                         reg = <0x13930000 0x48>;
 766                         clocks = <&cmu_disp CLK_PCLK_MIC0>,
 767                                 <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
 768                         clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
 769                         samsung,disp-syscon = <&syscon_disp>;
 770                         status = "disabled";
 771
 772                         ports {
 773                                 #address-cells = <1>;
 774                                 #size-cells = <0>;
 775
 776                                 port@0 {
 777                                         reg = <0>;
 778                                         mic_to_decon: endpoint {
 779                                                 remote-endpoint =
 780                                                         <&decon_to_mic>;
 781                                         };
 782                                 };
 783
 784                                 port@1 {
 785                                         reg = <1>;
 786                                         mic_to_dsi: endpoint {
 787                                                 remote-endpoint = <&dsi_to_mic>;
 788                                         };
 789                                 };
 790                         };
 791                 };
 792
 793                 syscon_disp: syscon@13b80000 {
 794                         compatible = "syscon";
 795                         reg = <0x13b80000 0x1010>;
 796                 };
 797
 798                 syscon_cam0: syscon@120f0000 {
 799                         compatible = "syscon";
 800                         reg = <0x120f0000 0x1020>;
 801                 };
 802
 803                 syscon_cam1: syscon@145f0000 {
 804                         compatible = "syscon";
 805                         reg = <0x145f0000 0x1038>;
 806                 };
 807
 808                 gsc_0: video-scaler@13C00000 {
 809                         compatible = "samsung,exynos5433-gsc";
 810                         reg = <0x13c00000 0x1000>;
 811                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 812                         clock-names = "pclk", "aclk", "aclk_xiu",
 813                                       "aclk_gsclbend";
 814                         clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
 815                                  <&cmu_gscl CLK_ACLK_GSCL0>,
 816                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 817                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 818                         iommus = <&sysmmu_gscl0>;
 819                 };
 820
 821                 gsc_1: video-scaler@13C10000 {
 822                         compatible = "samsung,exynos5433-gsc";
 823                         reg = <0x13c10000 0x1000>;
 824                         interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
 825                         clock-names = "pclk", "aclk", "aclk_xiu",
 826                                       "aclk_gsclbend";
 827                         clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
 828                                  <&cmu_gscl CLK_ACLK_GSCL1>,
 829                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 830                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 831                         iommus = <&sysmmu_gscl1>;
 832                 };
 833
 834                 gsc_2: video-scaler@13C20000 {
 835                         compatible = "samsung,exynos5433-gsc";
 836                         reg = <0x13c20000 0x1000>;
 837                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 838                         clock-names = "pclk", "aclk", "aclk_xiu",
 839                                       "aclk_gsclbend";
 840                         clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
 841                                  <&cmu_gscl CLK_ACLK_GSCL2>,
 842                                  <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 843                                  <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 844                         iommus = <&sysmmu_gscl2>;
 845                 };
 846
 847                 jpeg: codec@15020000 {
 848                         compatible = "samsung,exynos5433-jpeg";
 849                         reg = <0x15020000 0x10000>;
 850                         interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
 851                         clock-names = "pclk", "aclk", "aclk_xiu", "sclk";
 852                         clocks = <&cmu_mscl CLK_PCLK_JPEG>,
 853                                  <&cmu_mscl CLK_ACLK_JPEG>,
 854                                  <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
 855                                  <&cmu_mscl CLK_SCLK_JPEG>;
 856                         iommus = <&sysmmu_jpeg>;
 857                 };
 858
 859                 mfc: codec@152E0000 {
 860                         compatible = "samsung,exynos5433-mfc";
 861                         reg = <0x152E0000 0x10000>;
 862                         interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 863                         clock-names = "pclk", "aclk", "aclk_xiu";
 864                         clocks = <&cmu_mfc CLK_PCLK_MFC>,
 865                                  <&cmu_mfc CLK_ACLK_MFC>,
 866                                  <&cmu_mfc CLK_ACLK_XIU_MFCX>;
 867                         iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
 868                         iommu-names = "left", "right";
 869                 };
 870
 871                 sysmmu_decon0x: sysmmu@0x13a00000 {
 872                         compatible = "samsung,exynos-sysmmu";
 873                         reg = <0x13a00000 0x1000>;
 874                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 875                         clock-names = "pclk", "aclk";
 876                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 877                                 <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
 878                         #iommu-cells = <0>;
 879                 };
 880
 881                 sysmmu_decon1x: sysmmu@0x13a10000 {
 882                         compatible = "samsung,exynos-sysmmu";
 883                         reg = <0x13a10000 0x1000>;
 884                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
 885                         clock-names = "pclk", "aclk";
 886                         clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 887                                 <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
 888                         #iommu-cells = <0>;
 889                 };
 890
 891                 sysmmu_gscl0: sysmmu@0x13C80000 {
 892                         compatible = "samsung,exynos-sysmmu";
 893                         reg = <0x13C80000 0x1000>;
 894                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 895                         clock-names = "aclk", "pclk";
 896                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
 897                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
 898                         #iommu-cells = <0>;
 899                 };
 900
 901                 sysmmu_gscl1: sysmmu@0x13C90000 {
 902                         compatible = "samsung,exynos-sysmmu";
 903                         reg = <0x13C90000 0x1000>;
 904                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 905                         clock-names = "aclk", "pclk";
 906                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
 907                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
 908                         #iommu-cells = <0>;
 909                 };
 910
 911                 sysmmu_gscl2: sysmmu@0x13CA0000 {
 912                         compatible = "samsung,exynos-sysmmu";
 913                         reg = <0x13CA0000 0x1000>;
 914                         interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
 915                         clock-names = "aclk", "pclk";
 916                         clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
 917                                  <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
 918                         #iommu-cells = <0>;
 919                 };
 920
 921                 sysmmu_jpeg: sysmmu@0x15060000 {
 922                         compatible = "samsung,exynos-sysmmu";
 923                         reg = <0x15060000 0x1000>;
 924                         interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 925                         clock-names = "pclk", "aclk";
 926                         clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
 927                                  <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
 928                         #iommu-cells = <0>;
 929                 };
 930
 931                 sysmmu_mfc_0: sysmmu@0x15200000 {
 932                         compatible = "samsung,exynos-sysmmu";
 933                         reg = <0x15200000 0x1000>;
 934                         interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
 935                         clock-names = "pclk", "aclk";
 936                         clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
 937                                  <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
 938                         #iommu-cells = <0>;
 939                 };
 940
 941                 sysmmu_mfc_1: sysmmu@0x15210000 {
 942                         compatible = "samsung,exynos-sysmmu";
 943                         reg = <0x15210000 0x1000>;
 944                         interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 945                         clock-names = "pclk", "aclk";
 946                         clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
 947                                  <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
 948                         #iommu-cells = <0>;
 949                 };
 950
 951                 serial_0: serial@14c10000 {
 952                         compatible = "samsung,exynos5433-uart";
 953                         reg = <0x14c10000 0x100>;
 954                         interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 955                         clocks = <&cmu_peric CLK_PCLK_UART0>,
 956                                 <&cmu_peric CLK_SCLK_UART0>;
 957                         clock-names = "uart", "clk_uart_baud0";
 958                         pinctrl-names = "default";
 959                         pinctrl-0 = <&uart0_bus>;
 960                         status = "disabled";
 961                 };
 962
 963                 serial_1: serial@14c20000 {
 964                         compatible = "samsung,exynos5433-uart";
 965                         reg = <0x14c20000 0x100>;
 966                         interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
 967                         clocks = <&cmu_peric CLK_PCLK_UART1>,
 968                                 <&cmu_peric CLK_SCLK_UART1>;
 969                         clock-names = "uart", "clk_uart_baud0";
 970                         pinctrl-names = "default";
 971                         pinctrl-0 = <&uart1_bus>;
 972                         status = "disabled";
 973                 };
 974
 975                 serial_2: serial@14c30000 {
 976                         compatible = "samsung,exynos5433-uart";
 977                         reg = <0x14c30000 0x100>;
 978                         interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
 979                         clocks = <&cmu_peric CLK_PCLK_UART2>,
 980                                 <&cmu_peric CLK_SCLK_UART2>;
 981                         clock-names = "uart", "clk_uart_baud0";
 982                         pinctrl-names = "default";
 983                         pinctrl-0 = <&uart2_bus>;
 984                         status = "disabled";
 985                 };
 986
 987                 spi_0: spi@14d20000 {
 988                         compatible = "samsung,exynos5433-spi";
 989                         reg = <0x14d20000 0x100>;
 990                         interrupts = <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
 991                         dmas = <&pdma0 9>, <&pdma0 8>;
 992                         dma-names = "tx", "rx";
 993                         #address-cells = <1>;
 994                         #size-cells = <0>;
 995                         clocks = <&cmu_peric CLK_PCLK_SPI0>,
 996                                 <&cmu_peric CLK_SCLK_SPI0>,
 997                                 <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
 998                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
 999                         samsung,spi-src-clk = <0>;
1000                         pinctrl-names = "default";
1001                         pinctrl-0 = <&spi0_bus>;
1002                         num-cs = <1>;
1003                         status = "disabled";
1004                 };
1005
1006                 spi_1: spi@14d30000 {
1007                         compatible = "samsung,exynos5433-spi";
1008                         reg = <0x14d30000 0x100>;
1009                         interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
1010                         dmas = <&pdma0 11>, <&pdma0 10>;
1011                         dma-names = "tx", "rx";
1012                         #address-cells = <1>;
1013                         #size-cells = <0>;
1014                         clocks = <&cmu_peric CLK_PCLK_SPI1>,
1015                                 <&cmu_peric CLK_SCLK_SPI1>,
1016                                 <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
1017                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1018                         samsung,spi-src-clk = <0>;
1019                         pinctrl-names = "default";
1020                         pinctrl-0 = <&spi1_bus>;
1021                         num-cs = <1>;
1022                         status = "disabled";
1023                 };
1024
1025                 spi_2: spi@14d40000 {
1026                         compatible = "samsung,exynos5433-spi";
1027                         reg = <0x14d40000 0x100>;
1028                         interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>;
1029                         dmas = <&pdma0 13>, <&pdma0 12>;
1030                         dma-names = "tx", "rx";
1031                         #address-cells = <1>;
1032                         #size-cells = <0>;
1033                         clocks = <&cmu_peric CLK_PCLK_SPI2>,
1034                                 <&cmu_peric CLK_SCLK_SPI2>,
1035                                 <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
1036                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1037                         samsung,spi-src-clk = <0>;
1038                         pinctrl-names = "default";
1039                         pinctrl-0 = <&spi2_bus>;
1040                         num-cs = <1>;
1041                         status = "disabled";
1042                 };
1043
1044                 spi_3: spi@14d50000 {
1045                         compatible = "samsung,exynos5433-spi";
1046                         reg = <0x14d50000 0x100>;
1047                         interrupts = <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>;
1048                         dmas = <&pdma0 23>, <&pdma0 22>;
1049                         dma-names = "tx", "rx";
1050                         #address-cells = <1>;
1051                         #size-cells = <0>;
1052                         clocks = <&cmu_peric CLK_PCLK_SPI3>,
1053                                 <&cmu_peric CLK_SCLK_SPI3>,
1054                                 <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
1055                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1056                         samsung,spi-src-clk = <0>;
1057                         pinctrl-names = "default";
1058                         pinctrl-0 = <&spi3_bus>;
1059                         num-cs = <1>;
1060                         status = "disabled";
1061                 };
1062
1063                 spi_4: spi@14d00000 {
1064                         compatible = "samsung,exynos5433-spi";
1065                         reg = <0x14d00000 0x100>;
1066                         interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1067                         dmas = <&pdma0 25>, <&pdma0 24>;
1068                         dma-names = "tx", "rx";
1069                         #address-cells = <1>;
1070                         #size-cells = <0>;
1071                         clocks = <&cmu_peric CLK_PCLK_SPI4>,
1072                                 <&cmu_peric CLK_SCLK_SPI4>,
1073                                 <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
1074                         clock-names = "spi", "spi_busclk0", "spi_ioclk";
1075                         samsung,spi-src-clk = <0>;
1076                         pinctrl-names = "default";
1077                         pinctrl-0 = <&spi4_bus>;
1078                         num-cs = <1>;
1079                         status = "disabled";
1080                 };
1081
1082                 adc: adc@14d10000 {
1083                         compatible = "samsung,exynos7-adc";
1084                         reg = <0x14d10000 0x100>;
1085                         interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
1086                         clock-names = "adc";
1087                         clocks = <&cmu_peric CLK_PCLK_ADCIF>;
1088                         #io-channel-cells = <1>;
1089                         io-channel-ranges;
1090                         status = "disabled";
1091                 };
1092
1093                 pwm: pwm@14dd0000 {
1094                         compatible = "samsung,exynos4210-pwm";
1095                         reg = <0x14dd0000 0x100>;
1096                         interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
1097                                      <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
1098                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
1099                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
1100                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
1101                         samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1102                         clocks = <&cmu_peric CLK_PCLK_PWM>;
1103                         clock-names = "timers";
1104                         #pwm-cells = <3>;
1105                         status = "disabled";
1106                 };
1107
1108                 hsi2c_0: hsi2c@14e40000 {
1109                         compatible = "samsung,exynos7-hsi2c";
1110                         reg = <0x14e40000 0x1000>;
1111                         interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
1112                         #address-cells = <1>;
1113                         #size-cells = <0>;
1114                         pinctrl-names = "default";
1115                         pinctrl-0 = <&hs_i2c0_bus>;
1116                         clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
1117                         clock-names = "hsi2c";
1118                         status = "disabled";
1119                 };
1120
1121                 hsi2c_1: hsi2c@14e50000 {
1122                         compatible = "samsung,exynos7-hsi2c";
1123                         reg = <0x14e50000 0x1000>;
1124                         interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
1125                         #address-cells = <1>;
1126                         #size-cells = <0>;
1127                         pinctrl-names = "default";
1128                         pinctrl-0 = <&hs_i2c1_bus>;
1129                         clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
1130                         clock-names = "hsi2c";
1131                         status = "disabled";
1132                 };
1133
1134                 hsi2c_2: hsi2c@14e60000 {
1135                         compatible = "samsung,exynos7-hsi2c";
1136                         reg = <0x14e60000 0x1000>;
1137                         interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
1138                         #address-cells = <1>;
1139                         #size-cells = <0>;
1140                         pinctrl-names = "default";
1141                         pinctrl-0 = <&hs_i2c2_bus>;
1142                         clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
1143                         clock-names = "hsi2c";
1144                         status = "disabled";
1145                 };
1146
1147                 hsi2c_3: hsi2c@14e70000 {
1148                         compatible = "samsung,exynos7-hsi2c";
1149                         reg = <0x14e70000 0x1000>;
1150                         interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>;
1151                         #address-cells = <1>;
1152                         #size-cells = <0>;
1153                         pinctrl-names = "default";
1154                         pinctrl-0 = <&hs_i2c3_bus>;
1155                         clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
1156                         clock-names = "hsi2c";
1157                         status = "disabled";
1158                 };
1159
1160                 hsi2c_4: hsi2c@14ec0000 {
1161                         compatible = "samsung,exynos7-hsi2c";
1162                         reg = <0x14ec0000 0x1000>;
1163                         interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
1164                         #address-cells = <1>;
1165                         #size-cells = <0>;
1166                         pinctrl-names = "default";
1167                         pinctrl-0 = <&hs_i2c4_bus>;
1168                         clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
1169                         clock-names = "hsi2c";
1170                         status = "disabled";
1171                 };
1172
1173                 hsi2c_5: hsi2c@14ed0000 {
1174                         compatible = "samsung,exynos7-hsi2c";
1175                         reg = <0x14ed0000 0x1000>;
1176                         interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
1177                         #address-cells = <1>;
1178                         #size-cells = <0>;
1179                         pinctrl-names = "default";
1180                         pinctrl-0 = <&hs_i2c5_bus>;
1181                         clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
1182                         clock-names = "hsi2c";
1183                         status = "disabled";
1184                 };
1185
1186                 hsi2c_6: hsi2c@14ee0000 {
1187                         compatible = "samsung,exynos7-hsi2c";
1188                         reg = <0x14ee0000 0x1000>;
1189                         interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
1190                         #address-cells = <1>;
1191                         #size-cells = <0>;
1192                         pinctrl-names = "default";
1193                         pinctrl-0 = <&hs_i2c6_bus>;
1194                         clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
1195                         clock-names = "hsi2c";
1196                         status = "disabled";
1197                 };
1198
1199                 hsi2c_7: hsi2c@14ef0000 {
1200                         compatible = "samsung,exynos7-hsi2c";
1201                         reg = <0x14ef0000 0x1000>;
1202                         interrupts = <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>;
1203                         #address-cells = <1>;
1204                         #size-cells = <0>;
1205                         pinctrl-names = "default";
1206                         pinctrl-0 = <&hs_i2c7_bus>;
1207                         clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
1208                         clock-names = "hsi2c";
1209                         status = "disabled";
1210                 };
1211
1212                 hsi2c_8: hsi2c@14d90000 {
1213                         compatible = "samsung,exynos7-hsi2c";
1214                         reg = <0x14d90000 0x1000>;
1215                         interrupts = <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
1216                         #address-cells = <1>;
1217                         #size-cells = <0>;
1218                         pinctrl-names = "default";
1219                         pinctrl-0 = <&hs_i2c8_bus>;
1220                         clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
1221                         clock-names = "hsi2c";
1222                         status = "disabled";
1223                 };
1224
1225                 hsi2c_9: hsi2c@14da0000 {
1226                         compatible = "samsung,exynos7-hsi2c";
1227                         reg = <0x14da0000 0x1000>;
1228                         interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1229                         #address-cells = <1>;
1230                         #size-cells = <0>;
1231                         pinctrl-names = "default";
1232                         pinctrl-0 = <&hs_i2c9_bus>;
1233                         clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
1234                         clock-names = "hsi2c";
1235                         status = "disabled";
1236                 };
1237
1238                 hsi2c_10: hsi2c@14de0000 {
1239                         compatible = "samsung,exynos7-hsi2c";
1240                         reg = <0x14de0000 0x1000>;
1241                         interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
1242                         #address-cells = <1>;
1243                         #size-cells = <0>;
1244                         pinctrl-names = "default";
1245                         pinctrl-0 = <&hs_i2c10_bus>;
1246                         clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
1247                         clock-names = "hsi2c";
1248                         status = "disabled";
1249                 };
1250
1251                 hsi2c_11: hsi2c@14df0000 {
1252                         compatible = "samsung,exynos7-hsi2c";
1253                         reg = <0x14df0000 0x1000>;
1254                         interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
1255                         #address-cells = <1>;
1256                         #size-cells = <0>;
1257                         pinctrl-names = "default";
1258                         pinctrl-0 = <&hs_i2c11_bus>;
1259                         clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
1260                         clock-names = "hsi2c";
1261                         status = "disabled";
1262                 };
1263
1264                 usbdrd30: usb@15400000  {
1265                         compatible = "samsung,exynos5250-dwusb3";
1266                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
1267                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1268                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
1269                         #address-cells = <1>;
1270                         #size-cells = <1>;
1271                         ranges;
1272                         status = "disabled";
1273
1274                         dwc3@15400000 {
1275                                 compatible = "snps,dwc3";
1276                                 reg = <0x15400000 0x10000>;
1277                                 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1278                                 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1279                                 phy-names = "usb2-phy", "usb3-phy";
1280                         };
1281                 };
1282
1283                 usbdrd30_phy: phy@15500000 {
1284                         compatible = "samsung,exynos5433-usbdrd-phy";
1285                         reg = <0x15500000 0x100>;
1286                         clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
1287                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
1288                                 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
1289                                 <&cmu_fsys CLK_SCLK_USBDRD30>;
1290                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1291                                         "itp";
1292                         #phy-cells = <1>;
1293                         samsung,pmu-syscon = <&pmu_system_controller>;
1294                         status = "disabled";
1295                 };
1296
1297                 usbhost30_phy: phy@15580000 {
1298                         compatible = "samsung,exynos5433-usbdrd-phy";
1299                         reg = <0x15580000 0x100>;
1300                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
1301                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
1302                                 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
1303                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1304                         clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
1305                                         "itp";
1306                         #phy-cells = <1>;
1307                         samsung,pmu-syscon = <&pmu_system_controller>;
1308                         status = "disabled";
1309                 };
1310
1311                 usbhost30: usb@15a00000 {
1312                         compatible = "samsung,exynos5250-dwusb3";
1313                         clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
1314                                 <&cmu_fsys CLK_SCLK_USBHOST30>;
1315                         clock-names = "usbdrd30", "usbdrd30_susp_clk";
1316                         #address-cells = <1>;
1317                         #size-cells = <1>;
1318                         ranges;
1319                         status = "disabled";
1320
1321                         usbdrd_dwc3_0: dwc3@15a00000 {
1322                                 compatible = "snps,dwc3";
1323                                 reg = <0x15a00000 0x10000>;
1324                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1325                                 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1326                                 phy-names = "usb2-phy", "usb3-phy";
1327                         };
1328                 };
1329
1330                 mshc_0: mshc@15540000 {
1331                         compatible = "samsung,exynos7-dw-mshc-smu";
1332                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1333                         #address-cells = <1>;
1334                         #size-cells = <0>;
1335                         reg = <0x15540000 0x2000>;
1336                         clocks = <&cmu_fsys CLK_ACLK_MMC0>,
1337                                 <&cmu_fsys CLK_SCLK_MMC0>;
1338                         clock-names = "biu", "ciu";
1339                         fifo-depth = <0x40>;
1340                         status = "disabled";
1341                 };
1342
1343                 mshc_1: mshc@15550000 {
1344                         compatible = "samsung,exynos7-dw-mshc-smu";
1345                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1346                         #address-cells = <1>;
1347                         #size-cells = <0>;
1348                         reg = <0x15550000 0x2000>;
1349                         clocks = <&cmu_fsys CLK_ACLK_MMC1>,
1350                                 <&cmu_fsys CLK_SCLK_MMC1>;
1351                         clock-names = "biu", "ciu";
1352                         fifo-depth = <0x40>;
1353                         status = "disabled";
1354                 };
1355
1356                 mshc_2: mshc@15560000 {
1357                         compatible = "samsung,exynos7-dw-mshc-smu";
1358                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
1359                         #address-cells = <1>;
1360                         #size-cells = <0>;
1361                         reg = <0x15560000 0x2000>;
1362                         clocks = <&cmu_fsys CLK_ACLK_MMC2>,
1363                                 <&cmu_fsys CLK_SCLK_MMC2>;
1364                         clock-names = "biu", "ciu";
1365                         fifo-depth = <0x40>;
1366                         status = "disabled";
1367                 };
1368
1369                 amba {
1370                         compatible = "simple-bus";
1371                         #address-cells = <1>;
1372                         #size-cells = <1>;
1373                         ranges;
1374
1375                         pdma0: pdma@15610000 {
1376                                 compatible = "arm,pl330", "arm,primecell";
1377                                 reg = <0x15610000 0x1000>;
1378                                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
1379                                 clocks = <&cmu_fsys CLK_PDMA0>;
1380                                 clock-names = "apb_pclk";
1381                                 #dma-cells = <1>;
1382                                 #dma-channels = <8>;
1383                                 #dma-requests = <32>;
1384                         };
1385
1386                         pdma1: pdma@15600000 {
1387                                 compatible = "arm,pl330", "arm,primecell";
1388                                 reg = <0x15600000 0x1000>;
1389                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1390                                 clocks = <&cmu_fsys CLK_PDMA1>;
1391                                 clock-names = "apb_pclk";
1392                                 #dma-cells = <1>;
1393                                 #dma-channels = <8>;
1394                                 #dma-requests = <32>;
1395                         };
1396                 };
1397
1398                 audio-subsystem@11400000 {
1399                         compatible = "samsung,exynos5433-lpass";
1400                         reg = <0x11400000 0x100>, <0x11500000 0x08>;
1401                         samsung,pmu-syscon = <&pmu_system_controller>;
1402                         #address-cells = <1>;
1403                         #size-cells = <1>;
1404                         ranges;
1405
1406                         adma: adma@11420000 {
1407                                 compatible = "arm,pl330", "arm,primecell";
1408                                 reg = <0x11420000 0x1000>;
1409                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1410                                 clocks = <&cmu_aud CLK_ACLK_DMAC>;
1411                                 clock-names = "apb_pclk";
1412                                 #dma-cells = <1>;
1413                                 #dma-channels = <8>;
1414                                 #dma-requests = <32>;
1415                         };
1416
1417                         i2s0: i2s0@11440000 {
1418                                 compatible = "samsung,exynos7-i2s";
1419                                 reg = <0x11440000 0x100>;
1420                                 dmas = <&adma 0 &adma 2>;
1421                                 dma-names = "tx", "rx";
1422                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1423                                 #address-cells = <1>;
1424                                 #size-cells = <0>;
1425                                 clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
1426                                         <&cmu_aud CLK_SCLK_AUD_I2S>,
1427                                         <&cmu_aud CLK_SCLK_I2S_BCLK>;
1428                                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
1429                                 pinctrl-names = "default";
1430                                 pinctrl-0 = <&i2s0_bus>;
1431                                 status = "disabled";
1432                         };
1433
1434                         serial_3: serial@11460000 {
1435                                 compatible = "samsung,exynos5433-uart";
1436                                 reg = <0x11460000 0x100>;
1437                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1438                                 clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
1439                                         <&cmu_aud CLK_SCLK_AUD_UART>;
1440                                 clock-names = "uart", "clk_uart_baud0";
1441                                 pinctrl-names = "default";
1442                                 pinctrl-0 = <&uart_aud_bus>;
1443                                 status = "disabled";
1444                         };
1445                 };
1446         };
1447
1448         timer: timer {
1449                 compatible = "arm,armv8-timer";
1450                 interrupts = <GIC_PPI 13
1451                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1452                         <GIC_PPI 14
1453                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1454                         <GIC_PPI 11
1455                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
1456                         <GIC_PPI 10
1457                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1458         };
1459 };
1460
1461 #include "exynos5433-pinctrl.dtsi"
1462 #include "exynos5433-tmu.dtsi"