arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34
  35 / {
  36         compatible = "brcm,stingray";
  37         interrupt-parent = <&gic>;
  38         #address-cells = <2>;
  39         #size-cells = <2>;
  40
  41         cpus {
  42                 #address-cells = <2>;
  43                 #size-cells = <0>;
  44
  45                 cpu@000 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a72", "arm,armv8";
  48                         reg = <0x0 0x0>;
  49                         enable-method = "psci";
  50                         next-level-cache = <&CLUSTER0_L2>;
  51                 };
  52
  53                 cpu@001 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a72", "arm,armv8";
  56                         reg = <0x0 0x1>;
  57                         enable-method = "psci";
  58                         next-level-cache = <&CLUSTER0_L2>;
  59                 };
  60
  61                 cpu@100 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a72", "arm,armv8";
  64                         reg = <0x0 0x100>;
  65                         enable-method = "psci";
  66                         next-level-cache = <&CLUSTER1_L2>;
  67                 };
  68
  69                 cpu@101 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a72", "arm,armv8";
  72                         reg = <0x0 0x101>;
  73                         enable-method = "psci";
  74                         next-level-cache = <&CLUSTER1_L2>;
  75                 };
  76
  77                 cpu@200 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a72", "arm,armv8";
  80                         reg = <0x0 0x200>;
  81                         enable-method = "psci";
  82                         next-level-cache = <&CLUSTER2_L2>;
  83                 };
  84
  85                 cpu@201 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a72", "arm,armv8";
  88                         reg = <0x0 0x201>;
  89                         enable-method = "psci";
  90                         next-level-cache = <&CLUSTER2_L2>;
  91                 };
  92
  93                 cpu@300 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a72", "arm,armv8";
  96                         reg = <0x0 0x300>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&CLUSTER3_L2>;
  99                 };
 100
 101                 cpu@301 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a72", "arm,armv8";
 104                         reg = <0x0 0x301>;
 105                         enable-method = "psci";
 106                         next-level-cache = <&CLUSTER3_L2>;
 107                 };
 108
 109                 CLUSTER0_L2: l2-cache@000 {
 110                         compatible = "cache";
 111                 };
 112
 113                 CLUSTER1_L2: l2-cache@100 {
 114                         compatible = "cache";
 115                 };
 116
 117                 CLUSTER2_L2: l2-cache@200 {
 118                         compatible = "cache";
 119                 };
 120
 121                 CLUSTER3_L2: l2-cache@300 {
 122                         compatible = "cache";
 123                 };
 124         };
 125
 126         memory: memory@80000000 {
 127                 device_type = "memory";
 128                 reg = <0x00000000 0x80000000 0 0x40000000>;
 129         };
 130
 131         psci {
 132                 compatible = "arm,psci-0.2";
 133                 method = "smc";
 134         };
 135
 136         pmu {
 137                 compatible = "arm,armv8-pmuv3";
 138                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 139         };
 140
 141         timer {
 142                 compatible = "arm,armv8-timer";
 143                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 144                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 145                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 146                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 147         };
 148
 149         scr {
 150                 compatible = "simple-bus";
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 ranges = <0x0 0x0 0x61000000 0x05000000>;
 154
 155                 gic: interrupt-controller@02c00000 {
 156                         compatible = "arm,gic-v3";
 157                         #interrupt-cells = <3>;
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         ranges;
 161                         interrupt-controller;
 162                         reg = <0x02c00000 0x010000>, /* GICD */
 163                               <0x02e00000 0x600000>; /* GICR */
 164                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 165
 166                         gic_its: gic-its@63c20000 {
 167                                 compatible = "arm,gic-v3-its";
 168                                 msi-controller;
 169                                 #msi-cells = <1>;
 170                                 reg = <0x02c20000 0x10000>;
 171                         };
 172                 };
 173
 174                 smmu: mmu@03000000 {
 175                         compatible = "arm,mmu-500";
 176                         reg = <0x03000000 0x80000>;
 177                         #global-interrupts = <1>;
 178                         interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
 181                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
 184                                      <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
 186                                      <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
 187                                      <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
 189                                      <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
 190                                      <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
 197                                      <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
 207                                      <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
 208                                      <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
 209                                      <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
 210                                      <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
 218                                      <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
 236                                      <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
 237                                      <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
 239                                      <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
 240                                      <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
 241                                      <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
 242                                      <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
 243                         #iommu-cells = <2>;
 244                 };
 245         };
 246
 247         crmu: crmu {
 248                 compatible = "simple-bus";
 249                 #address-cells = <1>;
 250                 #size-cells = <1>;
 251                 ranges = <0x0 0x0 0x66400000 0x100000>;
 252
 253                 #include "stingray-clock.dtsi"
 254
 255                 gpio_crmu: gpio@00024800 {
 256                         compatible = "brcm,iproc-gpio";
 257                         reg = <0x00024800 0x4c>;
 258                         ngpios = <6>;
 259                         #gpio-cells = <2>;
 260                         gpio-controller;
 261                 };
 262         };
 263
 264         hsls {
 265                 compatible = "simple-bus";
 266                 #address-cells = <1>;
 267                 #size-cells = <1>;
 268                 ranges = <0x0 0x0 0x68900000 0x17700000>;
 269
 270                 #include "stingray-pinctrl.dtsi"
 271
 272                 pwm: pwm@00010000 {
 273                         compatible = "brcm,iproc-pwm";
 274                         reg = <0x00010000 0x1000>;
 275                         clocks = <&crmu_ref25m>;
 276                         #pwm-cells = <3>;
 277                         status = "disabled";
 278                 };
 279
 280                 i2c0: i2c@000b0000 {
 281                         compatible = "brcm,iproc-i2c";
 282                         reg = <0x000b0000 0x100>;
 283                         #address-cells = <1>;
 284                         #size-cells = <0>;
 285                         interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
 286                         clock-frequency = <100000>;
 287                         status = "disabled";
 288                 };
 289
 290                 wdt0: watchdog@000c0000 {
 291                         compatible = "arm,sp805", "arm,primecell";
 292                         reg = <0x000c0000 0x1000>;
 293                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
 295                         clock-names = "wdogclk", "apb_pclk";
 296                 };
 297
 298                 gpio_hsls: gpio@000d0000 {
 299                         compatible = "brcm,iproc-gpio";
 300                         reg = <0x000d0000 0x864>;
 301                         ngpios = <151>;
 302                         #gpio-cells = <2>;
 303                         gpio-controller;
 304                         interrupt-controller;
 305                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 306                         gpio-ranges = <&pinmux 0 0 16>,
 307                                         <&pinmux 16 71 2>,
 308                                         <&pinmux 18 131 8>,
 309                                         <&pinmux 26 83 6>,
 310                                         <&pinmux 32 123 4>,
 311                                         <&pinmux 36 43 24>,
 312                                         <&pinmux 60 89 2>,
 313                                         <&pinmux 62 73 4>,
 314                                         <&pinmux 66 95 28>,
 315                                         <&pinmux 94 127 4>,
 316                                         <&pinmux 98 139 10>,
 317                                         <&pinmux 108 16 27>,
 318                                         <&pinmux 135 77 6>,
 319                                         <&pinmux 141 67 4>,
 320                                         <&pinmux 145 149 6>,
 321                                         <&pinmux 151 91 4>;
 322                 };
 323
 324                 i2c1: i2c@000e0000 {
 325                         compatible = "brcm,iproc-i2c";
 326                         reg = <0x000e0000 0x100>;
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                         interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
 330                         clock-frequency = <100000>;
 331                         status = "disabled";
 332                 };
 333
 334                 uart0: uart@00100000 {
 335                         device_type = "serial";
 336                         compatible = "snps,dw-apb-uart";
 337                         reg = <0x00100000 0x1000>;
 338                         reg-shift = <2>;
 339                         clock-frequency = <25000000>;
 340                         interrupt-parent = <&gic>;
 341                         interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
 342                         status = "disabled";
 343                 };
 344
 345                 uart1: uart@00110000 {
 346                         device_type = "serial";
 347                         compatible = "snps,dw-apb-uart";
 348                         reg = <0x00110000 0x1000>;
 349                         reg-shift = <2>;
 350                         clock-frequency = <25000000>;
 351                         interrupt-parent = <&gic>;
 352                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 353                         status = "disabled";
 354                 };
 355
 356                 uart2: uart@00120000 {
 357                         device_type = "serial";
 358                         compatible = "snps,dw-apb-uart";
 359                         reg = <0x00120000 0x1000>;
 360                         reg-shift = <2>;
 361                         clock-frequency = <25000000>;
 362                         interrupt-parent = <&gic>;
 363                         interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
 364                         status = "disabled";
 365                 };
 366
 367                 uart3: uart@00130000 {
 368                         device_type = "serial";
 369                         compatible = "snps,dw-apb-uart";
 370                         reg = <0x00130000 0x1000>;
 371                         reg-shift = <2>;
 372                         clock-frequency = <25000000>;
 373                         interrupt-parent = <&gic>;
 374                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 375                         status = "disabled";
 376                 };
 377
 378                 ssp0: ssp@00180000 {
 379                         compatible = "arm,pl022", "arm,primecell";
 380                         reg = <0x00180000 0x1000>;
 381                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 382                         clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
 383                         clock-names = "spiclk", "apb_pclk";
 384                         num-cs = <1>;
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         status = "disabled";
 388                 };
 389
 390                 ssp1: ssp@00190000 {
 391                         compatible = "arm,pl022", "arm,primecell";
 392                         reg = <0x00190000 0x1000>;
 393                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 394                         clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
 395                         clock-names = "spiclk", "apb_pclk";
 396                         num-cs = <1>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         status = "disabled";
 400                 };
 401
 402                 hwrng: hwrng@00220000 {
 403                         compatible = "brcm,iproc-rng200";
 404                         reg = <0x00220000 0x28>;
 405                 };
 406
 407                 dma0: dma@00310000 {
 408                         compatible = "arm,pl330", "arm,primecell";
 409                         reg = <0x00310000 0x1000>;
 410                         interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 411                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 412                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 413                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 414                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 415                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 416                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 417                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 418                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
 419                         #dma-cells = <1>;
 420                         #dma-channels = <8>;
 421                         #dma-requests = <32>;
 422                         clocks = <&hsls_div2_clk>;
 423                         clock-names = "apb_pclk";
 424                         iommus = <&smmu 0x6000 0x0000>;
 425                 };
 426
 427                 nand: nand@00360000 {
 428                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 429                         reg = <0x00360000 0x600>,
 430                               <0x0050a408 0x600>,
 431                               <0x00360f00 0x20>;
 432                         reg-names = "nand", "iproc-idm", "iproc-ext";
 433                         interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         brcm,nand-has-wp;
 437                         status = "disabled";
 438                 };
 439
 440                 sdio0: sdhci@003f1000 {
 441                         compatible = "brcm,sdhci-iproc";
 442                         reg = <0x003f1000 0x100>;
 443                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
 444                         bus-width = <8>;
 445                         clocks = <&sdio0_clk>;
 446                         iommus = <&smmu 0x6002 0x0000>;
 447                         status = "disabled";
 448                 };
 449
 450                 sdio1: sdhci@003f2000 {
 451                         compatible = "brcm,sdhci-iproc";
 452                         reg = <0x003f2000 0x100>;
 453                         interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
 454                         bus-width = <8>;
 455                         clocks = <&sdio1_clk>;
 456                         iommus = <&smmu 0x6003 0x0000>;
 457                         status = "disabled";
 458                 };
 459         };
 460 };