4 * Copyright (c) 2015 Broadcom. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of Broadcom Corporation nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/clock/bcm-ns2.h>
37 compatible = "brcm,ns2";
38 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a57", "arm,armv8";
50 enable-method = "psci";
51 next-level-cache = <&CLUSTER0_L2>;
56 compatible = "arm,cortex-a57", "arm,armv8";
58 enable-method = "psci";
59 next-level-cache = <&CLUSTER0_L2>;
64 compatible = "arm,cortex-a57", "arm,armv8";
66 enable-method = "psci";
67 next-level-cache = <&CLUSTER0_L2>;
72 compatible = "arm,cortex-a57", "arm,armv8";
74 enable-method = "psci";
75 next-level-cache = <&CLUSTER0_L2>;
78 CLUSTER0_L2: l2-cache@000 {
84 compatible = "arm,psci-1.0";
89 compatible = "arm,armv8-timer";
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
91 IRQ_TYPE_EDGE_RISING)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
93 IRQ_TYPE_EDGE_RISING)>,
94 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
95 IRQ_TYPE_EDGE_RISING)>,
96 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
97 IRQ_TYPE_EDGE_RISING)>;
101 compatible = "arm,armv8-pmuv3";
102 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-affinity = <&A57_0>,
112 pcie0: pcie@20020000 {
113 compatible = "brcm,iproc-pcie";
114 reg = <0 0x20020000 0 0x1000>;
116 #interrupt-cells = <1>;
117 interrupt-map-mask = <0 0 0 0>;
118 interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
120 linux,pci-domain = <0>;
122 bus-range = <0x00 0xff>;
124 #address-cells = <3>;
127 ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
130 brcm,pcie-ob-oarr-size;
131 brcm,pcie-ob-axi-offset = <0x00000000>;
132 brcm,pcie-ob-window-size = <256>;
136 msi-parent = <&msi0>;
138 compatible = "brcm,iproc-msi";
140 interrupt-parent = <&gic>;
141 interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
142 <GIC_SPI 278 IRQ_TYPE_NONE>,
143 <GIC_SPI 279 IRQ_TYPE_NONE>,
144 <GIC_SPI 280 IRQ_TYPE_NONE>;
145 brcm,num-eq-region = <1>;
146 brcm,num-msi-msg-region = <1>;
150 pcie4: pcie@50020000 {
151 compatible = "brcm,iproc-pcie";
152 reg = <0 0x50020000 0 0x1000>;
154 #interrupt-cells = <1>;
155 interrupt-map-mask = <0 0 0 0>;
156 interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
158 linux,pci-domain = <4>;
160 bus-range = <0x00 0xff>;
162 #address-cells = <3>;
165 ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
168 brcm,pcie-ob-oarr-size;
169 brcm,pcie-ob-axi-offset = <0x30000000>;
170 brcm,pcie-ob-window-size = <256>;
174 msi-parent = <&msi4>;
176 compatible = "brcm,iproc-msi";
178 interrupt-parent = <&gic>;
179 interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
180 <GIC_SPI 302 IRQ_TYPE_NONE>,
181 <GIC_SPI 303 IRQ_TYPE_NONE>,
182 <GIC_SPI 304 IRQ_TYPE_NONE>;
187 compatible = "simple-bus";
188 #address-cells = <1>;
190 ranges = <0 0 0 0xffffffff>;
192 #include "ns2-clock.dtsi"
195 compatible = "arm,pl330", "arm,primecell";
196 reg = <0x61360000 0x1000>;
197 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
208 #dma-requests = <32>;
209 clocks = <&iprocslow>;
210 clock-names = "apb_pclk";
214 compatible = "arm,mmu-500";
215 reg = <0x64000000 0x40000>;
216 #global-interrupts = <2>;
217 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
254 gic: interrupt-controller@65210000 {
255 compatible = "arm,gic-400";
256 #interrupt-cells = <3>;
257 interrupt-controller;
258 reg = <0x65210000 0x1000>,
262 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
263 IRQ_TYPE_LEVEL_HIGH)>;
266 timer0: timer@66030000 {
267 compatible = "arm,sp804", "arm,primecell";
268 reg = <0x66030000 0x1000>;
269 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&iprocslow>,
273 clock-names = "timer1", "timer2", "apb_pclk";
276 timer1: timer@66040000 {
277 compatible = "arm,sp804", "arm,primecell";
278 reg = <0x66040000 0x1000>;
279 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&iprocslow>,
283 clock-names = "timer1", "timer2", "apb_pclk";
286 timer2: timer@66050000 {
287 compatible = "arm,sp804", "arm,primecell";
288 reg = <0x66050000 0x1000>;
289 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&iprocslow>,
293 clock-names = "timer1", "timer2", "apb_pclk";
296 timer3: timer@66060000 {
297 compatible = "arm,sp804", "arm,primecell";
298 reg = <0x66060000 0x1000>;
299 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&iprocslow>,
303 clock-names = "timer1", "timer2", "apb_pclk";
307 compatible = "brcm,iproc-i2c";
308 reg = <0x66080000 0x100>;
309 #address-cells = <1>;
311 interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
312 clock-frequency = <100000>;
316 wdt0: watchdog@66090000 {
317 compatible = "arm,sp805", "arm,primecell";
318 reg = <0x66090000 0x1000>;
319 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&iprocslow>, <&iprocslow>;
321 clock-names = "wdogclk", "apb_pclk";
325 compatible = "brcm,iproc-i2c";
326 reg = <0x660b0000 0x100>;
327 #address-cells = <1>;
329 interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
330 clock-frequency = <100000>;
334 uart3: serial@66130000 {
335 compatible = "snps,dw-apb-uart";
336 reg = <0x66130000 0x100>;
337 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
345 compatible = "arm,pl022", "arm,primecell";
346 reg = <0x66180000 0x1000>;
347 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&iprocslow>, <&iprocslow>;
349 clock-names = "spiclk", "apb_pclk";
350 #address-cells = <1>;
356 compatible = "arm,pl022", "arm,primecell";
357 reg = <0x66190000 0x1000>;
358 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&iprocslow>, <&iprocslow>;
360 clock-names = "spiclk", "apb_pclk";
361 #address-cells = <1>;
366 hwrng: hwrng@66220000 {
367 compatible = "brcm,iproc-rng200";
368 reg = <0x66220000 0x28>;
371 sdio0: sdhci@66420000 {
372 compatible = "brcm,sdhci-iproc-cygnus";
373 reg = <0x66420000 0x100>;
374 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
380 sdio1: sdhci@66430000 {
381 compatible = "brcm,sdhci-iproc-cygnus";
382 reg = <0x66430000 0x100>;
383 interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
389 nand: nand@66460000 {
390 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
391 reg = <0x66460000 0x600>,
394 reg-names = "nand", "iproc-idm", "iproc-ext";
395 interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
397 #address-cells = <1>;