arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ARM Ltd. Fast Models
   4  *
   5  * Architecture Envelope Model (AEM) ARMv8-A
   6  * ARMAEMv8AMPCT
   7  *
   8  * RTSM_VE_AEMv8A.lisa
   9  */
  10
  11 /dts-v1/;
  12
  13 /memreserve/ 0x80000000 0x00010000;
  14
  15 / {
  16         model = "RTSM_VE_AEMv8A";
  17         compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         chosen { };
  23
  24         aliases {
  25                 serial0 = &v2m_serial0;
  26                 serial1 = &v2m_serial1;
  27                 serial2 = &v2m_serial2;
  28                 serial3 = &v2m_serial3;
  29         };
  30
  31         cpus {
  32                 #address-cells = <2>;
  33                 #size-cells = <0>;
  34
  35                 cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,armv8";
  38                         reg = <0x0 0x0>;
  39                         enable-method = "spin-table";
  40                         cpu-release-addr = <0x0 0x8000fff8>;
  41                         next-level-cache = <&L2_0>;
  42                 };
  43                 cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,armv8";
  46                         reg = <0x0 0x1>;
  47                         enable-method = "spin-table";
  48                         cpu-release-addr = <0x0 0x8000fff8>;
  49                         next-level-cache = <&L2_0>;
  50                 };
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,armv8";
  54                         reg = <0x0 0x2>;
  55                         enable-method = "spin-table";
  56                         cpu-release-addr = <0x0 0x8000fff8>;
  57                         next-level-cache = <&L2_0>;
  58                 };
  59                 cpu@3 {
  60                         device_type = "cpu";
  61                         compatible = "arm,armv8";
  62                         reg = <0x0 0x3>;
  63                         enable-method = "spin-table";
  64                         cpu-release-addr = <0x0 0x8000fff8>;
  65                         next-level-cache = <&L2_0>;
  66                 };
  67
  68                 L2_0: l2-cache0 {
  69                         compatible = "cache";
  70                 };
  71         };
  72
  73         memory@80000000 {
  74                 device_type = "memory";
  75                 reg = <0x00000000 0x80000000 0 0x80000000>,
  76                       <0x00000008 0x80000000 0 0x80000000>;
  77         };
  78
  79         gic: interrupt-controller@2c001000 {
  80                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  81                 #interrupt-cells = <3>;
  82                 #address-cells = <0>;
  83                 interrupt-controller;
  84                 reg = <0x0 0x2c001000 0 0x1000>,
  85                       <0x0 0x2c002000 0 0x2000>,
  86                       <0x0 0x2c004000 0 0x2000>,
  87                       <0x0 0x2c006000 0 0x2000>;
  88                 interrupts = <1 9 0xf04>;
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 interrupts = <1 13 0xf08>,
  94                              <1 14 0xf08>,
  95                              <1 11 0xf08>,
  96                              <1 10 0xf08>;
  97                 clock-frequency = <100000000>;
  98         };
  99
 100         pmu {
 101                 compatible = "arm,armv8-pmuv3";
 102                 interrupts = <0 60 4>,
 103                              <0 61 4>,
 104                              <0 62 4>,
 105                              <0 63 4>;
 106         };
 107
 108         smb@8000000 {
 109                 compatible = "simple-bus";
 110
 111                 #address-cells = <2>;
 112                 #size-cells = <1>;
 113                 ranges = <0 0 0 0x08000000 0x04000000>,
 114                          <1 0 0 0x14000000 0x04000000>,
 115                          <2 0 0 0x18000000 0x04000000>,
 116                          <3 0 0 0x1c000000 0x04000000>,
 117                          <4 0 0 0x0c000000 0x04000000>,
 118                          <5 0 0 0x10000000 0x04000000>;
 119
 120                 #interrupt-cells = <1>;
 121                 interrupt-map-mask = <0 0 63>;
 122                 interrupt-map = <0 0  0 &gic 0  0 4>,
 123                                 <0 0  1 &gic 0  1 4>,
 124                                 <0 0  2 &gic 0  2 4>,
 125                                 <0 0  3 &gic 0  3 4>,
 126                                 <0 0  4 &gic 0  4 4>,
 127                                 <0 0  5 &gic 0  5 4>,
 128                                 <0 0  6 &gic 0  6 4>,
 129                                 <0 0  7 &gic 0  7 4>,
 130                                 <0 0  8 &gic 0  8 4>,
 131                                 <0 0  9 &gic 0  9 4>,
 132                                 <0 0 10 &gic 0 10 4>,
 133                                 <0 0 11 &gic 0 11 4>,
 134                                 <0 0 12 &gic 0 12 4>,
 135                                 <0 0 13 &gic 0 13 4>,
 136                                 <0 0 14 &gic 0 14 4>,
 137                                 <0 0 15 &gic 0 15 4>,
 138                                 <0 0 16 &gic 0 16 4>,
 139                                 <0 0 17 &gic 0 17 4>,
 140                                 <0 0 18 &gic 0 18 4>,
 141                                 <0 0 19 &gic 0 19 4>,
 142                                 <0 0 20 &gic 0 20 4>,
 143                                 <0 0 21 &gic 0 21 4>,
 144                                 <0 0 22 &gic 0 22 4>,
 145                                 <0 0 23 &gic 0 23 4>,
 146                                 <0 0 24 &gic 0 24 4>,
 147                                 <0 0 25 &gic 0 25 4>,
 148                                 <0 0 26 &gic 0 26 4>,
 149                                 <0 0 27 &gic 0 27 4>,
 150                                 <0 0 28 &gic 0 28 4>,
 151                                 <0 0 29 &gic 0 29 4>,
 152                                 <0 0 30 &gic 0 30 4>,
 153                                 <0 0 31 &gic 0 31 4>,
 154                                 <0 0 32 &gic 0 32 4>,
 155                                 <0 0 33 &gic 0 33 4>,
 156                                 <0 0 34 &gic 0 34 4>,
 157                                 <0 0 35 &gic 0 35 4>,
 158                                 <0 0 36 &gic 0 36 4>,
 159                                 <0 0 37 &gic 0 37 4>,
 160                                 <0 0 38 &gic 0 38 4>,
 161                                 <0 0 39 &gic 0 39 4>,
 162                                 <0 0 40 &gic 0 40 4>,
 163                                 <0 0 41 &gic 0 41 4>,
 164                                 <0 0 42 &gic 0 42 4>;
 165
 166                 /include/ "rtsm_ve-motherboard.dtsi"
 167         };
 168 };