arch/arm64/boot/dts/arm/juno-motherboard.dtsi

   1 /*
   2  * ARM Juno Platform motherboard peripherals
   3  *
   4  * Copyright (c) 2013-2014 ARM Ltd
   5  *
   6  * This file is licensed under a dual GPLv2 or BSD license.
   7  *
   8  */
   9
  10                 mb_clk24mhz: clk24mhz {
  11                         compatible = "fixed-clock";
  12                         #clock-cells = <0>;
  13                         clock-frequency = <24000000>;
  14                         clock-output-names = "juno_mb:clk24mhz";
  15                 };
  16
  17                 mb_clk25mhz: clk25mhz {
  18                         compatible = "fixed-clock";
  19                         #clock-cells = <0>;
  20                         clock-frequency = <25000000>;
  21                         clock-output-names = "juno_mb:clk25mhz";
  22                 };
  23
  24                 v2m_refclk1mhz: refclk1mhz {
  25                         compatible = "fixed-clock";
  26                         #clock-cells = <0>;
  27                         clock-frequency = <1000000>;
  28                         clock-output-names = "juno_mb:refclk1mhz";
  29                 };
  30
  31                 v2m_refclk32khz: refclk32khz {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                         clock-frequency = <32768>;
  35                         clock-output-names = "juno_mb:refclk32khz";
  36                 };
  37
  38                 motherboard {
  39                         compatible = "arm,vexpress,v2p-p1", "simple-bus";
  40                         #address-cells = <2>;  /* SMB chipselect number and offset */
  41                         #size-cells = <1>;
  42                         #interrupt-cells = <1>;
  43                         ranges;
  44                         model = "V2M-Juno";
  45                         arm,hbi = <0x252>;
  46                         arm,vexpress,site = <0>;
  47                         arm,v2m-memory-map = "rs1";
  48
  49                         mb_fixed_3v3: mcc-sb-3v3 {
  50                                 compatible = "regulator-fixed";
  51                                 regulator-name = "MCC_SB_3V3";
  52                                 regulator-min-microvolt = <3300000>;
  53                                 regulator-max-microvolt = <3300000>;
  54                                 regulator-always-on;
  55                         };
  56
  57                         gpio_keys {
  58                                 compatible = "gpio-keys";
  59
  60                                 power-button {
  61                                         debounce_interval = <50>;
  62                                         wakeup-source;
  63                                         linux,code = <116>;
  64                                         label = "POWER";
  65                                         gpios = <&iofpga_gpio0 0 0x4>;
  66                                 };
  67                                 home-button {
  68                                         debounce_interval = <50>;
  69                                         wakeup-source;
  70                                         linux,code = <102>;
  71                                         label = "HOME";
  72                                         gpios = <&iofpga_gpio0 1 0x4>;
  73                                 };
  74                                 rlock-button {
  75                                         debounce_interval = <50>;
  76                                         wakeup-source;
  77                                         linux,code = <152>;
  78                                         label = "RLOCK";
  79                                         gpios = <&iofpga_gpio0 2 0x4>;
  80                                 };
  81                                 vol-up-button {
  82                                         debounce_interval = <50>;
  83                                         wakeup-source;
  84                                         linux,code = <115>;
  85                                         label = "VOL+";
  86                                         gpios = <&iofpga_gpio0 3 0x4>;
  87                                 };
  88                                 vol-down-button {
  89                                         debounce_interval = <50>;
  90                                         wakeup-source;
  91                                         linux,code = <114>;
  92                                         label = "VOL-";
  93                                         gpios = <&iofpga_gpio0 4 0x4>;
  94                                 };
  95                                 nmi-button {
  96                                         debounce_interval = <50>;
  97                                         wakeup-source;
  98                                         linux,code = <99>;
  99                                         label = "NMI";
 100                                         gpios = <&iofpga_gpio0 5 0x4>;
 101                                 };
 102                         };
 103
 104                         flash@0,00000000 {
 105                                 /* 2 * 32MiB NOR Flash memory mounted on CS0 */
 106                                 compatible = "arm,vexpress-flash", "cfi-flash";
 107                                 linux,part-probe = "afs";
 108                                 reg = <0 0x00000000 0x04000000>;
 109                                 bank-width = <4>;
 110                                 /*
 111                                  * Unfortunately, accessing the flash disturbs
 112                                  * the CPU idle states (suspend) and CPU
 113                                  * hotplug of the platform. For this reason,
 114                                  * flash hardware access is disabled by default.
 115                                  */
 116                                 status = "disabled";
 117                         };
 118
 119                         ethernet@2,00000000 {
 120                                 compatible = "smsc,lan9118", "smsc,lan9115";
 121                                 reg = <2 0x00000000 0x10000>;
 122                                 interrupts = <3>;
 123                                 phy-mode = "mii";
 124                                 reg-io-width = <4>;
 125                                 smsc,irq-active-high;
 126                                 smsc,irq-push-pull;
 127                                 clocks = <&mb_clk25mhz>;
 128                                 vdd33a-supply = <&mb_fixed_3v3>;
 129                                 vddvario-supply = <&mb_fixed_3v3>;
 130                         };
 131
 132                         iofpga@3,00000000 {
 133                                 compatible = "simple-bus";
 134                                 #address-cells = <1>;
 135                                 #size-cells = <1>;
 136                                 ranges = <0 3 0 0x200000>;
 137
 138                                 v2m_sysctl: sysctl@20000 {
 139                                         compatible = "arm,sp810", "arm,primecell";
 140                                         reg = <0x020000 0x1000>;
 141                                         clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&mb_clk24mhz>;
 142                                         clock-names = "refclk", "timclk", "apb_pclk";
 143                                         #clock-cells = <1>;
 144                                         clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
 145                                         assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
 146                                         assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
 147                                 };
 148
 149                                 apbregs@10000 {
 150                                         compatible = "syscon", "simple-mfd";
 151                                         reg = <0x010000 0x1000>;
 152
 153                                         led0 {
 154                                                 compatible = "register-bit-led";
 155                                                 offset = <0x08>;
 156                                                 mask = <0x01>;
 157                                                 label = "vexpress:0";
 158                                                 linux,default-trigger = "heartbeat";
 159                                                 default-state = "on";
 160                                         };
 161                                         led1 {
 162                                                 compatible = "register-bit-led";
 163                                                 offset = <0x08>;
 164                                                 mask = <0x02>;
 165                                                 label = "vexpress:1";
 166                                                 linux,default-trigger = "mmc0";
 167                                                 default-state = "off";
 168                                         };
 169                                         led2 {
 170                                                 compatible = "register-bit-led";
 171                                                 offset = <0x08>;
 172                                                 mask = <0x04>;
 173                                                 label = "vexpress:2";
 174                                                 linux,default-trigger = "cpu0";
 175                                                 default-state = "off";
 176                                         };
 177                                         led3 {
 178                                                 compatible = "register-bit-led";
 179                                                 offset = <0x08>;
 180                                                 mask = <0x08>;
 181                                                 label = "vexpress:3";
 182                                                 linux,default-trigger = "cpu1";
 183                                                 default-state = "off";
 184                                         };
 185                                         led4 {
 186                                                 compatible = "register-bit-led";
 187                                                 offset = <0x08>;
 188                                                 mask = <0x10>;
 189                                                 label = "vexpress:4";
 190                                                 linux,default-trigger = "cpu2";
 191                                                 default-state = "off";
 192                                         };
 193                                         led5 {
 194                                                 compatible = "register-bit-led";
 195                                                 offset = <0x08>;
 196                                                 mask = <0x20>;
 197                                                 label = "vexpress:5";
 198                                                 linux,default-trigger = "cpu3";
 199                                                 default-state = "off";
 200                                         };
 201                                         led6 {
 202                                                 compatible = "register-bit-led";
 203                                                 offset = <0x08>;
 204                                                 mask = <0x40>;
 205                                                 label = "vexpress:6";
 206                                                 default-state = "off";
 207                                         };
 208                                         led7 {
 209                                                 compatible = "register-bit-led";
 210                                                 offset = <0x08>;
 211                                                 mask = <0x80>;
 212                                                 label = "vexpress:7";
 213                                                 default-state = "off";
 214                                         };
 215                                 };
 216
 217                                 mmci@50000 {
 218                                         compatible = "arm,pl180", "arm,primecell";
 219                                         reg = <0x050000 0x1000>;
 220                                         interrupts = <5>;
 221                                         /* cd-gpios = <&v2m_mmc_gpios 0 0>;
 222                                         wp-gpios = <&v2m_mmc_gpios 1 0>; */
 223                                         max-frequency = <12000000>;
 224                                         vmmc-supply = <&mb_fixed_3v3>;
 225                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 226                                         clock-names = "mclk", "apb_pclk";
 227                                 };
 228
 229                                 kmi@60000 {
 230                                         compatible = "arm,pl050", "arm,primecell";
 231                                         reg = <0x060000 0x1000>;
 232                                         interrupts = <8>;
 233                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 234                                         clock-names = "KMIREFCLK", "apb_pclk";
 235                                 };
 236
 237                                 kmi@70000 {
 238                                         compatible = "arm,pl050", "arm,primecell";
 239                                         reg = <0x070000 0x1000>;
 240                                         interrupts = <8>;
 241                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 242                                         clock-names = "KMIREFCLK", "apb_pclk";
 243                                 };
 244
 245                                 wdt@f0000 {
 246                                         compatible = "arm,sp805", "arm,primecell";
 247                                         reg = <0x0f0000 0x10000>;
 248                                         interrupts = <7>;
 249                                         clocks = <&mb_clk24mhz>, <&soc_smc50mhz>;
 250                                         clock-names = "wdogclk", "apb_pclk";
 251                                 };
 252
 253                                 v2m_timer01: timer@110000 {
 254                                         compatible = "arm,sp804", "arm,primecell";
 255                                         reg = <0x110000 0x10000>;
 256                                         interrupts = <9>;
 257                                         clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&mb_clk24mhz>;
 258                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 259                                 };
 260
 261                                 v2m_timer23: timer@120000 {
 262                                         compatible = "arm,sp804", "arm,primecell";
 263                                         reg = <0x120000 0x10000>;
 264                                         interrupts = <9>;
 265                                         clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&mb_clk24mhz>;
 266                                         clock-names = "timclken1", "timclken2", "apb_pclk";
 267                                 };
 268
 269                                 rtc@170000 {
 270                                         compatible = "arm,pl031", "arm,primecell";
 271                                         reg = <0x170000 0x10000>;
 272                                         interrupts = <0>;
 273                                         clocks = <&soc_smc50mhz>;
 274                                         clock-names = "apb_pclk";
 275                                 };
 276
 277                                 iofpga_gpio0: gpio@1d0000 {
 278                                         compatible = "arm,pl061", "arm,primecell";
 279                                         reg = <0x1d0000 0x1000>;
 280                                         interrupts = <6>;
 281                                         clocks = <&soc_smc50mhz>;
 282                                         clock-names = "apb_pclk";
 283                                         gpio-controller;
 284                                         #gpio-cells = <2>;
 285                                         interrupt-controller;
 286                                         #interrupt-cells = <2>;
 287                                 };
 288                         };
 289                 };